MAXIM MAX1425CAI

19-1597; Rev 1; 7/11
10-Bit, 20Msps ADC
Features
o Differential Inputs for High Common-Mode
Noise Rejection
o Signal-to-Noise Ratio
61dB (at fIN = 2MHz)
59.3dB (at fIN = 10MHz)
o Internal +2.5V Reference
o 150MHz Input Bandwidth
o Wide ±2V Input Range
o Low Power Consumption: 172mW
o Separate Digital Supply Input for 3V Logic
Compatibility
o Single +5V Supply Operation Possible
Ordering Information
PART
TEMP. RANGE
MAX1425CAI+
0°C to +70°C
28 SSOP
MAX1425EAI+
-40°C to +85°C
28 SSOP
+Denotes a lead(Pb)-free/RoHS-compliant package.
Devices are also available in a tape-and-reel packaging.
Specify tape and reel by adding “T” to the number when ordering.
Applications
Medical Ultrasound Imaging
CCD Pixel Processing
IR Focal Plane Array
Radar
IF and Baseband Digitization
Set-Top Boxes
Pin Configuration
TOP VIEW
+
AGND 1
28 D0
AVDD 2
27 D1
REFP 3
26 D2
REFIN 4
25 D3
REFN 5
Functional Diagram
CLK
MAX1425
T/H
PIPELINE ADC
INN
REF
OUTPUT
DRIVERS
REF SYSTEM +
BIAS
REFIN REFP
CML REFN
AVDD
AGND
INTERFACE
INP
PIN-PACKAGE
OE/PD
CML 6
24 D4
MAX1425
23 DGND
AGND 7
22 DVDD
AVDD 8
21 DGND
INP 9
20 DVDD
INN 10
19 D5
CMLP 11
18 D6
DVDD
CMLN 12
17 D7
DGND
CLK 13
16 D8
OE/PD 14
15 D9
D9–D0
SSOP
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1
MAX1425
General Description
The MAX1425 10-bit, monolithic analog-to-digital converter (ADC) is capable of a 20Msps sampling rate. This
device features an internal track-and-hold (T/H) amplifier
for excellent dynamic performance; at the same time, it
minimizes the number of external components. Low
input capacitance of only 8pF minimizes input drive
requirements. A wide input bandwidth (up to 150MHz)
makes this device suitable for digital RF/IF downconverter applications employing undersampling techniques.
The MAX1425 employs a differential pipelined architecture with a wideband T/H amplifier to maximize throughput while limiting power consumption to only 172mW.
The MAX1425 generates an internal +2.5V reference
that supplies three additional reference voltages
(+3.25V, +2.25V, and +1.25V). These reference voltages provide a differential input range of +2V to -2V.
The analog inputs are biased internally to correct the
DC level, eliminating the need for external biasing on
AC-coupled applications.
A separate +3V digital logic supply input allows for
separation of digital and analog circuitry. The output
data is in two’s complement format. The MAX1425 is
available in the space-saving 28-pin SSOP package.
For a pin-compatible version at a lower data rate, refer
to the MAX1426 data sheet. For a higher data rate, refer
to the MAX1424 data sheet.
MAX1425
10-Bit, 20Msps ADC
ABSOLUTE MAXIMUM RATINGS
AVDD to AGND ........................................................ -0.3V to +6V
DVDD to DGND ....................................................... -0.3V to +6V
AVDD to DGND ........................................................ -0.3V to +6V
DGND to AGND ................................................................. ±0.3V
REFP, REFIN, REFN, CMLN, CMLP,
CML, INP, INN ....................(VAGND - 0.3V) to (VAVDD + 0.3V)
CLK, OE/PD, D0–D9 ...............(VDGND - 0.3V) to (VDVDD + 0.3V)
Continuous Power Dissipation (TA = +70°C)
28-Pin SSOP (derated 9.5mW/°C above +70°C) .........762mW
Operating Temperature Ranges
MAX1425CAI ..................................................... 0°C to +70°C
MAX1425EAI................................................... -40°C to +85°C
Junction Temperature ..................................................... +150°C
Storage Temperature Range ............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VAVDD = VCMLP = +5V, VDVDD = +3.3V, VCMLN = VAGND = VDGND = 0V, internal reference, digital output load = 35pF, fCLK = 20MHz
(50% duty cycle), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
1
LSB
1.5
LSB
ACCURACY
10
Resolution
RES
Differential Nonlinearity
DNL
-1
Integral Nonlinearity
INL
-1.5
±0.3
(Note 1)
-3
±1.0
3
Internal reference (Note 1)
-10
±5
10
External reference (REFIN) (Note 2)
-5
±2
5
External reference (REFP, CML, REFN)
(Note 3)
-5
±3
5
(Note 4)
-5
±2
5
f = 2MHz
60
61
f = 10MHz
56
59
f = 2MHz
70
72
f = 10MHz
64
69
No Missing Codes
Midscale Offset
Gain Error
Power-Supply Rejection Ratio
Bits
Guaranteed monotonic
MSO
GE
PSRR
%FSR
%FSR
mV/V
DYNAMIC PERFORMANCE (AIN = -1.0dBFS)
Signal-to-Noise Ratio
SNR
Spurious-Free Dynamic Range
SFDR
Total Harmonic Distortion
(first five harmonics)
THD
Signal-to-Noise and Distortion
SINAD
Effective Number of Bits
ENOB
Intermodulation Distortion
2
IMD
dB
dB
f = 2MHz
-70
-67
f = 10MHz
-69
-64
f = 2MHz
59
61
f = 10MHz
55
59
f = 2MHz
9.3
9.7
f = 10MHz
8.8
9.5
f1 = 10.17MHz, f2 = 10.19MHz
(-7dB FS, each tone) (Note 5)
-70
_______________________________________________________________________________________
dB
dB
Bits
dBc
10-Bit, 20Msps ADC
(VAVDD = VCMLP = +5V, VDVDD = +3.3V, VCMLN = VAGND = VDGND = 0V, internal reference, digital output load = 35pF, fCLK = 20MHz
(50% duty cycle), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG INPUT (INP, INN, CML)
Input Resistance
RIN
Either input to ground
Input Capacitance
CIN
Either input to ground
Input Common-Mode Voltage
Range
VCMVR
3.5
kΩ
8
pF
2.25
±10%
V
VINP - VINN
±2
V
CML (Note 6)
Differential Input Range
DR
Small-Signal Bandwidth
SSBW
(Note 7)
400
MHz
Large-Signal Bandwidth
LSBW
(Note 7)
150
MHz
REFERENCE (VREFIN = 0; REFP, REFN, CML applied externally)
6.5
Input Resistance
RIN
REFIN (Note 8)
Input Capacitance
CIN
REFIN
10
pF
VREFP - VREFN
2.0
V
Differential Reference
Input Current
IIN
REFP, CML, REFN
Input Capacitance
CIN
REFP, CML, REFN
kΩ
-325
325
µA
15
pF
REFP Input Range
3.25
±10%
V
CML Input Range
2.25
±10%
V
REFN Input Range
1.25
±10%
V
REFERENCE OUTPUTS (REFP, CML, REFN; external +2.5V reference)
Positive Reference Voltage
VREFP
3.25
V
Common-Mode Reference
Voltage
VCML
2.25
V
Negative Reference Input
Voltage
VREFN
1.25
V
Differential Reference
VREFP - VREFN, TA = +25°C
1.9
Differential Reference
Temperature Coefficient
2.0
2.1
V
±50
ppm/°C
REFERENCE OUTPUTS (REFP, CML, REFN; internal +2.5V reference)
Positive Reference
VREFP
(Note 1)
3.25
V
Common-Mode Reference
Voltage
VCML
(Note 1)
2.25
V
Negative Reference
VREFN
(Note 1)
Differential Reference
Differential Reference
Temperature Coefficient
VREFP - VREFN, TA = +25°C
1.25
1.8
2
±150
V
2.2
V
ppm/°C
_______________________________________________________________________________________
3
MAX1425
ELECTRICAL CHARACTERISTICS (continued)
MAX1425
10-Bit, 20Msps ADC
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VCMLP = +5V, VDVDD = +3.3V, VCMLN = VAGND = VDGND = 0V, internal reference, digital output load = 35pF, fCLK = 20MHz
(50% duty cycle), TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
POWER SUPPLY
Analog Supply Voltage
VAVDD
4.75
5.00
5.25
Digital Supply Voltage
VDVDD
2.7
3.3
5.5
V
Analog Supply Current
IAVDD
31
38
mA
REFIN = AGND
26
35
mA
OE/PD = DVDD
VDVDD = 3.3V
0.6
1
mA
5.3
9
VDVDD = 5.0V
8.5
14
OE/PD = DVDD
90
150
µA
172
220
mW
Analog Supply Current with
Internal Reference in Shutdown
Analog Shutdown Current
Digital Supply Current
IDVDD
Digital Shutdown Current
Power Dissipation
PD
mA
DIGITAL INPUTS (CLK, OE/PD)
Input Logic High
Input Logic Low
VIH
VIL
VDVDD > 4.75V
2.4
VDVDD < 4.75V
0.7 ·
VDVDD
VDVDD > 4.75V
0.8
VDVDD < 4.75V
0.3 ·
VDVDD
V
VDVDD = 5.25V
Input Current Leakage
V
ICLK
-10
10
µA
IOE/PD
-20
20
µA
Input Capacitance
10
pF
DIGITAL OUTPUTS (D0–D9)
Output Logic High
VOH
IOH = -200µA, VDVDD = 2.7V
Output Logic Low
VOL
IOL = 200µA, VDVDD = 2.7V
Three-State Leakage
VDVDD = 5.25V, OE/PD = DVDD
Three-State Capacitance
OE/PD = DVDD
VDVDD
- 0.5
VDV
DD
-10
V
0.5
V
10
µA
10
pF
TIMING CHARACTERISTICS
Conversion Rate
CONV
Clock Frequency
fCLK
Clock High
tCH
Figure 4
20
Clock Low
tCL
Figure 4
20
Pipeline Delay (Latency)
Aperture Delay
Aperture Jitter
Data Output Delay
Bus Enable
Bus Disable
4
tAD
tAJ
tOD
0.1
5
20
MHz
20
MHz
25
30
ns
25
30
ns
25
20
20
cycles
ns
ps
ns
ns
ns
5.5
5
7
20
10
10
_______________________________________________________________________________________
10-Bit, 20Msps ADC
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
MAX1425
ELECTRICAL CHARACTERISTICS (continued)
Internal reference, REFIN bypassed to AGND with a 0.1µF capacitor.
External +2.5V reference applied to REFIN.
Internal reference disabled. VREFIN = 0, VREFP = 3.25V, VCML = 2.25V, and VREFN = 1.25V.
Measured as the ratio of the change in midscale offset voltage for a ±5% change in VAVDD using the internal reference.
IMD is measured with respect to either of the fundamental tones.
Specifies the common-mode range of the differential input signal supplied to the MAX1425.
Defined as the input frequency at which the fundamental component of the output spectrum is attenuated by 3dB.
VREFIN is internally biased to +2.5V through a 5kΩ resistor.
Typical Operating Characteristics
(VAVDD = VCMLP = +5V, VDVDD = +3.3V, VCMLN = VAGND = 0V, internal reference, digital output load = 35pF, fCLK = 20Msps (50%
duty cycle), for dynamic performance 0dB is full scale, TA = +25°C, unless otherwise noted.)
INTEGRAL NONLINEARITY vs. CODE
fINP = 2MHz
0.4
0.4
-1.0
AMPLITUDE (dB)
-2.0
0.2
0.2
0
DNL (LSB)
-0.2
-0.4
0
-0.2
-0.6
-4.0
-5.0
-6.0
-0.8
-0.4
-7.0
-1.0
-1.2
-8.0
-0.6
0
200
400
600
1000
800
-40
200
400
600
800
0.01
1000
0.1
1
10
100
1000 10,000
CODE
BANDWIDTH (MHz)
INTERMODULATION DISTORTION
vs. FREQUENCY
SIGNAL-TO-NOISE PLUS DISTORTION
vs. POWER (fIN = 2.003MHz)
SIGNAL-TO-NOISE RATIO PLUS DISTORTION
vs. POWER (fIN = 5.009MHz)
60
MAX1425-05
60
MAX1425-04
CLK == 20MHz
ffCLK
20MHz
f1 == 5.01MHz
f1
5.01MHz
f2 == 5.03MHz
f2
5.03MHz
-20
0
CODE
0
40
40
-60
-80
SNDR (dB)
SINAD (dB)
MAGNITUDE (dB)
-3.0
20
20
-100
MAX1425-06
INL (LSB)
0
MAX1425-03
0.6
0.6
MAX1425-02
fINP = 2MHz
MAX1425-01
0.8
ANALOG INPUT BANDWIDTH
(FULL POWER)
DIFFERENTIAL NONLINEARITY vs. CODE
-120
-140
0
0
0
1
2
3
4
5
6
7
FREQUENCY (MHz)
8
9
10
-60
-45
-30
INPUT (dB)
-15
0
-60
-45
-30
-15
0
INPUT (dB)
_______________________________________________________________________________________
5
Typical Operating Characteristics (continued)
(VAVDD = VCMLP = +5V, VDVDD = +3.3V, VCMLN = VAGND = 0V, internal reference, digital output load = 35pF, fCLK = 20Msps (50%
duty cycle), for dynamic performance 0dB is full scale, TA = +25°C, unless otherwise noted.)
SIGNAL-TO-NOISE RATIO
vs. POWER (fIN = 2.003MHz)
50
40
30
40
SNR (dB)
SNR (dB)
30
30
20
20
20
10
10
10
0
0
-30
-15
0
-60
0
-45
-30
-15
INPUT (dB)
INPUT (dB)
SIGNAL-TO-NOISE RATIO
vs. POWER (fIN = 9.884MHz)
SPURIOUS-FREE DYNAMIC RANGE
vs. POWER (fIN = 2.003MHz)
SFDR (dB)
SNR (dB)
20
-60
-45
-30
-15
60
50
50
40
30
20
20
10
10
0
-60
-45
-30
-15
0
-60
0
MAX1425-14
MAX1425-13
0
THD (dB)
THD (dB)
-40
-45
-30
INPUT (dB)
-15
0
-40
-60
-80
-80
0
0
-20
-60
20
-15
TOTAL HARMONIC DISTORTION
vs. POWER (fIN = 5.009MHz)
-20
40
-30
INPUT (dB)
TOTAL HARMONIC DISTORTION
vs. POWER (fIN = 2.003MHz)
SPURIOUS-FREE DYNAMIC RANGE
vs. POWER (fIN = 9.984MHz)
-60
-45
INPUT (dB)
60
0
40
30
INPUT (dB)
80
-15
70
60
0
-30
80
0
0
-45
SPURIOUS-FREE DYNAMIC RANGE
vs. POWER (fIN = 5.009MHz)
70
40
-60
INPUT (dB)
80
MAX1425-10
60
0
MAX1425-15
-45
SFDR (dB)
-60
MAX1425-11
SINAD (dB)
40
6
50
MAX1425-12
50
60
MAX1425-08
60
MAX1425-07
60
SIGNAL-TO-NOISE RATIO
vs. POWER (fIN = 5.009MHz)
MAX1425-09
SIGNAL-TO-NOISE PLUS DISTORTION
vs. POWER (fIN = 9.884MHz)
SFDR (dB)
MAX1425
10-Bit, 20Msps ADC
-60
-45
-30
INPUT (dB)
-15
0
-60
-45
-30
INPUT (dB)
_______________________________________________________________________________________
-15
0
10-Bit, 20Msps ADC
EFFECTIVE NUMBER OF BITS
vs. POWER (fIN = 2.003MHz)
8
-40
-60
8
ENOB (bits)
ENOB (bits)
-20
6
4
2
0
-80
-45
-30
-15
0
-60
0
4
-45
-30
-15
0
-60
-45
-30
-15
0
INPUT (dB)
INPUT (dB)
INPUT (dB)
EFFECTIVE NUMBER OF BITS
vs. POWER (fIN = 9.884MHz)
EFFECTIVE NUMBER OF BITS
vs. INPUT FREQUENCY
SIGNAL-TO-NOISE RATIO
vs. INPUT FREQUENCY
10.0
MAX1425-19
10
8
60
MAX1425-21
-60
6
2
MAX1425-20
THD (dB)
10
MAX1425-17
10
MAX1425-16
0
EFFECTIVE NUMBER OF BITS
vs. POWER (fIN = 5.009MHz)
MAX1425-18
TOTAL HARMONIC DISTORTION
vs. POWER (fIN = 9.884MHz)
9.6
4
9.2
SNR (dB)
ENOB (bits)
ENOB (bits)
59
6
8.8
58
2
8.4
-45
-30
-15
0
2
4
6
8
INPUT (dB)
INPUT FREQUENCY (MHz)
TOTAL HARMONIC DISTORTION
vs. INPUT FREQUENCY
SIGNAL-TO-NOISE PLUS DISTORTION
vs. INPUT FREQUENCY
-65
2
10
10
-20
-40
MAGNITUDE (dB)
SINAD (dB)
8
FFT PLOT (fIN = 2MHz)
59
58
-75
6
0
60
-70
4
INPUT FREQUENCY (MHz)
MAX1425-23
61
MAX1425-22
-60
THD (dB)
57
8.0
-60
MAX1425-24
0
-60
-80
-100
-120
-140
-80
57
2
4
6
8
INPUT FREQUENCY (MHz)
10
-160
2
4
6
8
INPUT FREQUENCY (MHz)
10
0
1
2
3
4
5
6
7
8
9
10
FREQUENCY (MHz)
_______________________________________________________________________________________
7
MAX1425
Typical Operating Characteristics (continued)
(VAVDD = VCMLP = +5V, VDVDD = +3.3V, VCMLN = VAGND = 0V, internal reference, digital output load = 35pF, fCLK = 20Msps (50%
duty cycle), for dynamic performance 0dB is full scale, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(VAVDD = VCMLP = +5V, VDVDD = +3.3V, VCMLN = VAGND = 0V, internal reference, digital output load = 35pF, fCLK = 20Msps (50%
duty cycle), for dynamic performance 0dB is full scale, TA = +25°C, unless otherwise noted.)
FFT PLOT (fIN = 5MHz)
FFT PLOT (fIN = 10MHz)
MAX1425-26
-20
-20
-40
MAGNITUDE (dB)
-60
-80
-40
-60
-80
-100
-100
-120
-120
-140
-140
2
3
4
5
6
7
8
9
10
1
2
3
4
5
6
7
8
9
FREQUENCY (MHz)
TOTAL SUPPLY CURRENT
vs. TEMPERATURE
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
MAX1425-27
48
SHUTDOWN
44
0
FREQUENCY (MHz)
40
0.75
2.18
0.70
2.16
0.65
OE/PD = 1
0.60
36
32
INTERNAL REFERENCE (V)
1
SHUTDOWN CURRENT (mA)
0
10
MAX1425-28
MAGNITUDE (dB)
0
MAX1425-25
0
SUPPLY CURRENT (mA)
MAX1425
10-Bit, 20Msps ADC
2.14
2.12
0.55
2.10
0.50
2.08
REFIN = AGND
28
-40
-15
10
35
TEMPERATURE (°C)
8
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
_______________________________________________________________________________________
10-Bit, 20Msps ADC
PIN
NAME
FUNCTION
1, 7
AGND
Analog Ground. Connect all return paths for analog signals to these pins.
2, 8
AVDD
Analog Supply Voltage Input. Bypass with a parallel combination of 2.2µF, 0.1µF, and 100pF capacitors
to AGND. Bypass each supply input to the closest AGND (e.g., capacitors between pins 1 and 2).
3
REFP
Positive Reference Output. Bypass to AGND with a 0.1µF capacitor. If the internal reference is
disabled, REFP can accept an external voltage.
4
REFIN
External Reference Input. Bypass to AGND with a 0.1µF capacitor. REFIN can be biased externally
to adjust the reference level and calibrate full-scale errors. To disable the internal reference, connect
REFIN to AGND.
5
REFN
Negative Reference Output. Bypass to AGND with a 0.1µF capacitor. REFN can accept an external
voltage when the internal reference is disabled (REFN = AGND).
6
CML
Common-Mode Level Input. Bypass to AGND with a 0.1µF capacitor. CML can accept an external
voltage when the internal reference is disabled (REFN = AGND).
9
INP
Positive Analog Signal Input
10
INN
Negative Analog Signal Input
11
CMLP
Common-Mode Level Positive Input. For AC applications, connect to AVDD to internally set the input
DC bias level. For DC-coupled applications, connect to AGND.
12
CMLN
Common-Mode Level Negative Input. Connect to AGND to internally set the input DC bias level for
both AC- and DC-coupled applications.
13
CLK
14
OE/PD
15
D9
16–19
D8–D5
Digital Data Outputs 8–5
20, 22
DVDD
Digital Supply Voltage Input. Bypass with 2.2µF and 0.1µF capacitors in parallel. Digital supply can
operate with voltages as low as +2.7V.
21, 23
DGND
Digital Ground
24–27
D4–D1
Digital Data Outputs 4–1
28
D0
Digital Data Output (LSB)
Clock Input. Clock frequency range from 0.1MHz to 20MHz.
Active-Low Output Enable and Power-Down Input. Digital outputs become high impedance and
device enters low-power mode when pin is high.
Digital Data Output (MSB)
_______________________________________________________________________________________
9
MAX1425
Pin Description
MAX1425
10-Bit, 20Msps ADC
Detailed Description
the residue by two and the next stage in the pipeline
performs a similar operation.
The MAX1425 uses a 10-stage, fully differential, pipelined
architecture (Figure 1) that allows for high-speed conversion while minimizing power consumption. Each sample
moves through a pipeline stage every half clock cycle.
Counting the delay through the output latch, there is a 5.5
clock-cycle latency.
A 2-bit flash ADC converts the input voltage to digital
code. A DAC converts the ADC result back into an analog voltage, which is subtracted from the held input signal. The resulting error signal is then multiplied by two,
and this product is passed along to the next pipeline
stage where the process is repeated. Digital error correction compensates for offsets and mismatches in each
pipeline stage and ensures no missing codes.
System Timing Requirements
Figure 3 shows the relationship between the clock
input, analog input, and data output. The MAX1425
samples the falling edge of the input clock. Output data
is valid on the rising edge of the input clock. The output
data has an internal latency of 5.5 clock cycles, as
shown. Figure 4 shows an output timing diagram that
specifies the relationship between the input clock parameters and the valid output data.
Analog Input and Internal Reference
The MAX1425 has an internal +2.5V reference used to
generate three reference levels: +3.25V, +2.25V, and
+1.25V corresponding to V REFP, V CML, and V REFN.
These reference voltages enable a ±2V input range.
Bypass all reference voltages with a 0.1µF capacitor.
The MAX1425 allows for three modes of reference
operation: an internal reference (default) mode, an
externally adjusted reference mode, or a full external
reference mode. The internal reference mode occurs
when no voltages are applied to REFIN, REFP, CML,
Internal Track-and-Hold Circuit
Figure 2 shows a simplified functional diagram of the
internal track-and-hold (T/H) circuit in both track mode
and hold mode. The fully differential circuit samples the
input signal onto the four capacitors C1a, C1b, C2a,
and C2b. Switches S2a and S2b set the common mode
for the amplifier input, and open before S1. When S1
opens, the input is sampled. Switches S3a and S3b
then connect capacitors C1a and C1b to the output of
the amplifier. Capacitors C2a and C2b are connected
either to REFN, REFP, or each other, depending on the
results of the flash ADC. The amplifier then multiplies
CML
S2a
INP
REFP
REFN
REFP
REFN
MDAC
VIN
Σ
T/H
x2
C1a
S3a
VOUT
C2a
S4a
S1
S4c
C2b
S4b
INN
C1b
FLASH
ADC
DAC
S2b
CML
a) TRACK MODE
2 BITS
CML
C1a
S3a
S2a
INP
VIN
C2a
S4a
STAGE 1
STAGE 2
REFP
REFN
REFP
REFN
STAGE 10
S1
S4c
C2b
S4b
INN
DIGITAL CORRECTION LOGIC
S3b
C1b
S2b
10
CML
D [9:0]
b) HOLD MODE
Figure 2. Internal Track-and-Hold Circuit
Figure 1. Pipelined A/D Architecture (Block)
10
10-Bit, 20Msps ADC
MAX1425
5.5 CLOCK-CYCLE LATENCY
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
ANALOG INPUT
CLOCK INPUT
n-6
DATA OUTPUT
n-5
n-4
n-3
n-2
n-1
n
n+1
Figure 3. System Timing Diagram
Table 1. MAX1425 Output Code
tCLK
DIFFERENTIAL INPUT
tCI
tCH
+Full Scale
INPUT
CLK
tOD
OUTPUT
DATA
DATA 0
DATA 1
DATA 2
Figure 4. Output Timing Diagram
and REFN. In this mode, the voltages at these pins
are set to their nominal values (see Electrical
Characteristics). The reference voltage levels can be
adjusted externally by applying a voltage at REFIN.
This allows other input levels to be used as well. The
full external reference mode is entered when REFIN =
AGND. External voltages can be applied to REFP,
CML, and REFN. In this mode, the internal reference
shuts down, resulting in less overall power consumption.
Clock Input (CLK)
CLK is TTL/CMOS-compatible. Since the interstage
conversion of the device depends on the rising and
falling edges of the external clock, use a clock with low
jitter and fast rise and fall times (<2ns). Low clock jitter
improves SNR performance. The MAX1425 operates
with a 50% duty cycle. If the clock has a duty cycle
other than 50%, the clock must meet the specifications
for high and low periods as stated in the Electrical
Characteristics.
OUTPUT CODE
(TWO’S COMPLEMENT)
0111111111
+Full Scale 1LSB
0111111110
+Full Scale 2LSB
0111111101
+3/4 Full Scale
0110000000
+1/2 Full Scale
0100000000
+1/4 Full Scale
0010000000
+1 LSB
0000000001
Bipolar Zero
0000000000
-1 LSB
1111111111
-1/4 Full Scale
1110000000
-1/2 Full Scale
1100000000
-3/4 Full Scale
1010000000
-Full Scale + 1LSB
1000000001
-Full Scale
1000000000
Output Enable/Power-Down Function
(OE/PD) and Output Data
All data outputs, D0 through D9, are TTL/CMOS-logic
compatible. There is a 5.5 clock-cycle latency between
the start convert signal and the valid output data. The
output coding for the MAX1425 is in binary two’s complement format, which has the MSB inverted (Table 1).
The digital output goes into a high-impedance state
and the device into a low-power mode when OE/PD
goes high. For normal operation, drive OE low. The outputs are not designed to drive high capacitances or
______________________________________________________________________________________
11
MAX1425
10-Bit, 20Msps ADC
heavy loads, as they are specified to deliver only
200µA for TTL compatibility. If an application needs
output buffering, use 74LS74s or 74ALS541s as
required.
to remove some of the wideband noise associated with
high-speed op amps. In this application, the amplifier
outputs are directly coupled to the inputs. This configuration can also be modified for AC-coupled applications.
The MAX1425 includes a DC level-shifting circuit internal
to the part, allowing for AC-coupled applications. The
level-shifting circuit is shown in Figure 6.
The circuit in Figure 6 can accept a 1Vp-p maximum
input voltage. With a maximum clock frequency of
20MHz, use 50Ω termination to minimize reflections.
Buffer the digital outputs with a low-cost, high-speed,
Applications Information
Figure 5 depicts a typical application circuit containing
a single-ended to differential converter. The internal reference provides a +2.25V output for level shifting. The
input is buffered and then split to a voltage follower and
inverter. The op amps are followed by a lowpass filter
+5V
0.1μF
300Ω
BAS16
INP
MAX4108
50Ω
0.1μF
300Ω
22pF
0.1μF
0.1μF
-5V
MAX1425
600Ω
CML
+5V
2.5k
0.1μF
300Ω
600Ω
MAX473A
0.1μF
0.1μF
2.5k
+5V
50Ω
+5V
0.1μF
300Ω
600Ω
INPUT
0.1μF
0.1μF
MAX4108
300Ω
50Ω
-5V
0.1μF
50Ω
INN
MAX4108
BAS16
22pF
300Ω
-5V
0.1μF
25Ω
25Ω
600Ω
Figure 5. Typical Application Circuit Using the Internal Reference
12
______________________________________________________________________________________
10-Bit, 20Msps ADC
A small transformer (Figure 8) provides isolation and
AC-coupling to the ADC’s input. Connecting the transformer’s center tap to CML provides a +2.25VDC level
shift to the input. Transformer coupling reduces the
need for high-speed op amps, thereby reducing cost.
Although a 1:1 transformer is shown, a step-up transformer may be selected to reduce the drive requirements.
Typical Application Using an
External Reference
Figure 7 depicts an application circuit that shuts down
the internal reference, allowing an external reference to
be used for selecting a different common-mode voltage. This added flexibility also allows for ratiometric
conversions, as well as for calibration.
Single-Ended DC-Coupled Input Signal
Figure 9 shows an AC-coupled, single-ended application. The MAX4108 quad op amp provides high speed,
high bandwidth, low noise, and low distortion to maintain the integrity of the input signal.
CMLP
5.5k
5.5k
INP
TO T/H INPUT
INN
4.5k
4.5k
CMLN
Figure 6. Analog Input DC Bias Circuit
VDD
50Ω
(V2DD)
CML
R
0.1μF
VDD
2
50Ω
R
REFP
MAX4284
0.1μF
R
R
VDD
2
MAX1425
VDD
4
R
50Ω
R
( V2DD + 1V )
REFN
MAX4284
0.1μF
( V2DD - 1V )
R
VDD
4
REFIN
R
AGND
+1V
Figure 7. Using an External Reference for REFP, REFN, and CML (internal reference shut down)
______________________________________________________________________________________
13
MAX1425
Using Transformer Coupling
octal D-latched flip-flop (74ALS374), or use octal
buffers such as the 74ALS541.
MAX1425
10-Bit, 20Msps ADC
R4
25Ω
VIN
±V
C3
22pF
N.C. 2
R2
100Ω
R3
100Ω
3
T1
INP
50Ω MAX4108
MAX1425
1
IN1
±2V 0.1μF 50Ω
22pF
100Ω
6
MAX1425
5
4
MINICIRCUITS
KKB1
CML
0.1μF
R5
25Ω
100Ω
INN
0.1μF
INP
C9
22pF
Figure 9. Single-Ended AC-Coupled Input Signal
Figure 8. Using a Transformer for AC-Coupling
Bypassing and Board Layout
The MAX1425 requires high-speed board layout design
techniques. Locate all bypass capacitors as close to
the device as possible, using surface-mount devices
for minimum inductance. Bypass all analog voltages
(AV DD , REFIN, REFP, REFN, and CML) to AGND.
Bypass the digital supply (DVDD) to DGND. Multilayer
boards with separated ground and power planes produce the highest level of signal integrity. Route highspeed digital signal traces away from sensitive analog
traces. Matching impedance, especially for the input
clock generator, may reduce reflections, thus providing
less jitter in the system. For optimum results, use lowdistortion complementary components such as the
MAX4108.
14
______________________________________________________________________________________
10-Bit, 20Msps ADC
PACKAGE TYPE
PACKAGE CODE
OUTLINE NO.
LAND PATTERN NO.
28 SSOP
A28+1
21-0056
90-0095
______________________________________________________________________________________
15
MAX1425
________________________________________________________Package Information
For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
MAX1425
10-Bit, 20Msps ADC
Revision History
REVISION
NUMBER
REVISION
DATE
0
1/00
Initial release
1
7/11
Updated Ordering Information, Absolute Maximum Ratings, Electrical Characteristics
and Package Information
DESCRIPTION
PAGES
CHANGED
—
1, 2, 4, 15
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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