Rev.3.7_00 BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK S-8253A/B Series The S-8253A/B Series are protection ICs for 2-serial or 3-serial cell lithium-ion rechargeable batteries and include high-accuracy voltage detectors and delay circuits. These ICs are suitable for protecting lithium-ion battery packs from overcharge, overdischarge and overcurrent. Features (1) High-accuracy voltage detection for each cell • Overcharge detection voltage n (n = 1 to 3) 3.9 V to 4.4 V (50 mV steps) • Overcharge release voltage n (n = 1 to 3) 3.8 V to 4.4 V *1 • Overdischarge detection voltage n (n = 1 to 3) 2.0 V to 3.0 V (100 mV steps) *2 • Overdischarge release voltage n (n = 1 to 3) 2.0 V to 3.4 V (2) Three-level overcurrent detection (Including load short circuiting detection) • Overcurrent detection voltage 1 0.05 V to 0.30 V (50 mV steps) Accuracy ±25 mV • Overcurrent detection voltage 2 0.5 V (Fixed) • Overcurrent detection voltage 3 1.2 V (Fixed) (3) Delay times (Overcharge, Overdischarge, Overcurrent) are generated by an internal circuit. unnecessary). (4) Charge / discharge operation can be inhibited via the control pin. (5) 0 V battery charge function available / unavailable are selectable. (6) High-voltage withstand devices Absolute maximum rating 26 V (7) Wide operating voltage range 2 to 24 V (8) Wide operating temperature range −40 to +85 °C (9) Low current consumption • Operation mode 28 µA max. (+25 °C) • Power-down mode 0.1 µA max. (+25 °C) (10) Lead-free products Accuracy ±25 mV Accuracy ±50 mV Accuracy ±80 mV Accuracy ±100 mV (External capacitors are *1. Overcharge release voltage = Overcharge detection voltage − Overcharge hysteresis voltage (Overcharge hysteresis voltage n (n = 1 to 3) can be selected as 0 V or from a range of 0.1 to 0.4 V in 50 mV steps.) *2. Overdischarge release voltage = Overdischarge detection voltage + Overdischarge hysteresis voltage (Overdischarge hysteresis voltage n (n = 1 to 3) can be selected as 0 V or from a range of 0.2 to 0.7 V in 100 mV steps.) Applications • Lithium-ion rechargeable battery packs • Lithium polymer rechargeable battery packs Package Package Name 8-Pin TSSOP Package Drawing Code Tape Reel FT008-A FT008-E FT008-E Seiko Instruments Inc. 1 BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK S-8253A/B Series Rev.3.7_00 Block Diagrams 1. S-8253A Series VDD DOP Oscillator, counter, controller COP − + + − + − 95 kΩ VMP 900 kΩ VC1 − + + − + − + − VC2 CTLH 200 nA CTLM CTL + − VSS Remark All diodes shown in figure are parasitic diodes. Figure 1 2 − + Seiko Instruments Inc. Rev.3.7_00 BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK S-8253A/B Series 2. S-8253B Series VDD DOP Oscillator, counter, controller COP − + + − + − 95 kΩ VMP 900 kΩ VC1 − + + − + − + − VC2 CTLH 200 nA CTLM CTL − + + − VSS Remark All diodes shown in figure are parasitic diodes. Figure 2 Seiko Instruments Inc. 3 BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK S-8253A/B Series Rev.3.7_00 Product Name Structure 1. Product Name S-8253 x xx - T8T1 GZ Indicates package type and packing specification of IC *1 T8T1 : 8-Pin TSSOP, Tape Serial code *2 Sequentially set from AA to ZZ Product series name A : 2-cell B : 3-cell *1. Refer to the taping specifications at the end of this book. *2. Refer to the “2. Product Name List”. 2. Product Name List Table 1 S-8253A Series (For 2-Serial Cell) Overcharge detection voltage VCU Overcharge release voltage VCL Overdischarge detection voltage VDL Overdischarge release voltage VDU Overcurrent detection voltage VIOV1 0 V battery charge function S-8253AAA-T8T1GZ 4.350 ±0.025 V 4.050 ±0.050 V 2.40 ±0.080 V 2.70 ±0.100 V 0.300 ±0.025 V Available S-8253AAB-T8T1GZ 4.350 ±0.025 V 4.050 ±0.050 V 2.70 ±0.080 V 2.70 ±0.080 V 0.300 ±0.025 V Available S-8253AAC-T8T1GZ 4.350 ±0.025 V 4.050 ±0.050 V 2.40 ±0.080 V 2.70 ±0.100 V 0.080 ±0.025 V Available S-8253AAD-T8T1GZ 4.250 ±0.025 V 4.050 ±0.050 V 2.40 ±0.080 V 2.70 ±0.100 V 0.120 ±0.025 V Available S-8253AAE-T8T1GZ 4.350 ±0.025 V 4.050 ±0.050 V 2.80 ±0.080 V 3.00 ±0.100 V 0.300 ±0.025 V Available S-8253AAF-T8T1GZ 4.350 ±0.025 V 4.050 ±0.050 V 2.40 ±0.080 V 2.60 ±0.100 V 0.300 ±0.025 V Unavailable S-8253AAG-T8T1GZ 4.280 ±0.025 V 4.080 ±0.050 V 2.40 ±0.080 V 2.70 ±0.100 V 0.150 ±0.025 V Unavailable S-8253AAH-T8T1GZ 4.350 ±0.025 V 4.150 ±0.050 V 2.30 ±0.080 V 2.30 ±0.080 V 0.090 ±0.025 V Available Model No. Remark Please contact the SII marketing department for the products with the detection voltage value other than those specified above. Table 2 S-8253B Series (For 3-Serial Cell) Overcharge detection voltage VCU Overcharge release voltage VCL Overdischarge detection voltage VDL Overdischarge release voltage VDU Overcurrent detection voltage VIOV1 0 V battery charge function S-8253BAA-T8T1GZ 4.350 ±0.025 V 4.050 ±0.050 V 2.40 ±0.080 V 2.70 ±0.100 V 0.300 ±0.025 V Available S-8253BAB-T8T1GZ 4.325 ±0.025 V 4.075 ±0.050 V 2.20 ±0.080 V 2.90 ±0.100 V 0.200 ±0.025 V Unavailable S-8253BAC-T8T1GZ 4.350 ±0.025 V 4.050 ±0.050 V 2.40 ±0.080 V 2.70 ±0.100 V 0.080 ±0.025 V Available S-8253BAD-T8T1GZ 4.250 ±0.025 V 4.050 ±0.050 V 2.40 ±0.080 V 2.70 ±0.100 V 0.120 ±0.025 V Available S-8253BAE-T8T1GZ 4.350 ±0.025 V 4.150 ±0.050 V 2.20 ±0.080 V 2.40 ±0.100 V 0.100 ±0.025 V Available S-8253BAF-T8T1GZ 4.280 ±0.025 V 4.180 ±0.050 V 2.20 ±0.080 V 2.50 ±0.100 V 0.190 ±0.025 V Unavailable S-8253BAG-T8T1GZ 4.280 ±0.025 V 4.180 ±0.050 V 2.20 ±0.080 V 2.50 ±0.100 V 0.125 ±0.025 V Unavailable S-8253BAH-T8T1GZ 4.350 ±0.025 V 4.150 ±0.050 V 2.20 ±0.080 V 2.40 ±0.100 V 0.250 ±0.025 V Available S-8253BAI-T8T1GZ 4.350 ±0.025 V 4.150 ±0.050 V 2.20 ±0.080 V 2.40 ±0.100 V 0.160 ±0.025 V Available Model No. Remark Please contact the SII marketing department for the products with the detection voltage value other than those specified above. 4 Seiko Instruments Inc. Rev.3.7_00 BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK S-8253A/B Series Pin Configuration 8-Pin TSSOP Top view DOP COP VMP CTL 1 2 3 4 Table 3 S-8253A Series 8 7 6 5 Figure 3 VDD VC1 VC2 VSS Pin No. Symbol Description Connection pin for discharge control FET gate (CMOS output) Connection pin for charge control FET gate 2 COP (Nch open-drain output) Pin for voltage detection between VDD and VMP 3 VMP (Detection pin for overcurrent) Input pin for charge / discharge control signal, Pin for shortening test time ( L : Normal operation, 4 CTL H : inhibit charge / discharge M (VDD × 1 / 2) : shorten test time) Input pin for negative power supply, 5 VSS Connection pin for negative voltage of battery 2 6 VC2 No connection *1 Connection pin for negative voltage of battery 1, 7 VC1 for positive voltage of battery 2 Input pin for positive power supply, 8 VDD Connection pin for positive voltage of battery 1 *1. No connection is electrically open. This pin can be connected to VDD or VSS. Remark Refer to the package drawings for the external views. 1 DOP Table 4 S-8253B Series Pin No. Symbol Description Connection pin for discharge control FET gate (CMOS output) Connection pin for charge control FET gate 2 COP (Nch open-drain output) Pin for voltage detection between VDD and VMP 3 VMP (Detection pin for overcurrent) Input pin for charge / discharge control signal, pin for shortening test time ( L : Normal operation, 4 CTL H : inhibit charge / discharge, M (VDD × 1 / 2) : shorten test time) Input pin for negative power supply, 5 VSS Connection pin for negative voltage of battery 3 Connection pin for negative voltage of battery 2, 6 VC2 for positive voltage of battery 3 Connection pin for negative voltage of battery 1, 7 VC1 for positive voltage of battery 2 Input pin for positive power supply, 8 VDD Connection pin for positive voltage of battery 1 Remark Refer to the package drawings for the external views. 1 DOP Seiko Instruments Inc. 5 BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK S-8253A/B Series Rev.3.7_00 Absolute Maximum Ratings Table 5 (Ta = 25 °C unless otherwise specified) Applicable Pins Absolute Maximum Ratings Unit Input voltage between VDD and VSS Item VDS Symbol VSS − 0.3 to VSS + 26 V Input pin voltage VIN VC1, VC2 VSS − 0.3 to VDD + 0.3 V VMP pin input voltage VVMP VMP VSS − 0.3 to VSS + 26 V DOP pin output voltage VDOP DOP VSS − 0.3 to VDD + 0.3 V COP pin output voltage VCOP COP VSS − 0.3 to VVMP + 0.3 V CTL input pin voltage VIN_CTL CTL Power dissipation PD Operating ambient temperature Topr VSS − 0.3 to VDD + 0.3 300 (When not mounted on board) 700*1 − 40 to + 85 V mW mW °C Storage temperature Tstg − 40 to + 125 °C *1. When mounted on board [Mounted board] (1) Board size : 114.3 mm × 76.2 mm × t1.6 mm (2) Board name : JEDEC STANDARD51-7 Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical damage. These values must therefore not be exceeded under any conditions. Power Dissipation (PD) [mW] 800 700 600 500 400 300 200 100 0 0 50 100 150 Ambient Temperature (Ta) [°C] Figure 4 Power Dissipation of Package (When Mounted on Board) 6 Seiko Instruments Inc. BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK S-8253A/B Series Rev.3.7_00 Electrical Characteristics 1. Except Detection Delay Time Table 6 (1/2) (Ta = 25 °C unless otherwise specified) Item Symbol Conditions Min. Typ. Max. Unit Test condition Test circuit 1 1 1 1 1 1 1 1 1 1 1 1 2 1 2 1 2 1 DETECTION VOLTAGE Overcharge detection voltage n VCUn 3.90 to 4.40 V, Adjustable Overcharge release voltage n VCLn 3.80 to 4.40 V, Adjustable VCL ≠ VCU VCL = VCU Overdischarge detection voltage n VDLn 2.0 to 3.0 V, Adjustable Overdischarge release voltage n VDUn 2.0 to 3.40 V, Adjustable VDL ≠ VDU VDL = VDU Overcurrent detection voltage 1 VIOV1 0.05 to 0.30 V, Adjustable Overcurrent detection voltage 2 VIOV2 Overcurrent detection voltage 3 VIOV3 Temperature coefficient 1 *1 Temperature coefficient 2 *2 0 V BATTERY CHARGE FUNCTION 0 V battery charge starting charger voltage 0 V battery charge inhibition battery voltage INTERNAL RESISTANCE Resistance between VMP and VDD Resistance between VMP and VSS TCOE1 TCOE2 Ta = 0 to 50 °C Ta = 0 to 50 °C V0CHA V0INH 0 V battery charging available 0 V battery charging unavailable RVMD RVMS V1 = V2 = V3 = 3.5 V, VVMP = VSS *3 V1 = V2 = V3 = 1.8 V, VVMP = VDD *3 Seiko Instruments Inc. VCUn −0.025 VCLn −0.05 VCLn −0.025 VDLn −0.080 VDun −0.10 VDun −0.08 VDD −VIOV1 −0.025 VDD −0.60 VDD −1.5 −1.0 −0.5 VCUn VCLn VCLn VDLn VDun VDun VDD −VIOV1 VDD −0.50 VDD −1.2 0 0 VCUn V +0.025 VCLn V +0.05 VCLn V +0.025 VDLn V +0.080 VDun V +0.10 VDun V +0.08 VDD −VIOV1 V +0.025 VDD V −0.40 VDD V −0.9 1.0 mV / °C 0.5 mV / °C 0.4 0.8 0.7 1.5 1.1 V V 12 12 5 5 70 450 95 900 120 1800 kΩ kΩ 6 6 2 2 7 BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK S-8253A/B Series Rev.3.7_00 Table 6 (2/2) Item INPUT VOLTAGE Operating voltage between VDD and VSS Symbol VDSOP Conditions Output voltage of DOP and COP fixed Min. (Ta = 25 °C unless otherwise specified) Test Test Typ. Max. Unit condicircuit tion 2 24 V CTL input voltage “H” VCTLH VDD −0.5 V 7 1 CTL input voltage “L” VCTLL VSS +0.5 V 7 1 28 0.1 0.3 0.3 0.1 µA µA µA µA µA µA 5 5 9 9 8 8 2 2 3 3 3 3 0.1 µA µA µA µA 10 10 11 11 4 4 4 4 INPUT CURRENT *3 Current consumption on operation IOPE V1 = V2 = V3 = 3.5 V 14 *3 Current consumption at power down IPDN V1 = V2 = V3 = 1.5 V *3 VC1 pin current IVC1 V1 = V2 = V3 = 3.5 V −0.3 0 *3 VC2 pin current IVC2 V1 = V2 = V3 = 3.5 V −0.3 0 *3 CTL pin current “H” ICTLH V1 = V2 = V3 = 3.5 V, VCTL1 = VDD *3 CTL pin current “L” ICTLL V1 = V2 = V3 = 3.5 V, VCTL1 = VSS −0.4 –0.2 OUTPUT CURRENT COP pin leakage current ICOH VCOP = 24 V COP pin sink current ICOL VCOP = VSS + 0.5 V 10 DOP pin source current IDOH VDOP = VDD − 0.5 V 10 DOP pin sink current IDOL VDOP = VSS + 0.5 V 10 *1. Voltage temperature coefficient 1 : Overcharge detection voltage *2. Voltage temperature coefficient 2 : Overcurrent detection voltage 1 *3. Because S-8253A Series are the protection ICs for 2-serial cell, there is no V3 for them. 8 Seiko Instruments Inc. Rev.3.7_00 BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK S-8253A/B Series 2. Detection Delay Time （1） S-8253AAA, S-8253AAB, S-8253AAC, S-8253AAD, S-8253AAE, S-8253AAF, S-8253AAG, S-8253BAA, S-8253BAC,S-8253BAD, S-8253BAE, S-8253BAH Table 7 Item Symbol Condition Min. Typ. Max. Unit Test Condition Test Circuit DELAY TIME (Ta = 25 °C) Overcharge detection delay time tCU － 0.92 1.15 1.38 s 3 1 Overdischarge detection delay time Overcurrent detection delay time 1 Overcurrent detection delay time 2 Overcurrent detection delay time 3 tDL tIOV1 tIOV2 tIOV3 － － － － 115 7.2 3.6 220 144 9 4.5 300 173 10.8 5.4 380 ms ms ms µs 3 4 4 4 1 1 1 1 Condition Min. Typ. Max. Unit Test Condition Test Circuit tCU － 0.92 1.15 1.38 s 3 1 tDL tIOV1 tIOV2 tIOV3 － － － － 115 3.6 0.89 220 144 4.5 1.1 300 173 5.4 1.4 380 ms ms ms µs 3 4 4 4 1 1 1 1 Condition Min. Typ. Max. Unit Test Condition Test Circuit （2） S-8253BAB, S-8253BAF, S-8253BAG, S-8253BAI Table 8 Item Symbol DELAY TIME (Ta = 25 °C) Overcharge detection delay time Overdischarge detection delay time Overcurrent detection delay time 1 Overcurrent detection delay time 2 Overcurrent detection delay time 3 （3） S-8253AAH Table 9 Item Symbol DELAY TIME (Ta = 25 °C) Overcharge detection delay time tCU － 0.92 1.15 1.38 s 3 1 Overdischarge detection delay time Overcurrent detection delay time 1 Overcurrent detection delay time 2 Overcurrent detection delay time 3 tDL tIOV1 tIOV2 tIOV3 － － － － 115 14.5 3.6 220 144 18 4.5 300 173 22 5.4 380 ms ms ms µs 3 4 4 4 1 1 1 1 Seiko Instruments Inc. 9 BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK S-8253A/B Series Rev.3.7_00 Test Circuits 1. Overcharge Detection Voltage 1, Overcharge Release Voltage 1, Overdischarge Detection Voltage 1, Overdischarge Release Voltage 1 (Test Condition 1, Test Circuit 1) Confirm that V1 = V2 = 3.5 V (S-8253A Series), V1 = V2 = V3 = 3.5 V (S-8253B Series), V4 = 0 V, V5 = 0 V, and the COP and DOP pins are “L” (VDD × 0.1 V or lower) (this status is referred to as the initial status). 1. 1 Overcharge Detection Voltage 1 (VCU1), Overcharge Release Voltage 1 (VCL1) Overcharge detection voltage 1 (VCU1) is the voltage of V1 when the voltage of the COP pin is “H” (VDD × 0.9 V or more) after the V1 voltage has been gradually increased starting at the initial status. Overcharge release voltage 1 (VCL1) is the voltage of V1 when the voltage at the COP pin is low after the V1 voltage has been gradually decreased. 1. 2 Overdischarge Detection Voltage 1 (VDL1), Overdischarge Release Voltage 1 (VDU1) Overdischarge detection voltage 1 (VDL1) is the voltage of V1 when the voltage of the DOP pin is high after the V1 voltage has been gradually decreased starting at the initial status. Overdischarge release voltage 1 (VDU1) is the voltage of V1 when the voltage at the DOP pin is low after the V1 voltage has been gradually increased. By changing Vn (n = 2: S-8253A Series, n = 2, 3: S-8253B Series) the overcharge detection voltage (VCUn), overcharge release voltage (VCLn), overdischarge detection voltage (VDLn), and overdischarge release voltage (VDun) can be measured in the same way as when n = 1. 2. Overcurrent Detection Voltage 1, Overcurrent Detection Voltage 2, Overcurrent Detection Voltage 3 (Test Condition 2, Test Circuit 1) Confirm that V1 = V2 = 3.5 V (S-8253A Series), V1 = V2 = V3 = 3.5 V (S-8253B Series), V4 = 0 V, V5 = 0 V, and the COP pin and DOP pin are low (this status is referred to as the initial status). 2. 1 Overcurrent Detection Voltage 1 (VIOV1) Overcurrent detection voltage 1 (VIOV1) is the voltage of V5 when the voltages of the COP pin and DOP pin are high after the V5 voltage has been gradually increased starting at the initial status. 2. 2 Overcurrent Detection Voltage 2 (VIOV2) Overcurrent detection voltage 2 (VIOV2) is the voltage of V5 when the voltages of the COP pin and DOP pin are high within the minimum and maximum values of overcurrent detection time 2 (tIOV2) after the voltage of V5 was instantaneously increased (within 10 µs) starting at the initial status. 2. 3 Overcurrent Detection Voltage 3 (VIOV3) Overcurrent detection voltage 3 (VIOV3) is the voltage of V5 when the voltages of the COP pin and DOP pin are high within the minimum and maximum values of overcurrent detection time 3 (tIOV3) after the voltage of V5 was instantaneously increased (within 10 µs) starting at the initial status. 10 Seiko Instruments Inc. Rev.3.7_00 BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK S-8253A/B Series 3. Overcharge Detection Delay Time, Overdischarge Detection Delay Time (Test Condition 3, Test Circuit 1) Confirm that V1 = V2 = 3.5 V (S-8253A Series), V1 = V2 = V3 = 3.5 V (S-8253B Series), V4 = 0 V, V5 = 0 V, and the COP pin and DOP pin are low (this status is referred to as the initial status). 3. 1 Overcharge Detection Delay Time (tCU) The overcharge detection delay time (tCU) is the time it takes for the voltage of the COP pin to change from low to high after the voltage of V1 is instantaneously changed from overcharge detection voltage 1 (VCU1) − 0.2 V to overcharge detection voltage 1 (VCU1) + 0.2 V (within 10 µs) starting at the initial status. 3. 2 Overdischarge Detection Delay Time (tDL) The overdischarge detection delay time (tDL) is the time it takes for the voltage of the DOP pin to change from low to high after the voltage of V1 is instantaneously changed from overdischarge detection voltage 1 (VDL1) + 0.2 V to overdischarge detection voltage 1 (VDL1) − 0.2 V (within 10 µs) starting at the initial status. 4. Overcurrent Detection Delay Time 1, Detection Delay Time 2, Detection Delay Time 3 (Test Condition 4, Test Circuit 1) Confirm that V1 = V2 = 3.5 V (S-8253A Series), V1 = V2 = V3 = 3.5 V (S-8253B Series), V4 = 0 V, V5 = 0 V, and the COP pin and DOP pin are low (this status is referred to as the initial status). 4. 1 Overcurrent Detection Delay Time 1 (tIOV1) Overcurrent detection delay time 1 (tIOV1) is the time it takes for the voltage of the DOP pin to change from low to high after the voltage of V5 is instantaneously changed to 0.35 V (within 10 µs) starting at the initial status. 4. 2 Overcurrent Detection Delay Time 2 (tIOV2) Overcurrent detection delay time 2 (tIOV2) is the time it takes for the voltage of the DOP pin to change from low to high after the voltage of V5 is instantaneously changed to 0.7 V (within 10 µs) starting at the initial status. 4. 3 Overcurrent Detection Delay Time 3 (tIOV3) Overcurrent detection delay time 3 (tIOV3) is the time it takes for the voltage of the DOP pin to change from low to high after the voltage of V5 is instantaneously changed to 1.6 V (within 10 µs) starting at the initial status. 5. Consumption on Operation, Power Consumption at Power-down (Test Condition 5, Test Circuit 2) 5. 1 Power Consumption on Operation (IOPE) The power consumption during operation (IOPE) is the current of the VSS pin (ISS) when V1 = V2 = 3.5 V (S-8253A Series), V1 = V2 = V3 = 3.5 V (S-8253B Series), S1 = ON, and S2 = OFF. 5. 2 Power Consumption at Power-down (IPDN) The power consumption at power-down (IPDN) is the current of the VSS pin (ISS) when V1 = V2 = 1.5 V (S-8253A Series), V1 = V2 = V3 = 1.5 V (S-8253B Series), S1 = OFF, and S2 = ON. Seiko Instruments Inc. 11 BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK S-8253A/B Series Rev.3.7_00 6. Resistance between VMP and VDD, Resistance between VMP and VSS (Test Condition 6, Test Circuit 2) Confirm that V1 = V2 = 3.5 V (S-8253A Series), V1 = V2 = V3 = 3.5 V (S-8253B Series), S1 = ON, and S2 = OFF (this status is referred to as the initial status). 6. 1 Resistance between VMP and VDD (RVMD) The resistance between VMP and VDD (RVMD) is determined based on the current of the VMP pin (IVMD) after S1 and S2 are switched to OFF and ON, respectively, starting at the initial status. S-8253A Series : RVMD = (V1 + V2) / IVMD S-8253B Series : RVMD = (V1 + V2 + V3) / IVMD 6. 2 Resistance between VMP and VSS (RVMS) The resistance between VMP and VSS (RVMS) is determined based on the current of the VMP pin (IVMS) after V1 = V2 = 1.8 V (S-8253A Series) or V1 = V2 = V3 = 1.8 V (S-8253B Series) are set starting at the initial status. S-8253A Series : RVMS = (V1 + V2) / IVMS S-8253B Series : RVMS = (V1 + V2 + V3) / IVMS 7. CTL Pin Input Voltage “H” (Test Condition 7, Test Circuit 1) Confirm that V1 = V2 = 3.5 V (S-8253A Series), V1 = V2 = V3 = 3.5 V (S-8253B Series), V4 = 0 V, V5 = 0 V, and the COP pin and DOP pin are low (this status is referred to as the initial status). 7. 1 CTL Pin Input Voltage “H” (VCTLH) The CTL pin input voltage “H” (VCTLH) is the voltage of V4 when the voltages of the COP pin and DOP pin are high after the voltage of V4 has been gradually increased starting at the initial status. 8. CTL Pin Input Voltage “L” (Test condition 7, Test circuit 1) Confirm that V1 = V2 = 3.5 V (S-8253A Series), V1 = V2 = V3 = 3.5 V (S-8253B Series), V4 = 0 V, V5 = 0.35 V, and the COP pin and DOP pin are high (this status is referred to as the initial status). 8. 1 CTL Pin Input Voltage “L” (VCTLL) The CTL pin input voltage “L” (VCTLL) is the voltage of V4 when the voltages of the COP pin and DOP pin are low after the voltage of V4 has been gradually decreased starting at the initial status. 9. CTL Pin Current “H”, CTL Pin Current “L” (Test Condition 8, Test Circuit 3) 9. 1 CTL Pin Current “H” (ICTLH), CTL Pin Current “L” (ICTLL) The CTL pin current “H” (ICTLH) is the current that flows through the CTL pin when V1 = V2 = 3.5 V (S-8253A Series), V1 = V2 = V3 = 3.5 V (S-8253B Series), and S3 = ON, S4 = OFF. The CTL current “L” (ICTLL) is the current that flows through the CTL pin when S3 = OFF and S4 = ON after that. 12 Seiko Instruments Inc. Rev.3.7_00 BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK S-8253A/B Series 10. VC1 Pin Current, VC2 Pin Current (Test Condition 9, Test Circuit 3) 10. 1 VC1 Pin Current (IVC1), VC2 Pin Current (IVC2) The VC1 pin current (IVC1) is the current that flows through the VC1 pin when V1 = V2 = 3.5 V (S-8253A Series), V1 = V2 = V3 = 3.5 V (S-8253B Series), and S3 = OFF, S4 = ON. Similarly, the VC2 pin current (IVC2) is the current that flows through the VC2 pin under these conditions (S-8253B Series only). 11. COP Pin Leakage Current, COP Pin Sink Current (Test Condition 10, Test Circuit 4) 11. 1 COP Pin Leakage Current (ICOH) The COP pin leakage current (ICOH) is the current that flows through the COP pin when V1 = V2 = 12 V (S-8253A Series), V1 = V2 = V3 = 8 V (S-8253B Series), S6 = S7 = S8 = OFF, and S5 = ON. 11. 2 COP Pin Sink Current (ICOL) The COP pin sink current (ICOL) is the current that flows through the COP pin when V1 = V2 = 3.5 V (S-8253A Series), V1 = V2 = V3 = 3.5 V (S-8253B Series), V6 = 0.5 V, S5 = S7 = S8 = OFF, and S6 = ON. 12. DOP Pin Source Current, DOP Pin Sink Current (Test Condition 11, Test Circuit 4) 12. 1 DOP Pin Source Current (IDOH) The DOP pin source current (IDOH) is the current that flows through the DOP pin when V1 = V2 = 1.8 V (S-8253A Series), V1 = V2 = V3 = 1.8 V (S-8253B Series), V7 = 0.5 V, S5 = S6 = S8 = OFF, and S7 = ON. 12. 2 DOP Pin Sink Current (IDOL) The DOP pin sink current (IDOL) is the current that flows through the DOP pin when V1 = V2 = 3.5 V (S-8253A Series), V1 = V2 = V3 = 3.5 V (S-8253B Series), V8 = 0.5 V, S5 = S6 = S7 = OFF, and S8 = ON. 13. 0 V Battery Charge Starting Battery Charger Voltage (Product with 0 V Battery Charge Function), 0 V Battery Charge Inhibition Battery Voltage (Product with 0 V Battery Charge Inhibition Function) (Test Condition 12, Test Circuit 5) 13. 1 0 V Battery Charge Starting Battery Charger Voltage (V0CHA) (Product with 0 V Battery Charge Function) The COP pin voltage should be lower than V0CHA max. − 1 V when V1 = V2 = 0 V (S-8253A Series), V1 = V2 = V3 = 0 V (S-8253B Series), and V9 = VVMP = V0CHA max. 13. 2 0 V Battery Charge Inhibition Battery Voltage (V0INH) (Product with 0 V Battery Charge Inhibition Function) The COP pin voltage should be higher than VVMP − 1 V when V1 = V2 = V0INH min. (S-8253A Series), V1 = V2 = V3 = V0INH min. (S-8253B Series), and V9 = VVMP = 24 V. Seiko Instruments Inc. 13 BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK S-8253A/B Series S-8253A V S-8253B V V 1 DOP V VDD 8 1 DOP V1 1 MΩ 2 COP VDD 8 V1 1 MΩ VC1 7 2 COP V5 V2 3 VMP Rev.3.7_00 VC1 7 V5 V2 VC2 6 3 VMP VC2 6 4 CTL VSS 5 1 µF 4 CTL 1 µF VSS 5 V4 V3 V4 Figure 5 Test Circuit 1 S-8253B S-8253A 1 DOP 1 DOP VDD 8 V1 S1 2 COP VDD 8 V1 S1 2 COP VC1 7 VC1 7 V2 V2 A 3 VMP A VC2 6 3 VMP VC2 6 4 CTL VSS 5 1 µF 4 CTL S2 VSS 5 1 µF A S2 V3 A Figure 6 Test Circuit 2 S-8253B S-8253A 1 DOP 1 DOP VDD 8 V1 S3 2 COP VC1 7 VDD 8 V1 S3 2 COP A VC1 7 A V2 V2 3 VMP 3 VMP VC2 6 VC2 6 1 µF A S4 4 CTL A VSS 5 S4 Figure 7 Test Circuit 3 14 A 1 µF Seiko Instruments Inc. 4 CTL VSS 5 V3 BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK S-8253A/B Series Rev.3.7_00 S5 S7 S5 S-8253A S7 V7 A 1 DOP VDD 8 A V8 A S-8253B V7 V1 2 COP 1 DOP VDD 8 V8 VC1 7 A V1 2 COP VC1 7 V2 V2 V6 3 VMP V6 VC2 6 3 VMP VC2 6 4 CTL VSS 5 1 µF S8 S6 4 CTL 1 µF VSS 5 S8 S6 V3 Figure 8 Test Circuit 4 S-8253A 1 DOP S-8253B VDD 8 1 DOP VDD 8 2 COP VC1 7 V1 2 COP V 1 MΩ V2 3 VMP V 1 MΩ VC2 6 V9 V2 3 VMP 1 µF 4 CTL V1 VC1 7 VC2 6 1 µF V9 VSS 5 4 CTL V3 VSS 5 Figure 9 Test Circuit 5 Seiko Instruments Inc. 15 BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK S-8253A/B Series Rev.3.7_00 Operation Remark Refer to “ Battery Protection IC Connection Example”. 1. Normal Status When all of the battery voltages are in the range from VDLn to VCUn and the discharge current is lower than the specified value (the VMP pin voltage is higher than VDD − VIOV1), the charging and discharging FETs are turned on. Caution When the battery is connected for the first time, discharging may not be enabled. In this case, short the VMP pin and VDD pin or connect the charger to restore the normal status. 2. Overcharge Status When any one of the battery voltages becomes higher than VCUn and the state continues for tCU or longer, the COP pin becomes high impedance. Because the COP pin is pulled up to the EB+ pin voltage by an external resistor, the charging FET is turned off to stop charging. This is called the overcharge status. The overcharge status is released when one of the following two conditions holds. (1) All battery voltages become VCLn or lower. (2) All of the battery voltages are VCUn or lower, and the VMP pin voltage is VDD − VIOV1 or lower (since the discharge current flows through the body diode of the charging FET immediately after discharging is started when the charger is removed and a load is connected, the VMP pin voltage momentarily decreases by approximately 0.6 V from the VDD pin voltage. The IC detects this voltage and releases the overcharging status). 3. Overdischarge Status When any one of the battery voltages becomes lower than VDLn and the state continues for tDL or longer, the DOP pin voltage becomes VDD level, and the discharging FET is turned off to stop discharging. This is called the overdischarging status. After discharging is stopped due to the overdischarge status, the S-8253A/B Series enters the power-down status. 4. Power-down Status When discharging has stopped due to the overdischarge status, the VMP pin is pulled down to the VSS level by the RVMS resistor. When the VMP pin voltage is lower than Typ. 0.8 V, the S-8253A/B Series enters the power-down status. In the power-down status, almost all the circuits of the S-8253A/B Series stop and the current consumption is IPDN or lower. The conditions of each output pin are as follows. (1) COP pin : High-Z (2) DOP pin : VDD The power-down status is released when the following condition holds. (1) The VMP pin voltage is Typ. 0.8 V or higher. The overdischarging status is released when the following two conditions hold. (1) All battery voltage is released at VDUn or higher when the VMP pin voltage is Typ. 0.8 V or higher and the VMP pin voltage is lower than VDD. (2) All battery voltage is released at VDLn or higher when the VMP pin voltage is Typ. 0.8 V or higher and the VMP pin voltage is VDD or higher (when a charger is connected and VMP pin voltage is VDD or higher, overdischarge hysteresis is released and electric discharge control FET is turned on at VDLn). 16 Seiko Instruments Inc. Rev.3.7_00 BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK S-8253A/B Series 5. Overcurrent Status The S-8253A/B Series has three overcurrent detection levels (VIOV1, VIOV2, and VIOV3) and three overcurrent detection delay times (tIOV1, tIOV2, and tIOV3) corresponding to each overcurrent detection level. When the discharging current becomes higher than the specified value (the difference of the voltages of the VMP pin and VDD pin is greater than VIOV1) and the state continues for tIOV1 or longer, the S-8253A/B Series enters the overcurrent status, in which the DOP pin voltage becomes VDD level to turn off the discharging FET to stop discharging, the COP pin becomes high impedance and is pulled up to the EB+ pin voltage to turn off the charging FET to stop charging, and the VMP pin is pulled up to the VDD voltage by the internal resistor (RVMD). Operation of overcurrent detection levels 2, 3 (VIOV2, VIOV3) and overcurrent detection delay times 2, 3 (tIOV2, tIOV3) are the same as for VIOV1 and tIOV1. The overcurrent status is released when the following condition holds. (1) The VMP pin voltage is VDD − VIOV1 or higher because a charger is connected or the load is released. Caution The impedance that enables automatic restoration varies depending on the battery voltage and set value of overcurrent detection voltage 1. 6. 0 V Battery Charge Function Regarding the charging of a self-discharged battery (0 V battery), the S-8253A/B Series has two functions from which one should be selected. (1) 0 V battery charging is allowed (0 V battery charging is available.) When the charger voltage is higher than V0CHA, the 0 V battery can be charged. (2) 0 V battery charging is prohibited (0 V battery charging is unavailable.) When one of the battery voltages is lower than V0INH, the 0 V battery cannot be charged. Caution When the VDD pin voltage is lower than the minimum value of VDSOP, the operation of the S-8253A/B Series is not guaranteed. Seiko Instruments Inc. 17 BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK S-8253A/B Series Rev.3.7_00 7. Delay Circuit The following detection delay times are determined by dividing a clock of approximately 3.57 kHz by the counter. (Example) Oscillator clock cycle (TCLK) : Overcharge detection delay time (tCU) : Overdischarge detection delay time (tDL) : Overcurrent detection delay time 1 (tIOV1) : Overcurrent detection delay time 2 (tIOV2) : 280 µs 1.15 s 144 ms 9 ms 4.5 ms Remark The overcurrent detection delay time 2 (tIOV2) and overcurrent detection delay time 3 (tIOV3) start when the overcurrent detection voltage 1 (VIOV1) is detected. As soon as the overcurrent detection voltage 2 (VIOV2) or overcurrent detection voltage 3 (VIOV3) is detected over the detection delay time for overcurrent 2 (tIOV2) or overcurrent 3 (tIOV3) after the detection of overcurrent 1 (VIOV1), the S-8253A/B turns the discharging control FET off within tIOV2 or tIOV3 of each detection. VDD DOP pin voltage tD 0 ≤ tD ≤ tIOV2 VSS Overcurrent detection delay time 2 (tIOV2) Time VDD VMP pin voltage VIOV1 VIOV2 VIOV3 VSS Time Figure 10 8. CTL Pin The S-8253A/B Series has a control pin for charge / discharge control and shortening the test time. The levels, “L”, “H”, and “M”, of the voltage input to the CTL pin determine the status of the S-8253A/B Series: normal operation, charge / discharge inhibition, or test time shortening. The CTL pin takes precedence over the battery protection circuit. During normal use, short the CTL pin and VSS pin. Table 10 Conditions Set by CTL Pin CTL Pin Potential Status of IC Open Charge / discharge inhibited status High (VCTL ≥ VCTLH) Charge / discharge inhibited status Delay time-shortening status *1 Middle (VCTLL < VCTL < VCTLH) Low (VCTLL ≥ VCTL) Normal status *1. In this status, delay times are shortened in 1 / 60 to 1 / 30 scale. *2. The pin status is controlled by the voltage detection circuit. Caution 18 1. 2. 3. COP Pin DOP Pin High-Z High-Z (*2) (*2) VDD VDD (*2) (*2) If the potential of the CTL pin is middle, overcurrent detection voltage 1 (VIOV1) does not operate. If you use the middle potential of the CTL pin, contact SII marketing department. Please note unexpected behavior might occur when electrical potential difference between the CTL pin (“L” level) and VSS is generated through the external filter (RVSS and CVSS) as a result of input voltage fluctuations. Seiko Instruments Inc. BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK S-8253A/B Series Rev.3.7_00 Timing Chart 1. Overcharge Detection and Overdischarge Detection Battery voltage VHC VCUn VCLn VDUn VDLn VHD (n = 1 to 3) VDD DOP pin voltage VSS VEB+ COP pin voltage High-Z High-Z VSS VEB+ VDD VIOV1 VMP pin voltage 0.8 V VSS Charger connection Load connection Mode*1 Overcharge detection delay time ( tCU ) <1> <2> Overdischarge detection delay time ( tDL ) <1> <3> <1> *1. < 1 > : Normal mode < 2 > : Overcharge mode < 3 > : Overdischarge mode Remark The charger is assumed to charge with a constant current. VEB+ indicates the open voltage of the charger. Figure 11 Seiko Instruments Inc. 19 BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK S-8253A/B Series Rev.3.7_00 2. Overcurrent Detection VHC VCUn VCLn Battery voltage VDUn VDLn VHD (n = 1 to 3) VDD DOP pin voltage VSS VEB+ COP pin voltage High-Z High-Z High-Z VSS VDD VIOV1 VIOV2 VMP pin voltage VIOV3 VSS Load connection Mode*1 *1. Overcurrent detection delay time 2 ( tIOV2 ) Overcurrent detection delay time 1 ( tIOV1 ) <1> <2> <1> <2> Overcurrent detection delay time 3 ( tIOV3) <1> <2> <1> < 1 > : Normal mode < 2 > : Overcurrent mode Remark The charger is assumed to charge with a constant current. VEB+ indicates the open voltage of the charger. Figure 12 20 Seiko Instruments Inc. Rev.3.7_00 BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK S-8253A/B Series Battery Protection IC Connection Example 1. S-8253A Series Charging Discharging FET FET EB+ RCOP RDOP S-8253A RVMP CTL 1 DOP VDD 8 2 COP VC1 7 3 VMP VC2 6 4 CTL VSS 5 CVC1 RVC1 CVSS RVSS RCTL EB− Figure 13 2. S-8253B Series Charging Discharging FET FET EB+ RCOP RDOP S-8253B RVMP CTL 1 DOP VDD 8 2 COP VC1 7 3 VMP VC2 6 4 CTL VSS 5 CVC1 RVC1 CVC2 CVSS RVC2 RVSS RCTL EB− Figure 14 Seiko Instruments Inc. 21 BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK S-8253A/B Series Rev.3.7_00 Table 11 Constants for External Components No. 1 2 3 4 5 6 7 8 9 10 Symbol RVC1 RVC2 RDOP RCOP RVMP RCTL RVSS CVC1 CVC2 CVSS Typ. 1 1 5.1 1 5.1 1 51 0.1 0.1 2.2 Range 0.51 to 1*1 0.51 to 1*1 2 to 10 0.1 to 1 1 to 10 1 to 100 5.1 to 51*1 0.1 to 0.47*1 0.1 to 0.47*1 1 to 10*1 Unit kΩ kΩ kΩ MΩ kΩ kΩ Ω µF µF µF *1. Please set up a filter constant to be RVSS × CVSS ≥ 51 µF • Ω and to be RVC1 × CVC1 = RVC2 × CVC2 = RVSS × CVSS. Caution 1. The above constants may be changed without notice. 2. It has not been confirmed whether the operation is normal or not in circuits other than the above example of connection. In addition, the example of connection shown above and the constant do not guarantee proper operation. Perform through evaluation using the actual application to set the constant. 22 Seiko Instruments Inc. BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK S-8253A/B Series Rev.3.7_00 Precautions • In case of designing a circuit by using the CTL pin, as seen in Figure 15, note that discharging may stop during connecting a battery pack and the device. 【Cause】 This is because the overcurrent detection voltage 3 (VIOV3) is detected due to the rush current which flows into the device while a battery pack is in the delay time-shortening status. 【Mechanism】 As seen in Figure 15, before a battery pack is connected to the device, the battery pack may be in the charge / discharge inhibited status in which the CTL pin is internally pulled-up. From this status, if connecting the battery pack to the device, the CTL pin will be pulled-down in a time-constant C1 × (R1 + RPD) by a pull-down resistor in the device. If the CTL’s potential reaches VCTLL<VCTL<VCTLH, the battery pack goes in the delay time-shortening status so that it releases charging and discharging, hence it starts charging a parasitic capacitor in the device. In this case, if the rush current, which makes the S-8253A/B Series to detect the overcurrent detection voltage 3 (VIOV3), flows into the device, the overcurrent detection delay time 3 (tIOV3 = 300 µs typ.) will be shortened. So that the battery pack goes in the overcurrent status in several 10 µs. However, the battery pack goes in the normal status by connecting the device to the charger. Battery pack Device EB+ S-8253A/B VDD Rush current DOP Parasitic capacitor COP VMP 200 nA R1 CTL CTL Pull-down resistor RPD Discharging C1 EB− Figure 15 CTL CTL = H CTL = L CTLM DOP OFF ON OFF ON tIOV3 Mode VMP Rush current Connect battery pack to device Connect charger <3> <4> <2> <1> <1> : Normal mode <2> : Overcurrent mode <3> : Charge / discharge inhibit mode <4> : Delay time-shortening mode (enable to charge / discharge) Figure 16 Seiko Instruments Inc. 23 BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK S-8253A/B Series Rev.3.7_00 • The application conditions for the input voltage, output voltage, and load current should not exceed the package power dissipation. • Batteries can be connected in any order, however, there may be cases when discharging cannot be performed when a battery is connected. In this case, short the VMP pin and VDD pin or connect the battery charger to return to the normal mode. • Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic protection circuit. • SII claims no responsibility for any disputes arising out of or in connection with any infringement by products including this IC of patents owned by a third party. 24 Seiko Instruments Inc. BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK S-8253A/B Series Rev.3.7_00 Characteristics (Typical Data) 1. Current Consumption 40 35 30 25 20 15 10 5 0 (S-8253AAA) IOPE [µA] IOPE [µA] 1. 1 IOPE vs. VDD 0 5 10 15 VDD [V] 20 40 35 30 25 20 15 10 5 0 (S-8253BAA) 0 5 10 15 VDD [V] 20 (S-8253AAA) 40 35 30 25 20 15 10 5 0 −40 −25 IOPE [µA] IOPE [µA] 1. 2 IOPE vs. Ta 0 25 Ta [°C] 50 75 85 (S-8253BAA) 40 35 30 25 20 15 10 5 0 −40 −25 0 25 Ta [°C] 50 75 85 0.10 0.09 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0 (S-8253AAA) 0.10 0.09 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0 IPDN [µA] IPDN [µA] 1. 3 IPDN vs. VDD 0 5 10 15 VDD [V] 20 (S-8253BAA) 0 5 10 15 VDD [V] 20 0.10 0.09 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0 −40 −25 (S-8253AAA) IPDN [µA] IPDN [µA] 1. 4 IPDN vs. Ta 0 25 Ta [°C] 50 75 85 0.10 0.09 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0 −40 −25 Seiko Instruments Inc. (S-8253BAA) 0 25 Ta [°C] 50 75 85 25 BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK S-8253A/B Series Rev.3.7_00 2. Overcharge Detection / Release Voltage, Overdischarge Detection / Release Voltage, Overcurrent Detection Voltage, and Delay Times (S-8253AAA, S-8253BAA) 2. 2 VCL vs. Ta 4.375 4.370 4.365 4.360 4.355 4.350 4.345 4.340 4.335 4.330 4.325 −40 −25 0 25 Ta [°C] 50 7585 2.80 2.78 2.76 2.74 2.72 2.70 2.68 2.66 2.64 2.62 2.60 −40 −25 0 25 Ta [°C] 50 2.48 2.46 2.44 2.42 2.40 2.38 2.36 2.34 2.32 −40 −25 75 85 2. 5 tCU vs. Ta 1220 155 tDL [ms] 173 165 1120 75 85 0 25 Ta [°C] 50 75 85 0 25 Ta [°C] 50 75 85 135 125 920 −40 −25 0 25 Ta [°C] 50 115 −40 −25 75 85 2. 7 VIOV1 vs. VDD 2. 8 VIOV1 vs. Ta VIOV1 [V] VIOV1 [V] 50 145 1020 26 25 Ta [°C] 2. 6 tDL vs. Ta 1380 1320 0.325 0.320 0.315 0.310 0.305 0.300 0.295 0.290 0.285 0.280 0.275 0 2. 4 VDL vs. Ta VDL [µA] VDU [µA] 2. 3 VDU vs. Ta tCU [ms] 4.10 4.09 4.08 4.07 4.06 4.05 4.04 4.03 4.02 4.01 4.00 −40 −25 VCL [µA] VCU [µA] 2. 1 VCU vs. Ta 7 8 9 10 11 VDD [V] 12 13 0.325 0.320 0.315 0.310 0.305 0.300 0.295 0.290 0.285 0.280 0.275 −40 −25 Seiko Instruments Inc. 0 25 Ta [°C] 50 75 85 BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK S-8253A/B Series Rev.3.7_00 0.60 0.58 0.56 0.54 0.52 0.50 0.48 0.46 0.44 0.42 0.40 2. 10 VIOV2 vs. Ta VIOV2 [V] VIOV2 [V] 2. 9 VIOV2 vs. VDD 7 8 9 10 11 VDD [V] 12 13 1.5 1.5 1.4 1.4 1.3 1.3 1.2 1.1 7 8 9 10 11 VDD [V] 12 tIOV1 [ms] tIOV1 [ms] 7 8 9 10 11 VDD [V] 12 13 1.1 7 0 25 Ta [°C] 50 75 85 10.8 10.4 10.0 9.6 9.2 8.8 8.4 8.0 7.6 7.2 −40 −25 0 25 Ta [°C] 50 75 85 0 25 Ta [°C] 50 75 85 2. 16 tIOV2 vs. Ta tIOV2 [ms] tIOV2 [ms] 75 85 2. 14 tIOV1 vs. Ta 2. 15 tIOV2 vs. VDD 5.4 5.2 5.0 4.8 4.6 4.4 4.2 4.0 3.8 3.6 50 1.2 0.9 −40 −25 13 2. 13 tIOV1 vs. VDD 10.8 10.4 10.0 9.6 9.2 8.8 8.4 8.0 7.6 7.2 25 Ta [°C] 1.0 1.0 0.9 0 2. 12 VIOV3 vs. Ta VIOV3 [V] VIOV3 [V] 2. 11 VIOV3 vs. VDD 0.60 0.58 0.56 0.54 0.52 0.50 0.48 0.46 0.44 0.42 0.40 −40 −25 8 9 10 11 VDD [V] 12 13 Seiko Instruments Inc. 5.4 5.2 5.0 4.8 4.6 4.4 4.2 4.0 3.8 3.6 −40 −25 27 BATTERY PROTECTION IC FOR 2-SERIAL OR 3-SERIAL-CELL PACK S-8253A/B Series 0.38 0.36 0.34 0.32 0.30 0.28 0.26 0.24 0.22 2. 18 tIOV3 vs. Ta tIOV3 [ms] tIOV3 [ms] 2. 17 tIOV3 vs. VDD 7 Rev.3.7_00 8 9 10 11 VDD [V] 12 13 0.38 0.36 0.34 0.32 0.30 0.28 0.26 0.24 0.22 −40 −25 0 25 Ta [°C] 50 75 85 3. COP / DOP Pin (S-8253AAA, S-8253BAA) 3. 1 ICOH vs. VCOP 3. 2 ICOL vs. VCOP 0.10 ICOL [mA] ICOH [µA] 0.08 0.06 0.04 0.02 0 0 4 8 12 16 VCOP [V] 20 24 3. 3 IDOH vs. VDOP IDOL [mA] IDOH [mA] −0.5 −1.0 −1.5 −2.0 28 0 0 3. VCOP [V] 7.0 10.5 7.0 10.5 3. 4 IDOL vs. VDOP 0 −2.5 14 12 10 8 6 4 2 0 1.8 VDOP [V] 3.6 5.4 Seiko Instruments Inc. 14 12 10 8 6 4 2 0 0 3.5 VDOP [V] +0.3 3.00 -0.2 8 5 1 4 0.17±0.05 0.2±0.1 0.65 No. FT008-A-P-SD-1.1 TITLE TSSOP8-E-PKG Dimensions FT008-A-P-SD-1.1 No. SCALE UNIT mm Seiko Instruments Inc. 4.0±0.1 2.0±0.05 ø1.55±0.05 0.3±0.05 +0.1 8.0±0.1 ø1.55 -0.05 (4.4) +0.4 6.6 -0.2 1 8 4 5 Feed direction No. FT008-E-C-SD-1.0 TITLE TSSOP8-E-Carrier Tape FT008-E-C-SD-1.0 No. SCALE UNIT mm Seiko Instruments Inc. 13.4±1.0 17.5±1.0 Enlarged drawing in the central part ø21±0.8 2±0.5 ø13±0.5 No. FT008-E-R-SD-1.0 TSSOP8-E-Reel TITLE No. FT008-E-R-SD-1.0 SCALE QTY. UNIT mm Seiko Instruments Inc. 3,000 • • • • • • The information described herein is subject to change without notice. Seiko Instruments Inc. is not responsible for any problems caused by circuits or diagrams described herein whose related industrial properties, patents, or other rights belong to third parties. The application circuit examples explain typical applications of the products, and do not guarantee the success of any specific mass-production design. When the products described herein are regulated products subject to the Wassenaar Arrangement or other agreements, they may not be exported without authorization from the appropriate governmental authority. Use of the information described herein for other purposes and/or reproduction or copying without the express permission of Seiko Instruments Inc. is strictly prohibited. The products described herein cannot be used as part of any device or equipment affecting the human body, such as exercise equipment, medical equipment, security systems, gas equipment, or any apparatus installed in airplanes and other vehicles, without prior written permission of Seiko Instruments Inc. Although Seiko Instruments Inc. exerts the greatest possible effort to ensure high quality and reliability, the failure or malfunction of semiconductor products may occur. The user of these products should therefore give thorough consideration to safety design, including redundancy, fire-prevention measures, and malfunction prevention, to prevent any accidents, fires, or community damage that may ensue.