Rev.3.2_10
BATTERY PROTECTION IC
FOR 3-SERIAL-CELL PACK
S-8233A Series
The S-8233A Series is a series of lithium-ion rechargeable battery
protection ICs incorporating high-accuracy voltage detection circuits and
delay circuits. It is suitable for a 3-serial-cell lithium-ion battery pack.
Features
(1)
Internal high-accuracy voltage detection circuit
Over charge detection voltage
4.10 ± 0.05 V to 4.35 ± 0.05 V
50 mV- step
Over charge release voltage
3.85 ± 0.10 V to 4.35 ± 0.10 V
50 mV- step
(The over charge release voltage can be selected within the range where a difference from over
charge detection voltage is 0 V to 0.3 V)
Over discharge detection voltage
2.00 ± 0.08 V to 2.70± 0.08 V
100 mV- step
Over discharge release voltage
2.00 ± 0.10 V to 3.70± 0.10 V
100 mV - step
(The over discharge release voltage can be selected within the range where a difference from over
discharge detection voltage is 0 V to 1.0 V)
Over current detection voltage 1
0.15 ±0.015 V to 0.5 ±0.05 V
50 mV-step
(2)
(3)
(4)
(5)
(6)
(7)
(8)
High input-voltage device (absolute maximum rating: 26 V)
Wide operating voltage range:
2 V to 24 V
The delay time for every detection can be set via an external capacitor.
Three over current detection levels (protection for short-circuiting)
Internal charge/discharge prohibition circuit via the control terminal
The function for charging batteries from 0 V is available.
Low current consumption
Operation
50 µA max. (+25 °C)
Power-down
0.1 µA max. (+25 °C)
Applications
Lithium-ion rechargeable battery packs
Packages
Package Name
14-Pin SOP
16-Pin TSSOP
Package
FE014-A
FT016-A
Drawing Code
Tape
FE014-A
FT016-A
Seiko Instruments Inc.
Reel
FE014-A
FT016-A
1
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
S-8233A Series
Rev.3.2_10
Block Diagram
VCC
Reference
voltage 1
Over current
2,3 delay
circuit
Over current
detection
circuit
VMP
Over current1,
delay circuit
COVT
Over discharge
delay circuit
CDT
Over charge
delay circuit
CCT
+
−
CD1
+
−
VC1
Battery 1
Over charge
Battery 1
Over discharge
Battery 1
Over charge
Control
+
−
CD2
Logic
Battery 2
Over charge
+
−
Battery 2
Over discharge
Reference
voltage 2
VC2
DOP
Battery 2
Over charge
+
−
CD3
Battery 3
Over charge
COP
+
−
Battery 3
Over discharge
Reference
voltage 3
VSS
Battery 3
Over charge
Floating
detection circuit
CTL
Figure 1
Remark
2
The delay time for over current detection 2 and 3 is fixed by an internal IC circuit. The delay time
cannot be changed via an external capacitor.
Seiko Instruments Inc.
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
S-8233A Series
Rev.3.2_10
Product Name Structure
1. Product name
x
S−8233A
xx
− TB
IC direction in tape specifications*1
Package name (abbreviation)
FE: 14-Pin SOP
FT: 16-Pin TSSOP
Serial code
Assigned from A to Z in alphabetical order
*1. Refer to the taping specifications.
Seiko Instruments Inc.
3
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
S-8233A Series
Rev.3.2_10
2. Product name list
・14-Pin SOP
Table 1
Product name /
Parameter
S-8233ACFE-TB
Overcharge
Overcharge
detection voltage release voltage
VCU
VCD
4.25±0.05 V
4.05±0.10 V
4.10
*1
Overdischarge
detection voltage
VDD
2.00±0.08 V
Overdischarge
release voltage
VDU
2.30±0.10 V
2.00±0.08 V
2.30±0.10 V
Overcurrent
0 V battery
detection voltage1
charge function
VIOV1
0.20±0.02 V
－
－
0.20±0.02 V
S-8233ADFE-TB
4.10±0.05 V
S-8233AEFE-TB
4.25±0.05 V
4.10±0.10 V
2.30±0.08 V
2.70±0.10 V
0.15±0.015 V
－
S-8233AFFE-TB
4.35±0.05 V
4.05±0.10 V
2.40±0.08 V
2.70±0.10 V
0.50±0.05 V
Available
S-8233AGFE-TB
4.25±0.05 V
4.05±0.10 V
2.40±0.08 V
2.70±0.10 V
0.40±.0.04 V
S-8233AIFE-TB
4.25±0.05 V
4.10±0.10 V
2.30±0.08 V
3.00±0.10 V
0.15±0.015 V
Available
－
S-8233AJFE-TB
4.35±0.05 V
4.05±0.10 V
2.40±0.08 V
2.70±0.10 V
0.30±0.03 V
－
S-8233AKFE-TB
4.35±0.05 V
4.05±0.10 V
2.40±0.08 V
2.70±0.10 V
0.15±0.015 V
－
S-8233ALFE-TB
4.35±0.05 V
4.05±0.10 V
2.40±0.08 V
2.70±0.10 V
0.40±0.04 V
Available
S-8233AMFE-TB
4.35±0.05 V
4.05±0.10 V
2.40±0.08 V
2.70±0.10 V
0.30±0.03 V
Available
S-8233ANFE-TB
4.35±0.05 V
4.05±0.10 V
2.40±0.08 V
2.40±0.10 V
0.15±0.015 V
Available
S-8233AOFE-TB
4.35±0.05 V
4.05±0.10 V
2.40±0.08 V
2.70±0.10 V
0.15±0.015 V
Available
S-8233APFE-TB
4.25±0.05 V
4.05±0.10 V
2.70±0.08 V
3.00±0.10 V
0.30±0.03 V
Available
2.70±0.08 V
3.00±0.10 V
0.30±0.03 V
Available
*1
S-8233AQFE-TB
4.25±0.05 V
4.25
*1. Without over charge detection hysteresis.
Remark Please contact the SII marketing department for the products with the detection voltage value other
than those specified above.
・16-Pin TSSOP
Table 2
Product name /
Parameter
S-8233ACFT-TB
Overcharge
Overcharge
detection voltage release voltage
VCu
VCD
4.25±0.05 V
4.05±0.10 V
4.10
*1
Overdischarge
detection voltage
VDD
2.00±0.08 V
Overdischarge
release voltage
VDU
2.30±0.10 V
2.00±0.08 V
2.30±0.10 V
Overcurrent
0 V battery
detection voltage1
charge function
VIOV1
0.20±0.02 V
－
－
0.20±0.02 V
S-8233ADFT-TB
4.10±0.05 V
S-8233AEFT-TB
4.25±0.05 V
4.10±0.10 V
2.30±0.08 V
2.70±0.10 V
0.15±0.015 V
－
S-8233AFFT-TB
4.35±0.05 V
4.05±0.10 V
2.40±0.08 V
2.70±0.10 V
0.50±0.05 V
Available
S-8233AGFT-TB
4.25±0.05 V
4.05±0.10 V
2.40±0.08 V
2.70±0.10 V
0.40±.0.04 V
S-8233AIFT-TB
4.25±0.05 V
4.10±0.10 V
2.30±0.08 V
3.00±0.10 V
0.15±0.015 V
Available
－
S-8233AJFT-TB
4.35±0.05 V
4.05±0.10 V
2.40±0.08 V
2.70±0.10 V
0.30±0.03 V
－
S-8233AKFT-TB
4.35±0.05 V
4.05±0.10 V
2.40±0.08 V
2.70±0.10 V
0.15±0.015 V
－
S-8233ALFT-TB
4.35±0.05 V
4.05±0.10 V
2.40±0.08 V
2.70±0.10 V
0.40±0.04 V
Available
S-8233AMFT-TB
4.35±0.05 V
4.05±0.10 V
2.40±0.08 V
2.70±0.10 V
0.30±0.03 V
Available
S-8233ANFT-TB
4.35±0.05 V
4.05±0.10 V
2.40±0.08 V
2.40±0.10 V
0.15±0.015 V
Available
S-8233AOFT-TB
4.35±0.05 V
4.05±0.10 V
2.40±0.08 V
2.70±0.10 V
0.15±0.015 V
Available
S-8233APFT-TB
4.25±0.05 V
4.05±0.10 V
2.70±0.08 V
3.00±0.10 V
0.30±0.03 V
Available
S-8233ARFT-TB
4.35±0.05 V
4.05±0.10 V
*1. Without over charge detection hysteresis.
2.00±0.08 V
2.70±0.10 V
0.30±0.03 V
Available
Remark Please contact the SII marketing department for the products with the detection voltage value other
than those specified above.
4
Seiko Instruments Inc.
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
S-8233A Series
Rev.3.2_10
Pin Assignment
14-Pin SOP
Top view
DOP
1
14
VCC
COP
2
13
CD1
VMP
3
12
VC1
COVT
4
11
CD2
CDT
5
10
VC2
CCT
6
9
CD3
VSS
7
8
CTL
Figure 2
16-Pin TSSOP
Top view
DOP
NC
COP
VMP
COVT
CDT
CCT
VSS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Figure 3
VCC
NC
CD1
VC1
CD2
VC2
CD3
CTL
Table 3
Pin No. Symbol
Pin description
1
DOP Connects FET gate for discharge control (CMOS output)
2
COP Connects FET gate for charge control (Nch open-drain output)
3
VMP Detects voltage between VCC to VMP(Over current detection pin)
4
COVT Connects capacitor for over current detection1delay circuit
5
CDT Connects capacitor for over discharge detection delay circuit
6
CCT Connects capacitor for over charge detection delay circuit
7
VSS Negative power input, and connects negative voltage for battery 3
8
CTL Charge/discharge control signal input
9
CD3 Battery 3 conditioning signal output
10
VC2 Connects battery 2 negative voltage and battery 3 positive voltage
11
CD2 Battery 2 conditioning signal output
12
VC1 Connects battery 1 negative voltage and battery 2 positive voltage
13
CD1 Battery 1 conditioning signal output
14
VCC Positive power input and connects battery 1 positive voltage
Table 4
Pin No. Symbol
Pin description
1
DOP Connects FET gate for discharge control (CMOS output)
*1
2
NC
No connection
3
COP Connects FET gate for charge control (Nch open-drain output)
4
VMP Detects voltage between VCC to VMP(Over current detection pin)
5
COVT Connects capacitor for over current detection1 delay circuit
6
CDT Connects capacitor for over discharge detection delay circuit
7
CCT Connects capacitor for over charge detection delay circuit
8
VSS Negative power input, and connects negative voltage for battery 3
9
CTL Charge/discharge control signal input
10
CD3 Battery 3 conditioning signal output
11
VC2 Connects battery 2 negative voltage and battery 3 positive voltage
12
CD2 Battery 2 conditioning signal output
13
VC1 Connects battery 1 negative voltage and battery 2 positive voltage
CD1
14
Battery 1 conditioning signal output
*1
15
NC
No connection
16
VCC Positive power input and connects battery 1 positive voltage
*1. The NC pin is electrically open. The NC pin can be connected to
VCC or VSS.
Seiko Instruments Inc.
5
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
S-8233A Series
Rev.3.2_10
Absolute Maximum Ratings
Table 5
Symbol
Applicable Pins
(Ta = 25 °C unless otherwise specified)
Absolute Maximum Ratings Unit
VDS
－
VSS−0.3 ~ VSS+26
V
VIN
VC1, VC2, CTL, CCT, CDT, COVT
VSS−0.3 ~ VCC+0.3
V
VMP Input terminal voltage
VVMP
VMP
VSS−0.3 ~ VSS+26
V
CD1 output terminal voltage
VCD1
CD1
VC1−0.3 ~ VCC+0.3
V
CD2 output terminal voltage
VCD2
CD2
VC2−0.3 ~ VCC+0.3
V
CD3 output terminal voltage
VCD3
CD3
VSS−0.3 ~ VCC+0.3
V
DOP output terminal voltage
VDOP
DOP
VSS−0.3 ~ VCC+0.3
V
COP output terminal voltage
Power dissipation
VCOP
COP
VSS−0.3 ~ VSS+26
V
PD
－
14-Pin SOP
400
mW
－
16-Pin TSSOP
300
mW
Parameter
Input voltage between VCC
and VSS
Input pin voltage
Operating temperature range
Topr
－
−20 ~ +70
°C
Tstg
−40 ~ +125
°C
－
Storage temperature range
Caution The absolute maximum ratings are rated values exceeding which the product could suffer
physical damage. These values must therefore not be exceeded under any conditions.
6
Seiko Instruments Inc.
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
S-8233A Series
Rev.3.2_10
Electrical Characteristics
Table 6 (1 / 2)
Item
(Ta = 25 °C unless otherwise specified)
Measure- Measurement
ment
Min. Typ. Max. Unit
condition circuit
Symbol
Condition
Over charge detection voltage1
VCU1
4.10 to 4.35 Adjustment
VCU1−0.05
VCU1 VCU1+0.05
V
1
1
Over charge release voltage1
VCD1
3.85 to 4.35 Adjustment
VCD1−0.10
VCD1 VCD1+0.10
V
1
1
Over discharge detection voltage1
VDD1
2.00 to 2.70 Adjustment
VDD1−0.08
VDD1 VDD1+0.08
V
1
1
Over discharge release voltage1
VDU1
2.00 to 3.70 Adjustment
VDU1−0.10
VDU1 VDU1+0.10
V
1
1
Over charge detection voltage 2
VCU2
4.10 to 4.35 Adjustment
VCU2−0.05
VCU2 VCU2+0.05
V
2
1
Over charge release voltage 2
VCD2
3.85 to 4.35 Adjustment
VCD2−0.10
VCD2 VCD2+0.10
V
2
1
Over discharge detection voltage 2
VDD2
2.00 to 2.70 Adjustment
VDD2−0.08
VDD2 VDD2+0.08
V
2
1
Over discharge release voltage 2
VDU2
2.00 to 3.70 Adjustment
VDU2−0.10
VDU2 VDU2+0.10
V
2
1
Over charge detection voltage3
VCU3
4.10 to 4.35 Adjustment
VCU3−0.05
VCU3 VCU3+0.05
V
3
1
Over charge release voltage3
VCD3
3.85 to 4.35 Adjustment
VCD3−0.10
VCD3 VCD3+0.10
V
3
1
Over discharge detection voltage3
VDD3
2.00 to 2.70 Adjustment
VDD3−0.08
VDD3 VDD3+0.08
V
3
1
Over discharge release voltage3
VDU3
2.00 to 3.70 Adjustment
VDU3−0.10
VDU3 VDU3+0.10
V
3
1
Over current detection voltage1
VIOV1
0.15 to 0.50V Adjustment
VIOV1 x 0.9 VIOV1 VIOV1 x 1.1
V
4
2
Over current detection voltage 2
VIOV2
VCC Reference
0.54
0.6
0.66
V
4
2
Over current detection voltage3
VIOV3
VSS Reference
1.0
2.0
3.0
V
4
2
Voltage temperature factor 1
TCOE1
Ta=-20 to 70°C
−1.0
0
1.0
mV/°C
TCOE2
Ta=-20 to 70°C
−0.5
0
0.5
mV/°C
−
−
−
−
Over charge detection delay time1
tCU1
CCCT=0.47 µF
0.5
1.0
1.5
s
9
6
Over charge detection delay time 2
tCU2
CCCT=0.47 µF
0.5
1.0
1.5
s
10
6
Over charge detection delay time3
tCU3
CCCT=0.47 µF
0.5
1.0
1.5
s
11
6
Over discharge detection delay time1
tDD1
CCDT=0.1 µF
20
40
60
ms
9
6
Over discharge detection delay time 2
tDD2
CCDT=0.1 µF
20
40
60
ms
10
6
Over discharge detection delay time3
tDD3
CCDT=0.1 µF
20
40
60
ms
11
6
Over current detection delay time1
tIOV1
CCOVT=0.1 µF
10
20
30
ms
12
7
Over current detection delay time 2
tIOV2
−
2
4
8
ms
12
7
Over current detection delay time3
tIOV3
FET gate capacitor =2000 pF
100
300
550
µs
12
7
VDSOP
−
2.0
−
24
V
−
−
IOPE
V1=V2=V3=3.5 V
−
20
50
µA
5
3
Current consumption for cell 2
ICELL2
V1=V2=V3=3.5 V
−300
0
300
nA
5
3
Current consumption for cell 3
ICELL3
V1=V2=V3=3.5 V
−300
0
300
nA
5
3
Current consumption at power down
IPDN
V1=V2=V3=1.5 V
−
−
0.1
µA
5
3
Detection voltage
Voltage temperature factor 2
*1
*2
*3
Delay time
Operating voltage
Operating voltage between VCC and
*4
VSS
Current consumption
Current consumption (during normal
operation)
Internal resistance
Resistance between
RVCM
VCC and VMP
Resistance between
V1=V2=V3=3.5 V
V1=V2=V3=3.5 V
RVSM
VSS and VMP
V1=V2=V3=1.5 V
V1=V2=V3=1.5 V
*5
*5
0.40
0.90
1.40
MΩ
6
3
0.20
0.50
0.80
MΩ
6
3
0.40
0.90
1.40
MΩ
6
3
0.20
0.50
0.80
MΩ
6
3
VCCx0.8
−
−
−
V
VCCx0.2
V
−
−
−
−
Input voltage
CTL"H" Input voltage
VCTL(H)
CTL"L" Input voltage
VCTL(L)
−
−
Seiko Instruments Inc.
−
7
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
S-8233A Series
Rev.3.2_10
Table 6 (2 / 2)
Item
Symbol
Condition
Min.
(Ta = 25 °C unless otherwise specified)
Measure- Measurement
ment
Typ.
Max.
Unit
condition
circuit
Output voltage
DOP"H" voltage
VDO(H)
IOUT=10 µA
VCC-0.5
DOP"L" voltage
VDO(L)
IOUT=10 µA
COP"L" voltage
VCO(L)
IOUT=10 µA
ICOL
V1=V2=V3=4.5 V
−
−
−
CD1"H" voltage
VCD1(H)
IOUT=0.1 µA
VCC -0.5
CD1"L" voltage
VCD1(L)
IOUT=10 µA
−
CD 2"H" voltage
VCD2(H)
IOUT=0.1 µA
VCC -0.5
CD 2"L" voltage
VCD2(L)
IOUT=10 µA
−
CD3"H" voltage
VCD3(H)
IOUT=0.1 µA
VCC -0.5
CD3"L" voltage
VCD3(L)
IOUT=10 µA
−
−
−
−
−
−
−
−
−
−
−
V0CHAR
−*5
−
−
COP OFF LEAK current
−
V
7
4
VSS+0.1
V
7
4
VSS+0.1
V
8
5
100
nA
14
9
−
V
13
8
VC1+0.1
V
13
8
-
V
13
8
VC2+0.1
V
13
8
−
V
13
8
VSS+0.1
V
13
8
1.4
V
15
10
0 V battery charging function
0 V charging start voltage
*1.
*2.
*3.
*4.
*5.
8
If over current detection voltage 1 is 0.50 V, both over current detection voltages 1 and 2 are 0.54 to
0.55 V, but VIOV2 > VIOV1.
Voltage temperature factor 1 indicates over charge detection voltage, over charge release voltage, over
discharge detection voltage, and over discharge release voltage.
Voltage temperature factor 2 indicates over current detection voltage.
The DOP and COP logic must be established for the operating voltage.
This spec applies for only 0 V battery charging function available type.
Seiko Instruments Inc.
Rev.3.2_10
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
S-8233A Series
Measurement Circuits
(1) Measurement 1 Measurement circuit 1
Set V1, V2, and V3 to 3.5 V under normal condition. Increase V1 from 3.5 V gradually. The V1 voltage
when COP = 'H' is over charge detection voltage 1 (VCU1). Decrease V1 gradually. The V1 voltage when
COP = 'L' is over charge release voltage 1 (VCD1). Further decrease V1. The V1 voltage when DOP = 'H'
is over discharge voltage 1 (VDD1). Increase V1 gradually. The V1 voltage when DOP = 'L' is over
discharge release voltage 1 (VDU1).
Remark The voltage change rate is 150 V/s or less.
(2) Measurement 2 Measurement circuit 1
Set V1, V2, and V3 to 3.5 V under normal condition. Increase V2 from 3.5 V gradually. The V2 voltage
when COP = 'H' is over charge detection voltage 2 (VCU2). Decrease V2 gradually. The V2 voltage when
COP = 'L' is over charge release voltage 2 (VCD2). Further decrease V2. The V2 voltage when DOP = 'H'
is over discharge voltage 2 (VDD2). Increase V2 gradually. The V2 voltage when DOP = 'L' is over
discharge release voltage 2 (VDU2).
Remark The voltage change rate is 150 V/s or less.
(3) Measurement 3 Measurement circuit 1
Set V1, V2, and V3 to 3.5 V under normal condition. Increase V3 from 3.5 V gradually. The V3 voltage
when COP = 'H' is over charge detection voltage 3 (VCU3). Decrease V3 gradually. The V3 voltage when
COP = 'L' is over charge release voltage 3 (VCD3). Further decrease V3. The V3 voltage when DOP = 'H'
is over discharge voltage 3 (VDD3). Increase V3 gradually. The V3 voltage when DOP = 'L' is over
discharge release voltage 3 (VDU3).
Remark The voltage change rate is 150 V/s or less.
(4) Measurement 4 Measurement circuit 2
Set V1, V2, V3 to 3.5 V and V4 to 0 V under normal condition. Increase V4 from 0 V gradually. The V4
voltage when DOP = 'H' and COP = 'H', is over current detection voltage 1 (VIOV1).
Set V1, V2, and V3 to 3.5 V and V4 to 0 V under normal condition. Fix the COVT terminal at VSS,
increase V4 from 0 V gradually. The V4 voltage when DOP = 'H' and COP = 'H' is over current detection
voltage 2 (VIOV2).
Set V1, V2, and V3 to 3.5 V and V4 to 0 V under normal condition. Fix the COVT terminal at VSS,
increase V4 gradually from 0 V at 400 µs to 2 ms. The V4 voltage when DOP = 'H' and COP = 'H' is over
current detection voltage 3 (VIOV3).
(5) Measurement 5 Measurement circuit 3
Set S1 to ON, V1, V2, and V3 to 3.5 V, and V4 to 0 V under normal condition and measure current
consumption. I1 is the normal condition current consumption (IOPE), I2, the cell 2 current consumption
(ICELL2), and I3, the cell 3 current consumption (ICELL3).
Set S1 to ON, V1, V2, and V3 to 1.5 V, and V4 to 4.5 V under over discharge condition. Current
consumption I1 is power-down current consumption (IPDN).
(6) Measurement 6 Measurement circuit 3
Set S1 to ON, V1, V2, and V3 to 3.5 V, and V4 to 10.5 V under normal condition. V4/I4 is the internal
resistance between VCC and VMP (RVCM).
Set S1 to ON, V1, V2, and V3 to 1.5 V, and V4 to 4.1 V under over discharge condition. (4.5-V4)/I4 is the
internal resistance between VSS and VMP (RVSM).
Seiko Instruments Inc.
9
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
S-8233A Series
Rev.3.2_10
(7) Measurement 7 Measurement circuit 4
Set S1 to ON, S2 to OFF, V1, V2, and V3 to 3.5 V, and V4 to 0 V under normal condition. Increase V5
from 0 V gradually. The V5 voltage when I1 = 10 µA is DOP'L' voltage (VD0(L)).
Set S1 to OFF, S2 to ON, V1, V2, V3 to 3.5 V, and V4 to VIOV2+0.1 V under over current condition.
Increase V6 from 0 V gradually. The V6 voltage when I2 = 10 µA is the DOP'H' voltage (VDO(H)).
(8) Measurement 8 Measurement circuit 5
Set V1, V2, V3 to 3.5 V and V4 to 0 V under normal condition. Increase V5 from 0 V gradually. The V5
voltage when I1 = 10 µA is the COP'L' voltage (VC0(L)).
(9) Measurement 9 Measurement circuit 6
Set V1, V2, V3 to 3.5 V under normal condition. Increase V1 from 3.5 V to 4.5 V immediately (within 10
µs). The time after V1 becomes 4.5 V until COP goes 'H' is the over charge detection delay time 1 (tCU1).
Set V1, V2, V3 to 3.5 V under normal condition. Decrease V1 from 3.5 V to 1.9 V immediately (within 10
µs). The time after V1 becomes 1.9 V until DOP goes 'H' is the over discharge detection delay time 1
(tDD1).
(10) Measurement 10 Measurement circuit 6
Set V1, V2, V3 to 3.5 V under normal condition. Increase V2 from 3.5 V to 4.5 V immediately (within 10
µs). The time after V2 becomes 4.5 V until COP goes 'H' is the over charge detection delay time 2 (tCU2).
Set V1, V2, V3 to 3.5 V under normal condition. Decrease V2 from 3.5 V to 1.9 V immediately (within 10
µs). The time after V2 becomes 1.9 V until DOP goes 'H' is the over discharge detection delay time 2
(tDD2).
(11) Measurement 11 Measurement circuit 6
Set V1, V2, V3 to 3.5 V under normal condition. Increase V3 from 3.5 V to 4.5 V immediately (within 10
µs). The time after V3 becomes 4.5 V until COP goes 'H' is the over charge detection delay time 3 (tCU3).
Set V1, V2, V3 to 3.5 V under normal condition. Decrease V3 from 3.5 V to 1.9 V immediately (within 10
µs). The time after V3 becomes 1.9 V until DOP goes 'H' is the over discharge detection delay time 3
(tDD3).
(12) Measurement 12 Measurement circuit 7
Set V1, V2, V3 to 3.5 V and S1 to OFF under normal condition. Increase V4 from 0 V to 0.55 V
immediately (within 10 µs). The time after V4 becomes 0.55 V until DOP goes 'H' is the over current
detection delay time 1 (tI0V1).
Set V1, V2, V3 to 3.5 V and S1 to OFF under normal condition. Increase V4 from 0 V to 0.75 V
immediately (within 10 µs). The time after V4 becomes 0.75 V until DOP goes 'H' is the over current
detection delay time 2 (tIOV2)
Set S1 to ON to inhibit over discharge detection. Set V1, V2, V3 to 4.0 V and increase V4 from 0 V to 6.0
V immediately (within 1 µs) and decrease V1, V2, and V3 to 2.0 V at a time. The time after V4 becomes
6.0 V until DOP goes 'H' is the over current detection delay time 3 (tIOV3).
10
Seiko Instruments Inc.
Rev.3.2_10
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
S-8233A Series
(13) Measurement 13 Measurement circuit 8
Set S4 to ON, S1, S2, S3, S5, and S6 to OFF, V1, V2, V3 to 3.5 V and V4, V6, and V7 to 0 V under
normal condition. Increase V5 from 0 V gradually. The V5 voltage when I2 = 10 µA is the CD1'L' voltage
(VCD1(L))
Set S5 to ON, S1, S2, S3, S4, and S6 to OFF, V1, V2, and V3 to 3.5 V and V4, V5, and V7 to 0 V under
normal condition. Increase V6 from 0 V gradually. The V6 voltage when I3 = 10 µA is the CD2'L' voltage
(VCD2(L)).
Set S6 to ON, S1, S2, S3, S4, and S5 to OFF, V1, V2, and V3 to 3.5 V and V4, V5, and V6 to 0 V under
normal condition. Increase V7 from 0 V gradually. The V7 voltage when I4 = 10 µA is the CD3'L' voltage
(VCD3(L)).
Set S1 to ON, S2, S3, S4, S5, and S6 to OFF, V1 to 4.5 V, V2 and V3 to 3.5 V and V5, V6, and V7 to 0 V
under over charge condition. Increase V4 from 0 V gradually. The V4 voltage when I1 = 0.1 µA is the
CD1'H' voltage (VCD1(H)).
Set S2 to ON, S1, S3, S4, S5, and S6 to OFF, V2 to 4.5 V, V1 and V3 to 3.5 V and V5, V6, and V7 to 0 V
under over charge condition. Increase V4 from 0 V gradually. The V4 voltage when I1 = 0.1 µA is the
CD2'H' voltage (VCD2(H)).
Set S3 to ON, S1, S2, S4, S5, and S6 to OFF, V3 to 4.5 V, V1 and V2 to 3.5 V and V5, V6, and V7 to 0 V
under over charge condition. Increase V4 from 0 V gradually. The V4 voltage when I1 = 0.1 µA is the
CD3'H' voltage (VCD3(H)).
(14) Measurement 14 Measurement circuit 9
Set V1, V2, and V3 to 4.5 V under over charge condition. The current I1 flowing to COP terminal is COP
OFF LEAK current (ICOL).
(15) Measurement 15 Measurement circuit 10
Set V1, V2, and V3 to 0 V, and V8 to 2 V, and decrease V8 gradually. The V8 voltage when COP = 'H'
(VSS + 0.1 V or higher) is the 0V charge start voltage (V0CHAR).
Seiko Instruments Inc.
11
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
S-8233A Series
Rev.3.2_10
V4
1 MΩ
DOP
COP
VCC
V1
1 MΩ
DOP
VMP
CD1
V1
CTL
VC1
V2
CD2
V3
V2
CTL
CCT
S-8233A
CDT
VC2
V3
CD3
CD1
CD2
CDT
VC2
VMP
VC1
CCT
S-8233A
COP
VCC
CD3
COVT
VSS
COVT
VSS
Measurement circuit 1
Measurement circuit 2
V5
I4
S1
V4
I1
S2
I2
VCC
VMP
CD1
CTL
V1
DOP
I2
V1
VC1
V2
CD2
V4
COP
DOP
I1
S1
V6
CCT
S-8233A
VMP
CD1
CTL
VC1
V2
I3
COP
VCC
CCT
S-8233A
CD2
CDT
VC2
V3
CDT
VC2
CD3
V3
COVT
VSS
COVT
VSS
Measurement circuit 3
V5
CD3
Measurement circuit 4
I1
1 MΩ
V4
DOP
VCC
V1
DOP
COP
VMP
CD1
V1
CTL
CD2
VC2
V3
S-8233A
V2
CCT
CDT
V3
CD3
COVT
CD1
CTL
S-8233A
CCT
VC2
C1=0.47 µF
CDT
CD3
C2=0.1 µF
C3=0.1 µF
CD2
COVT
VSS
VSS
Measurement circuit 6
Measurement circuit 5
Figure 4 (1/2)
12
VMP
VC1
VC1
V2
COP
VCC
Seiko Instruments Inc.
C1
C2
C3
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
S-8233A Series
Rev.3.2_10
V4
1 MΩ
DOP
1 MΩ
COP
VMP
VCC
V1
CD1
V1
CTL
S4
VC1
V2
VC2
V3
CD3
CCT
S-8233A
S5
S1
C1=0.47 µF
CDT
C2=0.1 µF
C3=0.1 µF
C3
Measurement circuit 7
VMP
CD1
CTL
CD2
VC2
V3
CD3
I4
V7
VC2
CDT
COVT
VSS
1 MΩ
COP
VCC
S-8233A
CCT
S-8233A
V8
DOP
V1
VC1
V2
VC1
Measurement circuit 8
I1
DOP
CTL
CD3
V3
S6
COVT
VMP
CD2
I3
V6
S3
C2
VSS
V1
I2
V5
V2
C1
COP
CD1
S2
CD2
DOP
VCC
I1 V4
S1
COP
VCC
VMP
CD1
CTL
VC1
CCT
V2
CD2
CDT
VC2
V3
COVT
VSS
CD3
S-8233A
CCT
CDT
COVT
VSS
Measurement circuit 9
Measurement circuit 10
Figure 4 (2/2)
Seiko Instruments Inc.
13
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
S-8233A Series
Rev.3.2_10
Operation
Remark Refer to “Battery Protection IC Connection Example”.
Normal condition
This IC monitors the voltages of the three serially-connected batteries and the discharge current to control
charging and discharging. If the voltages of all the three batteries are in the range from the over
discharge detection voltage (VDD) to the over charge detection voltage (VCU), and the current flowing
through the batteries becomes equal or lower than a specified value (the VMP terminal voltage is equal or
lower than over current detection voltage 1), the charging and discharging FETs turn on. In this condition,
charging and discharging can be carried out freely. This condition is called the normal condition. In this
condition, the VMP and VCC terminals are shorted by the RVCM resistor.
Over current condition
This IC is provided with the three over current detection levels (VIOV1,VIOV2 and VIOV3) and the three over
current detection delay time (tIOV1,tIOV2 and tIOV3) corresponding to each over current detection level.
If the discharging current becomes equal to or higher than a specified value (the VMP terminal voltage is
equal to or higher than the over current detection voltage) during discharging under normal condition and
it continues for the over current detection delay time (tIOV) or longer, the discharging FET turns off to stop
discharging. This condition is called an over current condition. The VMP and VCC terminals are shorted
by the RVCM resistor at this time. The charging FET turns off.
When the discharging FET is off and a load is connected, the VMP terminal voltage equals the VSS
potential.
The over current condition returns to the normal condition when the load is released and the impedance
between the EB- and EB+ terminals (see Figure 9 for a connection example) is 100 MΩ or higher. When
the load is released, the VMP terminal, which and the VCC terminal are shorted with the RVCM resistor,
goes back to the VCC potential. The IC detects that the VMP terminal potential returns to over current
detection voltage 1 (VIOV1) or lower (or the over current detection voltage 2 (VIOV2) or lower if the COVT
terminal is fixed at the 'L' level and over current detection 1 is inhibited) and returns to the normal
condition.
Over charge condition
If one of the battery voltages becomes higher than the over charge detection voltage (VCU) during
charging under normal condition and it continues for the over charge detection delay time (tCU) or longer,
the charging FET turns off to stop charging. This condition is called the over charge condition. The 'H'
level signal is output to the conditioning terminal corresponding to the battery which exceeds the over
charge detection voltage until the battery becomes equal to lower than the over charge release voltage
(VCD). The battery can be discharged by connecting an Nch FET externally. The discharging current can
be limited by inserting R11, R12 and R13 resistors (see Figure 9 for a connection example). The VMP
and VCC terminals are shorted by the RVCM resistor under the over charge condition.
The over charge condition is released in two cases:
1) The battery voltage which exceeded the over charge detection voltage (VCU) falls below the over
charge release voltage (VCD), the charging FET turns on and the normal condition returns.
2) If the battery voltage which exceeded the over charge detection voltage (VCU) is equal or higher than
the over charge release voltage (VCD), but the charger is removed, a load is placed, and discharging
starts, the charging FET turns on and the normal condition returns.
The release mechanism is as follows: the discharge current flows through an internal parasitic diode of
the charging FET immediately after a load is installed and discharging starts, and the VMP terminal
voltage decreases by about 0.6 V from the VCC terminal voltage momentarily. The IC detects this
voltage (over current detection voltage 1 or higher), releases the over charge condition and returns to the
normal condition.
14
Seiko Instruments Inc.
Rev.3.2_10
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
S-8233A Series
Over discharge condition
If any one of the battery voltages falls below the over discharge detection voltage (VDD) during discharging
under normal condition and it continues for the over discharge detection delay time (tDD) or longer, the
discharging FET turns off and discharging stops. This condition is called the over discharge condition.
When the discharging FET turns off, the VMP terminal voltage becomes equal to the VSS voltage and the
IC's current consumption falls below the power-down current consumption (IPDN). This condition is called
the power-down condition. The VMP and VSS terminals are shorted by the RVSM resistor under the over
discharge and power-down conditions.
The power-down condition is canceled when the charger is connected and the voltage between VMP and
VSS is 3.0 V or higher (over current detection voltage 3). When all the battery voltages becomes equal to
or higher than the over discharge release voltage (VDU) in this condition, the over discharge condition
changes to the normal condition.
Delay circuits
The over charge detection delay time (tCU1 to tCU3), over discharge detection delay time (tDD1 to tDD3), and
over current detection delay time 1 (tIOV1) are changed with external capacitors (C4 to C6).
The delay times are calculated by the following equations:
Min. Typ. Max.
tCU[s] =Delay factor ( 1.07, 2.13, 3.19)×C4 [uF]
tDD[s] =Delay factor ( 0.20, 0.40, 0.60)×C5 [uF]
tIOV1[s]=Delay factor ( 0.10, 0.20, 0.30)×C6 [uF]
Caution: The delay time for over current detection 2 and 3 is fixed by an internal IC circuit. The
delay time cannot be changed via an external capacitor.
CTL terminal
If the CTL terminal is floated under normal condition, it is pulled up to the VCC potential in the IC, and both
the charging and discharging FETs turn off to inhibit charging and discharging. Both charging and
discharging are also inhibited by applying the VCC terminal to the CTL terminal externally. At this time,
the VMP and VCC terminals are shorted by the RVCM resistor.
When the CTL terminal becomes equal to VSS potential, charging and discharging are enabled and go
back to their appropriate conditions for the battery voltages.
Caution Please note unexpected behavior might occur when electrical potential difference
between the CTL pin ('L' level) and VSS is generated through the external filter
(RVSS and CVSS) as a result of input voltage fluctuations.
0 V battery charging function
This function is used to recharge the three serially-connected batteries after they self-discharge to 0 V.
When the 0 V charging start voltage (V0CHAR) or higher is applied to between VMP and VSS by connecting
the charger, the charging FET gate is fixed to VSS potential.
When the voltage between the gate sources of the charging FET becomes equal to or higher than the
turn-on voltage by the charger voltage, the charging FET turns on to start charging. At this time, the
discharging FET turns off and the charging current flows through the internal parasitic diode in the
discharging FET. If all the battery voltages become equal to or higher than the over discharge release
voltage (VDU), the normal condition returns.
Caution: In the products without 0 V battery charging function, the resistance between VCC and
VMP and between VSS and VMP are lower than the products with 0 V battery charging
function. It causes to that over charge detection voltage increases by the drop voltage of
R5 (see Figure 9 for a connection example) with sink current at VMP.
The COP output is undefined below 2.0 V on VCC-VSS voltage in the products without 0 V
battery charging function.
Seiko Instruments Inc.
15
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
S-8233A Series
Rev.3.2_10
Voltage temperature factor
Voltage temperature factor 1 indicates over charge detection voltage, over charge release voltage, over
discharge detection voltage, and over discharge release voltage.
Voltage temperature factor 2 indicates over current detection voltage.
The Voltage temperature factors 1 and 2 are expressed by the oblique line parts in Figure 5.
Ex. Voltage temperature factor of over charge detection voltage
VCU
[V]
+0.1 mV/°C
VCU25 is the over charge detection voltage at 25°C
VCU25
−0.1 mV/°C
−20
25
70
Ta [°C]
Figure 5
16
Seiko Instruments Inc.
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
S-8233A Series
Rev.3.2_10
Timing Chart
1. Overcharge detection
V1 battery
V2 battery
V3 battery
VCU
VCD
Battery
voltage
VDU
VDD
VCC
DOP
terminal
VSS
COP
terminal
Hi-z
Hi-z
Hi-z
Hi-z
VSS
VCHA
VCC
VIOV1
VSS
VMP
terminal
Charger
connected
Load
connected
Mode
Delay
Delay
Delay
Delay
Delay
*1
&
*1.
Normal mode,
Over charge mode,
Over discharge mode,
Over current mode
Remark The charger is assumed to charge with a constant current. VCHA indicates the open voltage of the charger.
Figure 6
2. Overdischarge detection
Battery
voltage
VCU
VCD
VDU
VDD
V1 battery
V3 battery
V2 battery
VCC
DOP
terminal
VSS
COP
terminal
VMP
terminal
Hi-z
VSS
VCHA
VCC
VIOV1
VSS
Charger
connected
Load
connected
Delay
Delay
Delay
Delay
Delay
Mode*1
*1. Normal mode, Over charge mode, Over discharge mode, Over current mode
Remark The charger is assumed to charge with a constant current. VCHA indicates the open voltage of the charger.
Figure 7
Seiko Instruments Inc.
17
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
S-8233A Series
Rev.3.2_10
3. Over current detection
V1, V2, and V3 batteries
VCU
VCD
Battery
voltage
VDU
VDD
VCC
DOP
terminal
VSS
COP
terminal
Hi-z
Hi-z
Hi-z
Hi-z
VSS
VCC
VMP
VIOV1
terminal
VIOV2
VIOV3
Charger
connected
Load
connected
Delay tIOV1
Delay
Delay tIOV2
Mode*1
tIOV3
Inhibit charging and
discharging
CTL terminal
VSS VCC
*1.
Normal mode,
Over charge mode,
Over discharge mode,
Over current mode
Remark The charger is assumed to charge with a constant current. VCHA indicates the open voltage of the charger.
Figure 8
18
Seiko Instruments Inc.
CTL terminal
VCC VSS
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
S-8233A Series
Rev.3.2_10
Battery Protection IC Connection Example
EB+
FET-A
FET-B
R6
1 MΩ
DOP
FET1
Battery 1
R11
C1
FET2
Battery 2
COP
VMP
Nch open
drain
VC1
GND: Normal operation
Floating: Inhibit charging
and discharging.
Over charge delay
time setting
CCT
S-8233A series
Over discharge delay
time setting
CDT
R2
VC2
C5
FET3
R13
Battery 3
C3
1 KΩ
C4
CD2
C2
R7
CTL
CD1
R1
R12
VCC
R5
10 KΩ
CD3
VSS
COVT
C6
FET-C
High: Inhibit over
discharge
detection.
Over current delay
time setting
R3
EB-
Figure 9
[Description of Figure 9]
R11, R12, and R13 are used to adjust the battery conditioning current. The conditioning current
during over charge detection is given by Vcu (over charge detection voltage)/R (R: resistance). To
disable the conditioning function, open CD1, CD2, and CD3.
The over charge detection delay time (tCU1 to tCU3), over discharge detection delay time (tDD1 to tDD3),
and over current detection delay time (tIOV1) are changed with external capacitors (C4 to C6). See
the electrical characteristics.
R6 is a pull-up resistor that turns FET-B off when the COP terminal is opened. Connect a
100 kΩ to 1 MΩ resistor.
R5 is used to protect the IC if the charger is connected in reverse. Connect a 10 kΩ to 50 kΩ
resistor.
If capacitor C6 is absent, rush current occurs when a capacitive load is connected and the IC enters
the over current mode. C6 must be connected to prevent it.
If capacitor C5 is not connected, the IC may enter the over discharge condition due to variations of
battery voltage when the over current occurs. In this case, a charger must be connected to return
to the normal condition. To prevent this, connect an at least 0.01 µF capacitor to C5.
If a leak current flows between the delay capacitor connection terminal (CCT, CDT, or COVT) and
VSS, the delay time increases and an error occurs. The leak current must be 100 nA or less.
Over discharge detection can be disabled by using FET-C. The FET-C off leak must be 0.1 µA or
less. If over discharge is inhibited by using this FET, the current consumption does not fall below
0.1 µA even when the battery voltage drops and the IC enters the over discharge detection mode.
R1, R2, and R3 must be 1 kΩ or less.
R7 is the protection of the CTL when the CTL terminal voltage higher than VCC voltage. Connect a
300 Ω to 5 kΩ resister. If the CTL terminal voltage never greater than the VCC voltage (ex. R7
connect to VSS), without R7 resistance is allowed .
Seiko Instruments Inc.
19
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
S-8233A Series
Rev.3.2_10
Caution 1. The above constants may be changed without notice.
2. If any electrostatic discharge of 2000 V or higher is not applied to the S-8233A series
with a human body model, R1, R2, R3, C1, C2, and C3 are unnecessary.
3. It has not been confirmed whether the operation is normal or not in circuits other than
the above example of connection. In addition, the example of connection shown above
and the constant do not guarantee proper operation. Perform through evaluation using
the actual application to set the constant.
Precautions
If a charger is connected in the over discharge condition and one of the battery voltages becomes
equal to or higher than the over charge release voltage (VCU) before the battery voltage which is
below the over discharge detection voltage (VDD) becomes equal to or higher than the over discharge
release voltage (VDU), the over discharge and over charge conditions are entered and the charging
and discharging FETs turn off. Both charging and discharging are disabled. If the battery voltage
which was higher than the over charge detection voltage (VCU) falls to the over charge release voltage
(VCD) due to internal discharging, the charging FET turns on.
If the charger is detached in the over charge and over discharge condition, the over charge condition
is released, but the over discharge condition remains. If the charger is connected again, the battery
condition is monitored after that. The charging FET turns off after the over charge detection delay
time, the over charge and over discharge conditions are entered.
If any one of the battery voltages is equal to or lower than the over discharge release voltage (VDU)
when they are connected for the first time, the normal condition may not be entered. If the VMP
terminal voltage is made equal to or higher than the VCC voltage (if a charger is connected), the
normal condition is entered.
If the CTL terminal floats in power-down mode, it is not pulled up in the IC, charging and discharging
may not be inhibited. However, the over discharge condition becomes effective. If the charger is
connected, the CTL terminal is pulled up, and charging and discharging are inhibited immediately.
Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in
electrostatic protection circuit.
SII claims no responsibility for any disputes arising out of or in connection with any infringement by
products including this IC of patents owned by a third party.
20
Seiko Instruments Inc.
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
S-8233A Series
Rev.3.2_10
Characteristics (typical characteristics)
1. Detection voltage temperature characteristics
Overcharge release voltage vs. temperature
Overcharge detection voltage vs. temperature
VCU=4.25[V]
VCD=4.10[V]
4.20
VCD (V)
VCU (V)
4.35
4.10
4.25
4.15
-40
-20
0
20
40
60
80
4.00
-40
100
-20
0
20
40
60
80
100
Ta(°C)
Ta(°C)
Overdischarge detection voltage vs. temperature
Overdischarge release voltage vs. temperature
VDD=2.35[V]
VDU=2.85[V]
2.95
VDU (V)
VDD (V)
2.45
2.35
2.85
2.25
-40
-20
0
20
40
60
80
2.75
-40
100
-20
0
Ta(°C)
20
40
60
80
100
Ta(°C)
Overcurrent1 detection voltage vs. temperature
Overcurrent2 detection voltage vs. temperature
VIOV1=0.3 [V]
VIOV2=0.6 [V]
0.65
VIOV2 (V)
VIOV1 (V)
0.35
0.60
0.30
0.55
0.25
-40
-20
0
20
40
60
80
100
-40
-20
Ta(°C)
0
20
40
60
80
100
Ta(°C)
Seiko Instruments Inc.
21
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
S-8233A Series
Rev.3.2_10
2. Current consumption temperature characteristics
Current consumption vs. temperature in normal mode
Current consumption vs. temperature in power-down mode
VCC=10.5 [V]
VCC=4.5 [V]
1.0
IPDN (nA)
IOPE (uA)
50
25
0.5
0
-40
-20
0
20
40
60
80
0.0
100
-40
-20
0
Ta(°C)
20
40
60
80
100
Ta(°C)
3. Delay time temperature characteristics
Overcharge detection time vs. temperature
Overdischarge detection time vs. temperature
C=0.47[uF]
VCC=11.5 [V]
60
tDD (ms)
tCU (s)
1.5
C=0.1[uF]
VCC=8.5 [V]
1.0
40
0.5
-40
-20
0
20
40
60
80
20
-40
100
-20
0
20
Ta(°C)
80
100
Overcurrent2 detection time vs. temperature
C=0.1[uF]
VCC=10.5 [V]
30
VCC=10.5 [V]
8
tIOV2 (ms)
tIOV1 (ms)
60
Ta(°C)
Overcurrent1 detection time vs. temperature
20
10
-40
5
2
-20
0
20
40
60
80
100
-40
-20
0
20
Ta(°C)
Ta(°C)
22
40
Seiko Instruments Inc.
40
60
80
100
BATTERY PROTECTION IC FOR 3-SERIAL-CELL PACK
S-8233A Series
Rev.3.2_10
Overcurrent3 (load short) detection time vs. temperature
VCC=6.0 [V]
tIOV3 (ms)
0.40
0.25
0.10
-40
-20
0
20
40
60
80
100
Ta(°C)
4. Delay time vs. power supply voltage
Over current 3 (load short) detection time vs. power supply voltage
Ta =25(°C)
tIOV3(ms)
1.0
0.5
0
3
6
9
VCC(V)
12
15
Caution Please design all applications of the S-8233A Series with safety in mind.
Seiko Instruments Inc.
23
10.06 (10.5 max.)
+0.05
0.2 -0.02
1.27
0.4
+0.1
-0.05
No. FE014-A-P-SD-1.1
TITLE
SOP14-A-PKG Dimensions
No.
FE014-A-P-SD-1.1
SCALE
UNIT
mm
Seiko Instruments Inc.
(10 pitches:40.0±0.1)
+0.1
4.0±0.1
ø1.5 -0
2.0±0.1
12.0±0.1
0.3±0.05
ø1.6±0.1
2.7±0.1
8.8±0.1
5.4±0.2
+0.4
8.5 -0.2
8
7
14
1
Feed direction
No. FE014-A-C-SD-1.1
TITLE
SOP14-A-Carrier Tape
FE014-A-C-SD-1.1
No.
SCALE
UNIT
mm
Seiko Instruments Inc.
ø10
17.4±1.0
21.4±1.0
Enlarged drawing in the central part
ø21.0±0.8
2.0±0.5
ø13.0±0.2
No. FE014-A-R-SD-1.1
SOP14-A-Reel
TITLE
FE014-A-R-SD-1.1
No.
SCALE
UNIT
QTY.
2,000
mm
Seiko Instruments Inc.
5.1±0.2
0.65
16
9
1
8
0.17±0.05
0.22±0.08
No. FT016-A-P-SD-1.1
TITLE
TSSOP16-A-PKG Dimensions
No.
FT016-A-P-SD-1.1
SCALE
UNIT
mm
Seiko Instruments Inc.
+0.1
4.0±0.1
ø1.5 -0
0.3±0.05
2.0±0.1
8.0±0.1
1.5±0.1
ø1.6±0.1
(7.2)
4.2±0.2
+0.4
6.5 -0.2
1
16
8
9
Feed direction
No. FT016-A-C-SD-1.1
TITLE
TSSOP16-A-Carrier Tape
FT016-A-C-SD-1.1
No.
SCALE
UNIT
mm
Seiko Instruments Inc.
21.4±1.0
17.4±1.0
+2.0
17.4 -1.5
Enlarged drawing in the central part
ø21±0.8
2.0±0.5
ø13.0±0.2
No. FT016-A-R-SD-1.1
TITLE
TSSOP16-A- Reel
No.
FT016-A-R-SD-1.1
SCALE
UNIT
QTY.
2,000
mm
Seiko Instruments Inc.
•
•
•
•
•
•
The information described herein is subject to change without notice.
Seiko Instruments Inc. is not responsible for any problems caused by circuits or diagrams described herein
whose related industrial properties, patents, or other rights belong to third parties. The application circuit
examples explain typical applications of the products, and do not guarantee the success of any specific
mass-production design.
When the products described herein are regulated products subject to the Wassenaar Arrangement or other
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Use of the information described herein for other purposes and/or reproduction or copying without the
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Although Seiko Instruments Inc. exerts the greatest possible effort to ensure high quality and reliability, the
failure or malfunction of semiconductor products may occur. The user of these products should therefore
give thorough consideration to safety design, including redundancy, fire-prevention measures, and
malfunction prevention, to prevent any accidents, fires, or community damage that may ensue.