STMICROELECTRONICS USBULC6-2F3

USBULC6-2F3
IPAD™
Dual ultra low capacitance protection for high speed USB
Main application
■
Hi-Speed USB port in wireless handsets (up to
480 Mb/s according to USB 2.0 High Speed
Specification)
Features
■
Ultra low diode capacitance (1.2 pF max)
■
Two data lines (D+ and D-) protected against
15 kV ESD
■
Breakdown Voltage VBR = 6.0 V min
■
Flip-Chip 400 µm pitch, lead-free
■
Very low leakage current
■
Very small PCB area
■
RoHS compliant
Flip-Chip
(4 Bumps)
Pin configuration (bump side)
A
B
1
2
Description
The USBULC6-2F3 is a monolithic, application
specific discrete device dedicated to ESD
protection of high speed interfaces.
Configuration
A1
B1
Its ultra low line capacitance secures a high level
of signal integrity without compromizing the
protection of downstream sensitive chips against
the most stringently characterized ESD strikes.
Benefits
■
Minimized impact on rise and fall times for
maximum data integrity
■
Low PCB space occupation
■
Higher reliability offered by monolithic
integration
Complies with the following standards:
IEC 61000-4-2:
A2
Note: B1 and B2 bumps must be
grounded on the PCB together
Order code
15 kV (air discharge)
8 kV (contact discharge)
MIL STD 883G - Method 3015.7
25 kV (Human body model)
December 2006
B2
Part Number
Marking
USBULC6-2F3
EH
TM: IPAD is a trademark of STMicroelectronics
Rev 1
1/8
www.st.com
Characteristics
1
USBULC6-2F3
Characteristics
Table 1.
Absolute Maximum Ratings (Tamb = 25° C)
Symbol
Parameter
Value
Unit
VPP
ESD discharge IEC 61000-4-2, air discharge
ESD discharge IEC 61000-4-2, contact discharge
15
8
kV
PPP
Peak pulse power dissipation (8/20 µs)
60
W
Maximum junction temperature
125
°C
Tj
Top
Operating temperature range
-30 to + 85
°C
Tstg
Storage temperature range
-55 to +150
°C
Table 2.
Electrical characteristics (Tamb = 25° C)
Symbol
Parameter
VBR
Breakdown voltage
IRM
Leakage current @ VRM
VRM
Stand-off voltage
VCL
Clamping voltage
I
IF
Dynamic impedance
IPP
Peak pulse current
αT
Voltage temperature coefficient
VF
Forward voltage drop
Slope = 1/Rd
Test conditions
Min.
VBR
IR = 1 mA
IRM
VRM = 3 V
Rd
Exponential wave form 8/20 µs, Ipp = 1 to 5 A
αT
Figure 1.
IPP
Typ.
6
IR = 1 mA
Cline
V
IRM
Rd
Symbol
VF
VCL VBR VRM
Max.
Unit
9
V
100
nA
Ω
1.6
5
VLINE = 0 V, VOSC = 30 mV, F = 1 MHz
1.2
Application diagram
USB CONNECTOR
Vbus
Vbus
DB2
A2
B1
A1
D-
D+
D+
GND
GND
TO USB TRANSCEIVER
2/8
10-4/°
pF
C
USBULC6-2F3
Figure 2.
Characteristics
Eye diagram, board only (according Figure 3.
to USB High Speed)
USBULC6-2F3
480 Mb/s
Board
480 Mb/s
Horiz: 350 ps/div
Ver: 200 mV/div
Horiz: 350 ps/div
Ver: 200 mV/div
Figure 4.
Eye diagram, board with
USBULC6-2F3 (according to
USB 2.0 High Speed)
ESD response to IEC 61000-4-2
(+15 kV air discharge)
Figure 5.
ESD response to IEC 61000-4-2
(-15 kV air discharge
X: 50 ns/division
Y: 20 V/division
1 Gs/s
Figure 6.
1.2
X: 50 ns/division
Y: 20 V/division
1 Gs/s
Junction capacitance versus
frequency (typical values)
Figure 7.
C(pF)
0.00
VOSC=30 mVRMS
Tj=25 °C
1.1
Analog crosstalk measurements
dB
USBULC6 -2F3
1.0
0.9
-30.00
0.8
0.7
0.6
-60.00
0.5
0.4
0.3
-90.00
0.2
0.1
F(Hz)
F (Hz)
0.0
1.E+07
1.E+08
1.E+09
-120.00
100.0k
1.0M
10.0M
100.0M
1.0G
3/8
Characteristics
Figure 8.
USBULC6-2F3
S21 (dB) attenuation measurements
dB
USBULC6-2F3
0.00
-2.00
-4.00
-6.00
-8.00
F (Hz)
-10.00
100.0k
Figure 9.
1.0M
10.0M
100.0M
1.0G
Digital crosstalk
90%
INPUT:
1 V/div
0 mV offset
2 ns/div
5 Gs/s
Rise time = 1.647 ns
10%
OUTPUT:
100 m V/div
-300 mV offset
2 ns/div
5 Gs/s
Vpkpk = 205 mV
Figure 10. Relative variation of peak pulse
power versus initial junction
temperature
1.1
Figure 11. Peak pulse power versus
exponential pulse duration
PPP[T j initial] / PPP [T j initial=25°C]
1000
PPP(W)
Tj initial = 25° C
1.0
0.9
0.8
0.7
0.6
100
0.5
0.4
0.3
0.2
0.1
tP(µs)
Tj(°C)
10
0.0
0
4/8
25
50
75
100
125
150
1
10
100
USBULC6-2F3
Ordering information scheme
Figure 12. Clamping voltage versus peak
pulse current (typical values,
exponential waveform)
100.0
Figure 13. Relative variation of leakage
current versus junction
temperature (typical values)
IPP(A)
IR [T j] / IR [T j=25°C]
1.E+02
VR =3 V
10.0
1.E+01
1.0
8/20 µs
Tj initial =25° C
VCL(V)
T j(°C)
1.E+00
0.1
0
2
10
20
30
40
50
60
70
25
50
75
100
125
Ordering information scheme
USB ULC 6 - 2 F3
USB protection
Ultra Low Capacitance
Breakdown voltage
6 = 6 VMIN
Number of lines
2 = 2 lines
Package
F = Flip-Chip
3: Lead free, Pitch = 400 µm, Bump = 255 µm
5/8
Package information
3
USBULC6-2F3
Package information
400 µm ± 40
Figure 14. Flip-Chip dimensions
605 µm ± 55
0.97 mm ± 30µm
400 µm ± 40
0.92 mm ± 30 µm
255 µm ± 40
Figure 15. Foot print recommendations Figure 16. Marking
Copper pad Diameter:
220µm recommended
260µm maximum
Solder mask opening:
300µm minimum
Solder stencil opening :
220µm recommended
6/8
Dot
xx = marking
z = manufacturing location
yww = datecode
(y = year
ww = week)
x x z
y ww
USBULC6-2F3
Ordering information
Figure 17. Flip-Chip tape and reel specifications
Dot identifying Pin A1 location
3.5 +/- 0.1
1.07
xxz
yww
1.02
xxz
yww
xxz
yww
8 +/- 0.3
0.71
1.75 +/- 0.1
Ø 1.5 +/- 0.1
4 +/- 0.1
4 +/- 0.1
User direction of unreeling
All dimensions in mm
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a lead-free second level interconnect. The category of
second level interconnect is marked on the inner box label, in compliance with JEDEC
Standard JESD97. The maximum ratings related to soldering conditions are also marked on
the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available
at: www.st.com.
Note:
More information is available in the application notes:
AN2348: “400 µm Flip-Chip: Package description and recommendations for use”
AN1751: "EMI Filters: Recommendations and measurements"
4
Ordering information
5
Part Number
Marking
Package
Weight
Base qty
Delivery mode
USBULC6-2F3
EH
Flip-Chip
1.16 mg
5000
Tape and reel (7”)
Revision history
Date
Revision
15-Dec-2006
1
Changes
Initial release
7/8
USBULC6-2F3
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