19-3826; Rev 1; 6/07 KIT ATION EVALU E L B AVAILA 10-Bit, 45Msps, Ultra-Low-Power Analog Front-End Ordering Information PART* PIN-PACKAGE PKG CODE MAX19707ETM 48 Thin QFN-EP** T4877-4 MAX19707ETM+ 48 Thin QFN-EP** T4877-4 *All devices are specified over the -40°C to +85°C operating range. **EP = Exposed paddle. +Denotes lead-free package. ♦ Serial-Interface Control ♦ Versatile Power-Control Circuits Shutdown, Standby, Idle, Tx/Rx Disable ♦ Miniature 48-Pin Thin QFN Package (7mm x 7mm x 0.8mm) DOUT SHDN CS SCLK DIN T/R DAC3 TOP VIEW ADC1 ADC2 VDD GND VDD Pin Configuration 36 35 34 33 32 31 30 29 28 27 26 25 DAC2 DAC1 37 24 38 23 VDD IDN IDP GND 39 22 40 21 41 20 42 19 VDD QDN QDP 43 18 REFIN COM 46 47 14 REFN 48 13 MAX19707 17 44 16 45 EXPOSED PADDLE (GND) 1 2 3 4 5 6 7 8 15 D9 D8 D7 D6 OVDD OGND D5 D4 D3 D2 D1 D0 9 10 11 12 VDD Portable Communication Equipment ♦ 10-Bit, 333ksps Aux-ADC with 4:1 Input Mux and Data Averaging ♦ Excellent Gain/Phase Match ±0.03° Phase, ±0.01dB Gain (Rx ADC) at fIN = 5.5MHz ♦ Multiplexed Parallel Digital I/O GND VoIP Terminals 802.11a/b/g WLAN ♦ Programmable Tx DAC Common-Mode DC Level and I/Q Offset Trim ♦ Excellent Dynamic Performance SNR = 54.2dB at fIN = 5.5MHz (Rx ADC) SFDR = 73.2dBc at fOUT = 2.2MHz (Tx DAC) ♦ Three 12-Bit, 1µs Aux-DACs GND VDD QAN QAP WiMAX CPEs ♦ Ultra-Low Power 84.6mW at fCLK = 45MHz, Fast Mode 77.1mW at fCLK = 45MHz, Slow Mode Low-Current Standby and Shutdown Modes IAP IAN GND CLK Applications ♦ Dual, 10-Bit, 45Msps Rx ADC and Dual, 10-Bit, 45Msps Tx DAC REFP VDD The MAX19707 is an ultra-low-power, mixed-signal analog front-end (AFE) designed for power-sensitive communication equipment. Optimized for high dynamic performance at ultra-low power, the device integrates a dual, 10-bit, 45Msps receive (Rx) ADC; dual, 10-bit, 45Msps transmit (Tx) DAC; three fast-settling 12-bit aux-DAC channels for ancillary RF front-end control; and a 10-bit, 333ksps housekeeping aux-ADC. The typical operating power in Tx-Rx FAST mode is 84.6mW at a 45MHz clock frequency. The Rx ADCs feature 54.2dB SNR and 71.2dBc SFDR at fIN = 5.5MHz and fCLK = 45MHz. The analog I/Q input amplifiers are fully differential and accept 1.024VP-P full-scale signals. Typical I/Q channel matching is ±0.03° phase and ±0.01dB gain. The Tx DACs feature 73.2dBc SFDR at fOUT = 2.2MHz and fCLK = 45MHz. The analog I/Q full-scale output voltage is ±400mV differential. The Tx DAC common-mode DC level is programmable from 0.71V to 1.05V. The I/Q channel offset is programmable to optimize radio lineup sideband/carrier suppresion. The typical I/Q channel matching is ±0.01dB gain and ±0.07° phase. The Rx ADC and Tx DAC share a single, 10-bit parallel, high-speed digital bus allowing half-duplex operation for time-division duplex (TDD) applications. A 3-wire serial interface controls power-management modes, the aux-DAC channels, and the aux-ADC channels. The MAX19707 operates on a single 2.7V to 3.3V analog supply and 1.8V to 3.3V digital I/O supply. The MAX19707 is specified for the extended (-40°C to +85°C) temperature range and is available in a 48-pin, thin QFN package. The Selector Guide at the end of the data sheet lists other pin-compatible versions in this AFE family. Features THIN QFN Functional Diagram and Selector Guide appear at end of data sheet. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX19707 General Description MAX19707 10-Bit, 45Msps, Ultra-Low-Power Analog Front-End ABSOLUTE MAXIMUM RATINGS VDD to GND, OVDD to OGND ..............................-0.3V to +3.6V GND to OGND.......................................................-0.3V to +0.3V IAP, IAN, QAP, QAN, IDP, IDN, QDP, QDN, DAC1, DAC2, DAC3 to GND .....................-0.3V to VDD ADC1, ADC2 to GND.................................-0.3V to (VDD + 0.3V) REFP, REFN, REFIN, COM to GND-0.3V to (VDD + 0.3V)D0–D9, DOUT, T/R, SHDN, SCLK, DIN, CS, CLK to OGND .....................................-0.3V to (OVDD + 0.3V) Continuous Power Dissipation (TA = +70°C) 48-Pin Thin QFN (derate 27.8mW/°C above +70°C) .....2.22W Thermal Resistance θJA ..................................................36°C/W Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-60°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 45MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33µF, unless otherwise noted. CL < 5pF on all aux-DAC outputs. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 3.0 3.3 V VDD V POWER REQUIREMENTS Analog Supply Voltage VDD 2.7 Output Supply Voltage OVDD 1.8 VDD Supply Current 2 Ext1-Tx, Ext3-Tx, and SPI2-Tx states; transmit DAC operating mode (Tx): fCLK = 45MHz, fOUT = 2.2MHz on both channels; aux-DACs ON and at midscale, aux-ADC ON 16.5 Ext2-Tx, Ext4-Tx, and SPI4-Tx states; transmit DAC operating mode (Tx): fCLK = 45MHz, fOUT = 2.2MHz on both channels; aux-DACs ON and at midscale, aux-ADC ON 29.8 35 mA Ext1-Rx, Ext4-Rx, and SPI3-Rx states; receive ADC operating mode (Rx): fCLK = 45MHz, fIN = 5.5MHz on both channels; aux-DACs ON and at midscale, aux-ADC ON 28.2 Ext2-Rx, Ext3-Rx, and SPI1-Rx states; receive ADC operating mode (Rx): fCLK = 45MHz, fIN = 5.5MHz on both channels; aux-DACs ON and at midscale, aux-ADC ON 25.7 _______________________________________________________________________________________ 34 10-Bit, 45Msps, Ultra-Low-Power Analog Front-End (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 45MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33µF, unless otherwise noted. CL < 5pF on all aux-DAC outputs. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL VDD Supply Current CONDITIONS MIN TYP MAX Standby mode: CLK = 0 or OVDD; aux-DACs ON and at midscale, aux-ADC ON 3.2 5 Idle mode: fCLK = 45MHz; aux-DACs ON and at midscale, aux-ADC ON 12.1 mA 15 1 µA Ext1-Rx, Ext2-Rx, Ext3-Rx, Ext4-Rx, SPI1-Rx, SPI3-Rx states; receive ADC operating mode (Rx): fCLK = 45MHz, fIN = 5.5MHz on both channels; aux-DACs ON and at midscale, aux-ADC ON 7.7 mA Ext1-Tx, Ext2-Tx, Ext3-Tx, Ext4-Tx, SPI2-Tx, SPI4-Tx states; transmit DAC operating mode (Tx), fCLK = 45MHz, fOUT = 2.2MHz on both channels; aux-DACs ON and at midscale, aux-ADC ON 485 µA Standby mode: CLK = 0 or OVDD; aux-DACs ON and at midscale, aux-ADC ON 1 Shutdown mode: CLK = 0 or OVDD OVDD Supply Current UNITS Idle mode: fCLK = 45MHz; aux-DACs ON and at midscale, aux-ADC ON 76 Shutdown mode: CLK = 0 or OVDD 1 Rx ADC DC ACCURACY Resolution N 10 Bits Integral Nonlinearity INL ±1.6 LSB Differential Nonlinearity DNL ±0.7 LSB Offset Error Residual DC offset error Gain Error Include reference error DC Gain Matching -5 ±0.5 +5 %FS -5.5 ±1.0 +5.5 %FS -0.15 ±0.01 +0.15 dB Offset Matching ±13 LSB Gain Temperature Coefficient ±30 ppm/°C Offset error (VDD ±5%) ±0.4 LSB Gain error (VDD ±5%) ±0.1 %FS Power-Supply Rejection PSRR _______________________________________________________________________________________ 3 MAX19707 ELECTRICAL CHARACTERISTICS (continued) MAX19707 10-Bit, 45Msps, Ultra-Low-Power Analog Front-End ELECTRICAL CHARACTERISTICS (continued) (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 45MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33µF, unless otherwise noted. CL < 5pF on all aux-DAC outputs. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Rx ADC ANALOG INPUT Input Differential Range VID Input Common-Mode Voltage Range VCM Input Impedance RIN Differential or single-ended inputs Switched capacitor load CIN ±0.512 V VDD / 2 V 120 kΩ 5 pF Rx ADC CONVERSION RATE Maximum Clock Frequency fCLK Data Latency (Figure 3) (Note 2) 45 Channel I 5 Channel Q 5.5 MHz Clock Cycles Rx ADC DYNAMIC CHARACTERISTICS (Note 3) Signal-to-Noise Ratio SNR Signal-to-Noise Plus Distortion SINAD Spurious-Free Dynamic Range SFDR Third-Harmonic Distortion HD3 Intermodulation Distortion fIN = 5.5MHz, fCLK = 45MHz 52.5 fIN = 22MHz, fCLK = 45MHz fIN = 5.5MHz, fCLK = 45MHz 52.2 fIN = 22MHz, fCLK = 45MHz fIN = 5.5MHz, fCLK = 45MHz fIN = 22MHz, fCLK = 45MHz 54.2 dB 54.1 54.1 dB 54 62.1 71.2 dBc 70.4 fIN = 5.5MHz, fCLK = 45MHz -78.1 fIN = 22MHz, fCLK = 45MHz -73.1 IMD f1 = 1.8MHz, -7dBFS; f2 = 1MHz, -7dBFS -68.6 dBc Third-Order Intermodulation Distortion IM3 f1 = 1.8MHz, -7dBFS; f2 = 1MHz, -7dBFS -79.2 dBc Total Harmonic Distortion THD fIN = 5.5MHz, fCLK = 45MHz -68.4 fIN = 22MHz, fCLK = 45MHz -68.8 Aperture Delay Overdrive Recovery Time 1.5x full-scale input dBc -61.5 dBc 3.5 ns 2 ns -90 dB Rx ADC INTERCHANNEL CHARACTERISTICS Crosstalk Rejection fINX,Y = 5.5MHz at -0.5dBFS, fINX,Y = 1.8MHz at -0.5dBFS (Note 4) Amplitude Matching fIN = 5.5MHz at -0.5dBFS (Note 5) ±0.01 dB Phase Matching fIN = 5.5MHz at -0.5dBFS (Note 5) ±0.03 Degrees 4 _______________________________________________________________________________________ 10-Bit, 45Msps, Ultra-Low-Power Analog Front-End (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 45MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33µF, unless otherwise noted. CL < 5pF on all aux-DAC outputs. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Tx DAC DC ACCURACY Resolution N Integral Nonlinearity INL Differential Nonlinearity DNL Residual DC Offset VOS 10 ±0.3 LSB Guaranteed monotonic (Note 6) -1 ±0.2 +1 TA ≥ +25°C -4 ±1 +4 TA < +25°C -4.5 ±1 +4.5 Include reference error (peak-to-peak error) Full-Scale Gain Error Bits TA ≥ +25°C -30 +30 TA < +25°C -40 +40 LSB mV mV Tx DAC DYNAMIC PERFORMANCE DAC Conversion Rate fCLK In-Band Noise Density ND (Note 2) fOUT = 2.2MHz, fCLK = 45MHz 45 Third-Order Intermodulation Distortion IM3 f1 = 2MHz, f2 = 2.2MHz Glitch Impulse dBc/Hz 80 dBc 10 pV•s 73.2 dBc Spurious-Free Dynamic Range to Nyquist SFDR fCLK = 45MHz, fOUT = 2.2MHz Total Harmonic Distortion to Nyquist THD fCLK = 45MHz, fOUT = 2.2MHz -71 Signal-to-Noise Ratio to Nyquist SNR fCLK = 45MHz, fOUT = 2.2MHz 57.1 60 MHz -130.6 -59 dB dB Tx DAC INTERCHANNEL CHARACTERISTICS I-to-Q Output Isolation fOUTX,Y = 2MHz, fOUTX,Y = 2.2MHz 85 TA ≥ +25°C -0.3 TA < +25°C -0.42 Gain Mismatch Between DAC Outputs Measured at DC Phase Mismatch Between DAC Outputs fOUT = 2.2MHz, fCLK = 45MHz Differential Output Impedance ±0.01 dB +0.3 +0.42 dB ±0.07 Degrees 800 Ω Tx DAC ANALOG OUTPUT Full-Scale Output Voltage VFS ±400 Bits CM1 = 0, CM0 = 0 (default) Output Common-Mode Voltage VCOM 1.0 1.05 Bits CM1 = 0, CM0 = 1 0.95 Bits CM1 = 1, CM0 = 0 0.80 Bits CM1 = 1, CM0 = 1 0.71 mV 1.1 V _______________________________________________________________________________________ 5 MAX19707 ELECTRICAL CHARACTERISTICS (continued) MAX19707 10-Bit, 45Msps, Ultra-Low-Power Analog Front-End ELECTRICAL CHARACTERISTICS (continued) (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 45MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33µF, unless otherwise noted. CL < 5pF on all aux-DAC outputs. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Rx ADC–Tx DAC INTERCHANNEL CHARACTERISTICS ADC fINI = fINQ = 5.5MHz, DAC fOUTI = fOUTQ = 2.2MHz, fCLK = 45MHz Receive Transmit Isolation AUXILIARY ADC (ADC1, ADC2) Resolution Full-Scale Reference N VREF AD1 = 0 (default) 85 dB 10 Bits 2.048 AD1 = 1 V VDD Analog Input Range 0 to VREF V Analog Input Impedance At DC 500 kΩ Input-Leakage Current Measured at unselected input from 0 to VREF ±0.1 µA Gain Error GE Zero-Code Error Includes reference error -5 +5 %FS ZE 2 mV Differential Nonlinearity DNL ±0.53 LSB Integral Nonlinearity INL ±0.45 LSB 210 µA 12 Bits ±1.25 LSB Supply Current AUXILIARY DACs (DAC1, DAC2, DAC3) Resolution N Integral Nonlinearity INL Differential Nonlinearity DNL Gain Error GE (Note 6) Guaranteed monotonic over codes 100 to 4000 (Note 6) -1.0 RL > 200kΩ Zero-Code Error ZE Output-Voltage Low VOL RL > 200kΩ Output-Voltage High VOH RL > 200kΩ ±0.65 +1.1 ±0.7 LSB %FS ±0.6 %FS 0.1 2.56 V V DC Output Impedance DC output at midscale 4 Ω Settling Time From 1/4 FS to 3/4 FS, within ±10 LSB 1 µs Glitch Impulse From 0 to FS transition 24 nV•s Rx ADC–Tx DAC TIMING CHARACTERISTICS CLK Rise to Channel-I Output Data Valid tDOI Figure 3 (Note 6) 5.4 6.5 8.1 ns CLK Fall to Channel-Q Output Data Valid tDOQ Figure 3 (Note 6) 7.3 8.8 11.1 ns I-DAC DATA to CLK Fall Setup Time tDSI Figure 5 (Note 6) 9 6 _______________________________________________________________________________________ ns 10-Bit, 45Msps, Ultra-Low-Power Analog Front-End (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 45MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33µF, unless otherwise noted. CL < 5pF on all aux-DAC outputs. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Q-DAC DATA to CLK Rise Setup Time tDSQ Figure 5 (Note 6) 9 ns CLK Fall to I-DAC Data Hold Time tDHI Figure 5 (Note 6) -4 ns CLK Rise to Q-DAC Data Hold Time tDHQ Figure 5 (Note 6) -4 ns CLK Duty Cycle 50 CLK Duty-Cycle Variation Digital Output Rise/Fall Time 20% to 80% % ±15 % 2.6 ns SERIAL-INTERFACE TIMING CHARACTERISTICS (Figure 6, Note 6) Falling Edge of CS to Rising Edge of First SCLK Time tCSS 10 ns DIN to SCLK Setup Time tDS 10 ns DIN to SCLK Hold Time tDH 0 ns SCLK Pulse-Width High tCH 25 ns SCLK Pulse-Width Low tCL 25 ns SCLK Period tCP 50 ns SCLK to CS Setup Time tCS 10 ns CS High Pulse Width tCSW CS High to DOUT Active High tCSD 80 ns Bit AD0 set 200 ns Bit AD0 set, no averaging (see Table 14), fCLK = 45MHz, CLK divider = 16 (see Table 15) 4.27 µs tDCS Bit AD0, AD10 set 200 ns SCLK Low to DOUT Data Out tCD Bit AD0, AD10 set CS High to DOUT High Impedance tCHZ Bit AD0, AD10 set CS High to DOUT Low (Aux-ADC Conversion Time) DOUT Low to CS Setup Time tCONV 14.5 200 ns ns MODE-RECOVERY TIMING CHARACTERISTICS (Figure 7) Shutdown Wake-Up Time Idle Wake-Up Time (With CLK) Standby Wake-Up Time tWAKE,SD tWAKE,ST0 tWAKE,ST1 From shutdown to Rx mode, ADC settles to within 1dB SINAD 85.2 From shutdown to Tx mode, DAC settles to within 10 LSB error 28.2 From idle to Rx mode with CLK present during idle, ADC settles to within 1dB SINAD 9.8 From idle to Tx mode with CLK present during idle, DAC settles to 10 LSB error 6.4 From standby to Rx mode, ADC settles to within 1dB SINAD 13.7 µs µs µs From standby to Tx mode, DAC settles to 10 LSB error 24 _______________________________________________________________________________________ 7 MAX19707 ELECTRICAL CHARACTERISTICS (continued) MAX19707 10-Bit, 45Msps, Ultra-Low-Power Analog Front-End ELECTRICAL CHARACTERISTICS (continued) (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 45MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33µF, unless otherwise noted. CL < 5pF on all aux-DAC outputs. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Enable Time from Tx to Rx, (Ext2Tx to Ext2-Rx, Ext4-Tx to Ext4-Rx, and SPI4-Tx to SPI3-Rx States) tENABLE, RX ADC settles to within 1dB SINAD 500 ns Enable Time from Rx to Tx, (Ext1Rx to Ext1-Tx, Ext4-Rx to Ext4-Tx, and SPI3-Rx to SPI4-Tx States) tENABLE, TX DAC settles to within 10 LSB error 500 ns Enable Time from Tx to Rx, (Ext1Tx to Ext1-Rx, Ext3-Tx to Ext3-Rx, and SPI1-Tx to SPI2-Rx States) tENABLE, RX ADC settles to within 1dB SINAD 4.1 µs Enable Time from Rx to Tx, (Ext2Rx to Ext2-Tx, Ext3-Rx to Ext3-Tx, and SPI1-Rx to SPI2-Tx States) tENABLE, TX DAC settles to within 10 LSB error 7.0 µs 0.256 V INTERNAL REFERENCE (VREFIN = VDD; VREFP, VREFN, VCOM levels are generated internally) Positive Reference VREFP - VCOM Negative Reference VREFN - VCOM -0.256 V VCOM VDD / 2 VDD / 2 VDD / 2 - 0.15 + 0.15 V Maximum REFP/REFN/COM Source Current ISOURCE 2 mA Maximum REFP/REFN/COM Sink Current ISINK 2 mA Differential Reference Output VREF Common-Mode Output Voltage Differential Reference Temperature Coefficient VREFP - VREFN REFTC +0.489 +0.512 ±10 +0.534 V ppm/°C BUFFERED EXTERNAL REFERENCE (external VREFIN = 1.024V applied; VREFP, VREFN, VCOM levels are generated internally) Reference Input Voltage VREFIN 1.024 VREFP - VREFN V Differential Reference Output VDIFF 0.512 V Common-Mode Output Voltage VCOM VDD / 2 V Maximum REFP/REFN/COM Source Current ISOURCE 2 mA Maximum REFP/REFN/COM Sink Current ISINK 2 mA REFIN Input Current -0.7 µA REFIN Input Resistance 500 kΩ 8 _______________________________________________________________________________________ 10-Bit, 45Msps, Ultra-Low-Power Analog Front-End (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 45MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33µF, unless otherwise noted. CL < 5pF on all aux-DAC outputs. Typical values are at TA = +25°C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DIGITAL INPUTS (CLK, SCLK, DIN, CS, D0–D9, T/R, SHDN) Input High Threshold VINH Input Low Threshold VINL Input Leakage DIIN Input Capacitance DCIN 0.7 x OVDD V 0.3 x OVDD D0–D9, CLK, SCLK, DIN, CS, T/R, SHDN = OGND or OVDD -1 +1 5 V µA pF DIGITAL OUTPUTS (D0–D9, DOUT) Output-Voltage Low VOL ISINK = 200µA Output-Voltage High VOH ISOURCE = 200µA Tri-State Leakage Current ILEAK Tri-State Output Capacitance COUT 0.2 x OVDD 0.8 x OVDD V V -1 +1 5 µA pF Note 1: Specifications from TA = +25°C to +85°C are guaranteed by production tests. Specifications from TA = +25°C to -40°C are guaranteed by design and characterization. Note 2: The minimum clock frequency (fCLK) for the MAX19707 is 7.5MHz (typical). The minimum aux-ADC sample rate clock frequency (ACLK) is determined by fCLK and the chosen aux-ADC clock-divider value. The minimum aux-ADC ACLK > 7.5MHz / 128 = 58.6kHz. The aux-ADC conversion time does not include the time to clock the serial data out of the SPI™. The maximum conversion time (for no averaging, NAVG = 1) will be, tCONV (max) = (12 x 1 x 128) / 7.5MHz = 205µs. Note 3: SNR, SINAD, SFDR, HD3, and THD are based on a differential analog input voltage of -0.5dBFS referenced to the amplitude of the digital outputs. SINAD and THD are calculated using HD2 through HD6. Note 4: Crosstalk rejection is measured by applying a high-frequency test tone to one channel and a low-frequency tone to the second channel. FFTs are performed on each channel. The parameter is specified as the power ratio of the first and second channel FFT test tone. Note 5: Amplitude and phase matching is measured by applying the same signal to each channel, and comparing the two output signals using a sine-wave fit. Note 6: Guaranteed by design and characterization. SPI is a trademark of Motorola, Inc. _______________________________________________________________________________________ 9 MAX19707 ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 45MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33µF, TA = +25°C, unless otherwise noted.) -40 -50 -60 -70 0 -30 -40 -50 -60 -70 -20 -30 -40 -50 -60 -70 -80 -80 -90 -90 -90 -100 -100 -100 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 FREQUENCY (MHz) FREQUENCY (MHz) Rx ADC CHANNEL-QA TWO-TONE FFT PLOT Rx ADC SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT FREQUENCY Rx ADC SIGNAL-TO-NOISE AND DISTORTION RATIO vs. ANALOG INPUT FREQUENCY -30 -40 -60 55 54 QA 53 52 -70 MAX19707 toc06 55 54 -50 56 SINAD (dB) -20 56 MAX19707 toc05 fCLK = 45.006848MHz f1 = 1.4MHz f2 = 1.8MHz AQA = -7dBFS PER TONE 8192-POINT DATA RECORD SNR (dB) 0 -10 AMPLITUDE (dBFS) -80 FREQUENCY (MHz) MAX19707 toc04 0 fCLK = 45.006848MHz f1 = 1.4MHz f2 = 1.8MHz AIA = -7dBFS PER TONE 8192-POINT DATA RECORD -10 MAX19707 toc03 -20 AMPLITUDE (dBFS) AMPLITUDE (dBFS) -30 fCLK = 45.006848MHz fQA = 13.00155MHz 16,384-POINT DATA RECORD -10 AMPLITUDE (dBFS) fCLK = 45.006848MHz fIA = 13.00155MHz 16,384-POINT DATA RECORD -20 0 MAX19707 toc01 0 -10 Rx ADC CHANNEL-IA TWO-TONE FFT PLOT Rx ADC CHANNEL-QA FFT PLOT MAX19707 toc02 Rx ADC CHANNEL-IA FFT PLOT QA 53 52 IA IA -80 51 51 -90 50 -100 0 50 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 20 40 60 80 100 20 40 60 100 80 ANALOG INPUT FREQUENCY (MHz) Rx ADC TOTAL HARMONIC DISTORTION vs. ANALOG INPUT FREQUENCY Rx ADC SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT FREQUENCY Rx ADC SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT AMPLITUDE 80 -65 -75 SFDR (dBc) -70 IA -80 QA 40 QA 75 fIN = 13.00155MHz 50 SNR (dB) QA 60 MAX19707 toc08 MAX19707 toc07 85 MAX19707 toc09 ANALOG INPUT FREQUENCY (MHz) -60 70 IA 30 20 -85 IA 65 10 -90 -95 60 0 20 40 60 80 ANALOG INPUT FREQUENCY (MHz) 10 0 FREQUENCY (MHz) -55 THD (dBc) MAX19707 10-Bit, 45Msps, Ultra-Low-Power Analog Front-End 100 0 0 20 40 60 80 ANALOG INPUT FREQUENCY (MHz) 100 -21 -18 -15 -12 -9 -6 -3 ANALOG INPUT AMPLITUDE (dBFS) ______________________________________________________________________________________ 0 10-Bit, 45Msps, Ultra-Low-Power Analog Front-End QA -40 50 Rx ADC SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT AMPLITUDE fIN = 12.4980346MHz 75 -45 MAX19707 toc12 fIN = 13.00155MHz MAX19707 toc10 60 Rx ADC TOTAL HARMONIC DISTORTION vs. ANALOG INPUT AMPLITUDE MAX19707 toc11 Rx ADC SIGNAL-TO-NOISE AND DISTORTION RATIO vs. ANALOG INPUT AMPLITUDE fIN = 12.4980346MHz 70 -50 IA 30 65 -55 SFDR (dBc) THD (dBc) SINAD (dB) 40 QA -60 -65 20 QA 60 55 -70 10 0 IA 45 -80 -15 -12 -9 -6 -3 0 -21 -18 -15 -12 -9 -6 -3 -21 0 -15 -12 -9 -6 -3 0 ANALOG INPUT AMPLITUDE (dBFS) Rx ADC SIGNAL-TO-NOISE RATIO vs. SAMPLING RATE Rx ADC SIGNAL-TO-NOISE AND DISTORTION RATIO vs. SAMPLING RATE Rx ADC TOTAL HARMONIC DISTORTION vs. SAMPLING RATE fIN = 12.4980346MHz 57 IA fIN = 12.4980346MHz -55 56 QA 54 -70 -75 -80 QA 53 QA -65 THD (dBc) SINAD (dB) 54 fIN = 12.4980346MHz -60 IA 55 MAX19707 toc15 ANALOG INPUT AMPLITUDE (dBFS) 55 SNR (dB) -18 ANALOG INPUT AMPLITUDE (dBFS) MAX19707 toc14 56 -18 MAX19707 toc13 -21 IA 50 -75 IA -85 53 -90 52 52 15 20 25 30 35 40 10 15 20 25 30 35 40 45 5 10 15 20 25 30 35 40 45 SAMPLING RATE (MHz) SAMPLING RATE (MHz) Rx ADC SPURIOUS-FREE DYNAMIC RANGE vs. SAMPLING RATE Rx ADC SIGNAL-TO-NOISE RATIO vs. CLOCK DUTY CYCLE Rx ADC SIGNAL-TO-NOISE AND DISTORTION RATIO vs. CLOCK DUTY CYCLE fIN = 12.4980346MHz 57 fIN = 12.4980346MHz 57 56 MAX19707 toc18 SAMPLING RATE (MHz) 85 fIN = 12.4980346MHz 56 IA 75 70 QA 55 SINAD (dB) SNR (dB) 80 SFDR (dBc) -95 5 45 MAX19707 toc17 90 10 MAX19707 toc16 5 54 QA 15 20 25 30 35 SAMPLING RATE (MHz) 40 45 IA 53 52 52 60 10 54 IA 53 65 5 QA 55 35 45 55 CLOCK DUTY CYCLE (%) 65 35 45 55 65 CLOCK DUTY CYCLE (%) ______________________________________________________________________________________ 11 MAX19707 Typical Operating Characteristics (continued) (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 45MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33µF, TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 45MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33µF, TA = +25°C, unless otherwise noted.) -60 QA 85 80 -70 -75 -80 IA 75 70 0.4 0.2 0 -0.2 -0.4 QA -0.6 -0.8 -95 60 45 55 65 -1.0 35 45 55 65 -40 -15 10 35 60 CLOCK DUTY CYCLE (%) CLOCK DUTY CYCLE (%) TEMPERATURE (°C) Rx ADC GAIN ERROR vs. TEMPERATURE Tx DAC SPURIOUS-FREE DYNAMIC RANGE vs. SAMPLING RATE Tx DAC SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT FREQUENCY QA fOUT = fCLK / 10 73 72 75 70 1.4 1.0 0.8 IA 0.6 65 71 SFDR (dBc) SFDR (dBc) 1.2 85 MAX19707 toc24 1.8 1.6 74 MAX19707 toc22 2.0 MAX19707 toc23 35 70 69 60 55 68 50 67 0.2 0 66 -15 10 35 60 85 45 5 TEMPERATURE (°C) 10 15 20 25 30 35 40 0 45 Tx DAC SPURIOUS-FREE DYNAMIC RANGE vs. OUTPUT AMPLITUDE MAX19707 toc25 0 70 -20 AMPLITUDE (dBFS) 65 60 55 50 45 fID = 5.498MHz -10 -30 -40 -50 -60 -70 -20 -30 -40 -50 -60 -70 35 -90 -90 30 -100 -100 -10 0 fQD = 5.498MHz -10 -80 -20 8 10 12 14 16 18 20 22 Tx DAC CHANNEL-QD SPECTRAL PLOT 40 OUTPUT AMPLITUDE (dBFS) 6 0 AMPLITUDE (dBFS) fOUT = 2.2MHz 4 OUTPUT FREQUENCY (MHz) Tx DAC CHANNEL-ID SPECTRAL PLOT 80 -30 2 SAMPLING RATE (MHz) MAX19707 toc26 -40 MAX19707 toc27 0.4 75 IA 0.6 65 -90 GAIN ERROR (%FS) 0.8 QA -85 12 1.0 OFFSET ERROR (%FS) IA SFDR (dBc) THD (dBc) fIN = 12.4980346MHz MAX19707 toc21 fIN = 12.4980346MHz -65 90 MAX19707 toc19 -55 Rx ADC OFFSET ERROR vs. TEMPERATURE Rx ADC SPURIOUS-FREE DYNAMIC RANGE vs. CLOCK DUTY CYCLE MAX19707 toc20 Rx ADC TOTAL HARMONIC DISTORTION vs. CLOCK DUTY CYCLE SFDR (dBc) MAX19707 10-Bit, 45Msps, Ultra-Low-Power Analog Front-End -80 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 FREQUENCY (MHz) 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 FREQUENCY (MHz) ______________________________________________________________________________________ 10-Bit, 45Msps, Ultra-Low-Power Analog Front-End Rx ADC INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE 0.8 0.6 IVDD 22 20 18 16 10 15 20 25 30 35 40 -0.2 -0.4 -0.2 -0.6 -0.3 -0.8 -0.4 -1.0 -0.5 0 45 0 128 256 384 512 640 768 896 1024 Tx DAC DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE REFERENCE OUTPUT VOLTAGE vs. TEMPERATURE 0.4 0.3 0.1 0 -0.2 0 -0.1 -0.4 -0.2 -0.6 -0.3 -0.8 -0.4 -1.0 -0.5 128 256 384 512 640 768 896 1024 VREFP - VREFN 0.515 VREFP - VREFN (V) 0.2 DNL (LSB) 0.2 0.520 MAX19707 toc32 MAX19707 toc31 0.5 MAX19707 toc33 Tx DAC INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE 0.4 0.510 0.505 0.500 0 -40 128 256 384 512 640 768 896 1024 -15 10 35 60 DIGITAL INPUT CODE DIGITAL INPUT CODE TEMPERATURE (°C) AUX-DAC OUTPUT VOLTAGE vs. OUTPUT SOURCE CURRENT AUX-DAC OUTPUT VOLTAGE vs. OUTPUT SINK CURRENT AUX-DAC SETTLING TIME 3.0 MAX19707 toc34 3.0 2.5 OUTPUT VOLTAGE (V) 2.5 2.0 1.5 1.0 STEP FROM 1/4FS TO 3/4FS 85 2.0 500mV/div 1.5 1.0 0.5 0.5 0 0.001 128 256 384 512 640 768 896 1024 DIGITAL OUTPUT CODE 0.6 0 0 -0.1 DIGITAL OUTPUT CODE 0.8 INL (LSB) 0.1 0 SAMPLING RATE (MHz) 1.0 OUTPUT VOLTAGE (V) 0.2 0.2 MAX19707 toc35 5 0.3 0.4 MAX19707 toc36 24 INL (LSB) 26 0.4 DNL (LSB) 28 0.5 MAX19707 toc29 Ext4-Rx MODE SUPPLY CURRENT (mA) 1.0 MAX19707 toc28 30 Rx ADC DIFFERENTIAL NONLINEARITY vs. DIGITAL OUTPUT CODE MAX19707 toc30 SUPPLY CURRENT vs. SAMPLING RATE 0.01 0.1 1 10 OUTPUT SOURCE CURRENT (mA) 100 0 0.001 0.01 0.1 1 10 100 500ns/div OUTPUT SINK CURRENT (mA) ______________________________________________________________________________________ 13 MAX19707 Typical Operating Characteristics (continued) (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 45MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33µF, TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 45MHz (50% duty cycle), Rx ADC input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN = CCOM = 0.33µF, TA = +25°C, unless otherwise noted.) AUX-DAC DIFFERENTIAL NONLINEARITY vs. DIGITAL INPUT CODE AUX-DAC INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE 0.6 0.4 0.5 0.2 DNL (LSB) 1.0 0 -0.5 MAX19707 toc38 1.5 INL (LSB) 0.8 MAX19707 toc37 2.0 0 -0.2 -1.0 -0.4 -1.5 -0.6 -0.8 -2.0 0 1024 2048 3072 0 4096 AUX-ADC INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE 3072 4096 0.8 1.0 MAX19707 toc40 1.5 2048 AUX-ADC DIFFERENTIAL NONLINEARITY vs. DIGITAL OUTPUT CODE MAX19707 toc39 2.0 1024 DIGITAL INPUT CODE DIGITAL INPUT CODE 0.4 0.5 DNL (LSB) INL (LSB) MAX19707 10-Bit, 45Msps, Ultra-Low-Power Analog Front-End 0 -0.5 -1.0 0 -0.4 -1.5 -2.0 -0.8 0 128 256 384 512 640 768 896 1024 DIGITAL OUTPUT CODE 0 128 256 384 512 640 768 896 1024 DIGITAL OUTPUT CODE Pin Description PIN NAME 1 REFP 2, 8, 11, 31, 33, 39, 43 VDD Analog Supply Voltage. Supply range from 2.7V to 3.3V. Bypass VDD to GND with a combination of a 2.2µF capacitor in parallel with a 0.1µF capacitor. 3 IAP Channel-IA Positive Analog Input. For single-ended operation, connect signal source to IAP. 4 IAN Channel-IA Negative Analog Input. For single-ended operation, connect IAN to COM. 5, 7, 12, 32, 42 GND Analog Ground. Connect all GND pins to ground plane. 6 CLK Conversion Clock Input. Clock signal for both receive ADCs and transmit DACs. 9 QAN Channel-QA Negative Analog Input. For single-ended operation, connect QAN to COM. 14 FUNCTION Upper Reference Voltage. Bypass with a 0.33µF capacitor to GND as close to REFP as possible. ______________________________________________________________________________________ 10-Bit, 45Msps, Ultra-Low-Power Analog Front-End PIN NAME 10 QAP FUNCTION 13–18, 21–24 D0–D9 Digital I/O. Outputs for receive ADC in Rx mode. Inputs for transmit DAC in Tx mode. D9 is the most significant bit (MSB) and D0 is the least significant bit (LSB). 19 OGND Output-Driver Ground 20 OVDD Output-Driver Power Supply. Supply range from 1.8V to VDD. Bypass OVDD to OGND with a combination of a 2.2µF capacitor in parallel with a 0.1µF capacitor. 25 SHDN Active-Low Shutdown Input. Apply logic-low to place the MAX19707 in shutdown. 26 DOUT Aux-ADC Digital Output 27 T/R Transmit- or Receive-Mode Select Input. T/R logic-low input sets the device in receive mode. A logic-high input sets the device in transmit mode. 28 DIN 3-Wire Serial-Interface Data Input. Data is latched on the rising edge of the SCLK. 29 SCLK 30 CS 34 ADC2 Analog Input for Auxiliary ADC 35 ADC1 Analog Input for Auxiliary ADC 36 DAC3 Analog Output for Auxiliary DAC3 37 DAC2 Analog Output for Auxiliary DAC2 Channel-QA Positive Analog Input. For single-ended operation, connect signal source to QAP. 3-Wire Serial-Interface Clock Input 3-Wire Serial-Interface Chip-Select Input. Logic-low enables the serial interface. 38 DAC1 40, 41 IDN, IDP DAC Channel-ID Differential Voltage Output Analog Output for Auxiliary DAC1 (AFC DAC, VOUT = 1.1V During Power-Up) 44, 45 QDN, QDP DAC Channel-QD Differential Voltage Output 46 REFIN Reference Input. Connect to VDD for internal reference. Bypass to GND with a 0.1µF capacitor. 47 COM Common-Mode Voltage I/O. Bypass COM to GND with a 0.33µF capacitor. 48 REFN Negative Reference I/O. Rx ADC conversion range is ±(VREFP - VREFN). Bypass REFN to GND with a 0.33µF capacitor. — EP Exposed Paddle. Exposed paddle is internally connected to GND. Connect EP to the GND plane. Detailed Description The MAX19707 integrates a dual, 10-bit Rx ADC and a dual, 10-bit Tx DAC while providing ultra-low power and high dynamic performance at a 45Msps conversion rate. The Rx ADC analog input amplifiers are fully differential and accept 1.024VP-P full-scale signals. The Tx DAC analog outputs are fully differential with ±400mV full-scale output, selectable common-mode DC level, and adjustable I/Q offset trim. The MAX19707 integrates three 12-bit auxiliary DAC (aux-DAC) channels and a 10-bit, 333ksps auxiliary ADC (aux-ADC) with 4:1 input multiplexer. The aux-DAC channels feature 1µs settling time for fast automatic gain-control (AGC), variable-gain amplifier (VGA), and automatic frequency-control (AFC) level setting. The aux-ADC features data averaging to reduce processor overhead and a selectable clock-divider to program the conversion rate. The MAX19707 includes a 3-wire serial interface to control operating modes and power management. The serial interface is SPI and MICROWIRE™ compatible. The MAX19707 serial interface selects shutdown, idle, standby, transmit (Tx), and receive (Rx) modes, as well as controls aux-DAC and aux-ADC channels. The Rx ADC and Tx DAC share a common digital I/O to reduce the digital interface to a single, 10-bit parallel multiplexed bus. The 10-bit digital bus operates on a single 1.8V to 3.3V supply. MICROWIRE is a trademark of National Semiconductor Corp. ______________________________________________________________________________________ 15 MAX19707 Pin Description (continued) MAX19707 10-Bit, 45Msps, Ultra-Low-Power Analog Front-End Dual, 10-Bit Rx ADC The ADC uses a seven-stage, fully differential, pipelined architecture that allows for high-speed conversion while minimizing power consumption. Samples taken at the inputs move progressively through the pipeline stages every half clock cycle. Including the delay through the output latch, the total clock-cycle latency is 5 clock cycles for channel IA and 5.5 clock cycles for channel QA. The ADC full-scale analog input range is ±VREF with a VDD / 2 ±0.2V common-mode input range. VREF INTERNAL BIAS is the difference between VREFP and VREFN. See the Reference Configurations section for details. Input Track-and-Hold (T/H) Circuits Figure 1 displays a simplified diagram of the Rx ADC input track-and-hold (T/H) circuitry. Both ADC inputs (IAP, QAP, IAN, and QAN) can be driven either differentially or single-ended. Match the impedance of IAP and IAN, as well as QAP and QAN, and set the input signal common-mode voltage within the Rx ADC range of VDD / 2 (±200mV) for optimum performance. COM S5a S2a C1a S3a S4a IAP OUT C2a S4c S1 OUT IAN S4b C1b C2b S3b S5b S2b INTERNAL BIAS COM INTERNAL BIAS COM HOLD CLK HOLD TRACK TRACK INTERNAL NONOVERLAPPING CLOCK SIGNALS S5a S2a C1a S3a S4a QAP OUT C2a S4c S1 MAX19707 OUT QAN S4b C1b C2b S3b S2b INTERNAL BIAS S5b COM Figure 1. Rx ADC Internal T/H Circuits 16 ______________________________________________________________________________________ 10-Bit, 45Msps, Ultra-Low-Power Analog Front-End DIFFERENTIAL INPUT VOLTAGE DIFFERENTIAL INPUT (LSB) OFFSET BINARY (D0–D9) VREF x 512/512 511 (+Full Scale - 1 LSB) 11 1111 1111 1023 VREF x 511/512 510 (+Full Scale - 2 LSB) 11 1111 1110 1022 VREF x 1/512 +1 10 0000 0001 513 VREF x 0/512 0 (Bipolar Zero) 10 0000 0000 512 -VREF x 1/512 -1 01 1111 1111 511 -VREF x 511/512 -511 (-Full Scale +1 LSB) 00 0000 0001 1 -VREF x 512/512 -512 (-Full Scale) 00 0000 0000 0 1 LSB = 2 x VREF 1024 VREF multiplexed at the D0–D9 outputs. CHI data is updated on the rising edge and CHQ data is updated on the falling edge of the CLK. Including the delay through the output latch, the total clock-cycle latency is 5 clock cycles for CHI and 5.5 clock cycles for CHQ. VREF = VREFP - VREFN VREF VREF 11 1111 1111 11 1111 1110 11 1111 1101 10 0000 0001 10 0000 0000 01 1111 1111 (COM) VREF OFFSET BINARY OUTPUT CODE (LSB) OUTPUT DECIMAL CODE 00 0000 0011 00 0000 0010 00 0000 0001 00 0000 0000 -512 -511 -510 -509 -1 0+ 1 +509 +510 +511 +512 (COM) INPUT VOLTAGE (LSB) Figure 2. Rx ADC Transfer Function Rx ADC System Timing Requirements Figure 3 shows the relationship between the clock, analog inputs, and the resulting output data. Channel I (CHI) and channel Q (CHQ) are sampled on the rising edge of the clock signal (CLK) and the resulting data is Digital Input/Output Data (D0–D9) D0–D9 are the Rx ADC digital logic outputs when the MAX19707 is in receive mode. This bus is shared with the Tx DAC digital logic inputs and operates in halfduplex mode. D0–D9 are the Tx DAC digital logic inputs when the MAX19707 is in transmit mode. The logic level is set by OVDD from 1.8V to VDD. The digital output coding is offset binary (Table 1). Keep the capacitive load on the digital outputs D0–D9 as low as possible (< 15pF) to avoid large digital currents feeding back into the analog portion of the MAX19707 and degrading its dynamic performance. Buffers on the digital outputs isolate the outputs from heavy capacitive loads. Adding 100Ω resistors in series with the digital outputs close to the MAX19707 helps improve Rx ADC and Tx DAC performance. Refer to the MAX19707EVKIT schematic for an example of the digital outputs driving a digital buffer through 100Ω series resistors. During SHDN, IDLE, and STBY states, D0–D9 are internally pulled up to prevent floating digital inputs. To ensure no current flows through D0–D9 I/O, the external bus needs to be either tri-stated or pulled up to OVDD and should not be pulled to ground. ______________________________________________________________________________________ 17 MAX19707 Table 1. Rx ADC Output Codes vs. Input Voltage MAX19707 10-Bit, 45Msps, Ultra-Low-Power Analog Front-End 5.5 CLOCK-CYCLE LATENCY (CHQ) 5 CLOCK-CYCLE LATENCY (CHI) CHI CHQ tCLK tCL tCH CLK tDOQ D0–D9 tDOI D0Q D1I D1Q D2I D2Q D3I D3Q D4I D4Q D5I D5Q D6I D6Q Figure 3. Rx ADC System Timing Diagram Dual, 10-Bit Tx DAC The dual, 10-bit digital-to-analog converter (Tx DAC) operates with clock speeds up to 45MHz. The Tx DAC digital inputs, D0–D9, are multiplexed on a single 10-bit bus. The voltage reference determines the Tx DAC fullscale output voltage. See the Reference Configurations section for details on setting the reference voltage. The Tx DAC outputs at IDN, IDP and QDN, QDP are biased at a 0.7V to 1.05V adjustable DC commonmode bias and designed to drive a differential input stage with ≥ 70kΩ input impedance. This simplifies the analog interface between RF quadrature upconverters and the MAX19707. Many RF upconverters require a 0.7V to 1.05V common-mode bias. The Tx DAC DC common-mode bias eliminates discrete level-setting resistors and code-generated level shifting while preserving the full dynamic range of each Tx DAC. The Tx DAC differential analog outputs cannot be used in single-ended mode because of the internally generated common-mode DC level. Table 2 shows the Tx DAC output voltage vs. input codes. Table 10 shows the selection of DC common-mode levels. See Figure 4 for an illustration of the Tx DAC analog output levels. Table 2. Tx DAC Output Voltage vs. Input Codes (Internal Reference Mode VREFDAC = 1.024V, External Reference Mode VREFDAC = VREFIN; VFS = ±400 for 800mVP-P Full Scale) DIFFERENTIAL OUTPUT VOLTAGE (V) OFFSET BINARY (D0–D9) INPUT DECIMAL CODE 1023 × (VFS ) VREFDAC 1024 1023 11 1111 1111 1023 (VFS ) VREFDAC 1024 × 1021 1023 11 1111 1110 1022 (VFS ) VREFDAC 1024 × 3 1023 10 0000 0001 513 (VFS ) VREFDAC 1024 × 1 1023 10 0000 0000 512 01 1111 1111 511 00 0000 0001 1 00 0000 0000 0 (VFS ) −VREFDAC 1024 × (VFS ) −VREFDAC 1024 × 1 1023 1021 1023 1023 × (VFS ) −VREFDAC 1024 1023 18 ______________________________________________________________________________________ 10-Bit, 45Msps, Ultra-Low-Power Analog Front-End used to optimize sideband and carrier suppression in the Tx signal path (see Table 9). MAX19707 EXAMPLE: Tx DAC I-CH Tx RFIC INPUT REQUIREMENTS • DC COMMON-MODE BIAS = 0.9V (MIN), 1.3V (MAX) 0 90 Tx DAC Q-CH • BASEBAND INPUT = ±400mV DC-COUPLED FULL SCALE = 1.25V VCOM = 1.05V COMMON-MODE LEVEL SELECT CM1 = 0, CM0 = 0 VCOM = 1.05V VDIFF = ±400mV ZERO SCALE = 0.85V 0V Figure 4. Tx DAC Common-Mode DC Level at IDN, IDP or QDN, QDP Differential Outputs ______________________________________________________________________________________ 19 MAX19707 The Tx DAC also features independent DC offset correction of each I/Q channel. This feature is configured through the SPI interface. The DC offset correction is MAX19707 10-Bit, 45Msps, Ultra-Low-Power Analog Front-End Tx DAC Timing Figure 5 shows the relationship between the clock, input data, and analog outputs. Data for the I channel (ID) is latched on the falling edge of the clock signal, and Qchannel (QD) data is latched on the rising edge of the clock signal. Both I and Q outputs are simultaneously updated on the next rising edge of the clock signal. composed of A3–A0 control bits and D11–D0 data bits. Data is shifted in MSB first (D11) and LSB last (A0). Tables 4, 5, and 6 show the MAX19707 operating modes and SPI commands. The serial interface remains active in all modes. SPI Register Description Program the control bits, A3–A0, in the register as shown in Table 3 to select the operating mode. Modify A3–A0 bits to select from ENABLE-16, Aux-DAC1, Aux-DAC2, Aux-DAC3, IOFFSET, QOFFSET, Aux-ADC, ENABLE-8, and COMSEL modes. ENABLE-16 is the default operating mode. This mode allows for shutdown, idle, and standby states as well as switching between FAST, SLOW, Rx, and Tx modes. Table 4 shows the MAX19707 power-management modes. Table 5 shows the T/R pincontrolled external Tx-Rx switching modes. Table 6 shows the SPI-controlled Tx-Rx switching modes. 3-Wire Serial Interface and Operation Modes The 3-wire serial interface controls the MAX19707 operation modes as well as the three 12-bit aux-DACs and the 10-bit aux-ADC. Upon power-up, program the MAX19707 to operate in the desired mode. Use the 3wire serial interface to program the device for shutdown, idle, standby, Rx, Tx, aux-DAC controls, or aux-ADC conversion. A 16-bit data register sets the mode control as shown in Table 3. The 16-bit word is CLK tDHQ tDSQ D0–D9 Q: N - 2 I: N - 1 Q: N - 1 tDSI Q: N I: N I: N + 1 tDHI ID N-2 N-1 N QD N-2 N-1 N Figure 5. Tx DAC System Timing Diagram 20 ______________________________________________________________________________________ 10-Bit, 45Msps, Ultra-Low-Power Analog Front-End D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A3 A2 A1 A0 (MSB) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 (LSB) ENABLE-16 E11 = 0 Reserved E10 = 0 Reserved E9 — — E6 E5 E4 E3 E2 E1 E0 0 0 0 0 Aux-DAC1 1D11 1D10 1D9 1D8 1D7 1D6 1D5 1D4 1D3 1D2 1D1 1D0 0 0 0 1 Aux-DAC2 2D11 2D10 2D9 2D8 2D7 2D6 2D5 2D4 2D3 2D2 2D1 2D0 0 0 1 0 Aux-DAC3 3D11 3D10 3D9 3D8 3D7 3D6 3D5 3D4 3D3 3D2 3D1 3D0 0 0 1 1 IOFFSET — — — — — — IO5 IO4 IO3 IO2 IO1 IO0 0 1 0 0 QOFFSET — — — — — — QO5 QO4 QO3 QO2 QO1 QO0 0 1 0 1 COMSEL — — — — — — — — — — CM1 CM0 0 1 1 0 Aux-ADC AD11 = 0 Reserved AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 0 1 1 1 ENABLE-8 — — — — — — — — E3 E2 E1 E0 1 0 0 0 REGISTER NAME — = Not used. Table 4. Power-Management Modes ADDRESS DATA BITS T/R MODE A3 A2 A1 A0 E9* 0000 (16-Bit Mode) or 1000 (8-Bit Mode) E3 E2 E1 E0 PIN 27 FUNCTION (POWER MANAGEMENT) 1X000 X SHDN SHUTDOWN XX001 X IDLE IDLE 1X010 X STBY STANDBY DESCRIPTION Rx ADC = OFF Tx DAC = OFF Aux-DAC = OFF Aux-ADC = OFF CLK = OFF REF = OFF Rx ADC = OFF Tx DAC = OFF Aux-DAC = Last State CLK = ON REF = ON Rx ADC = OFF Tx DAC = OFF Aux-DAC = Last State Aux-ADC = OFF CLK = OFF REF = ON COMMENT Device is in complete shutdown. Overrides T/R pin. Fast turn-on time. Moderate idle power. Overrides T/R pin. Slow turn-on time. Low standby power. Overrides T/R pin. X = Don't care. *Bit E9 is not available in 8-bit mode. ______________________________________________________________________________________ 21 MAX19707 Table 3. MAX19707 Mode Control MAX19707 10-Bit, 45Msps, Ultra-Low-Power Analog Front-End Table 5. External Tx-Rx Control Using T/R Pin (T/R = 0 = Rx Mode, T/R = 1 = Tx Mode) ADDRESS DATA BITS A3 A2 A1 A0 E3 E2 E1 E0 T/R STATE PIN 27 0 Ext1-Rx 0011 COMMENT Rx Mode: Rx ADC = ON Tx DAC = ON Rx Bus = Enable Moderate Power: Fast Rx to Tx when T/R transitions 0 to 1. Low Power: Slow Tx to Rx when T/R transitions 1 to 0. 1 Ext1-Tx Tx Mode: Rx ADC = OFF Tx DAC = ON Tx Bus = Enable 0 Ext2-Rx (Default) Rx Mode: Rx ADC = ON Tx DAC = OFF Rx Bus = Enable Low Power: Slow Rx to Tx when T/R transitions 0 to 1. Ext2-Tx Tx Mode: Rx ADC = ON Tx DAC = ON Tx Bus = Enable Moderate Power: Fast Tx to Rx when T/R transitions 1 to 0. Ext3-Rx Rx Mode: Rx ADC = ON Tx DAC = OFF Rx Bus = Enable Low Power: Slow Rx to Tx when T/R transitions 0 to 1. Ext3-Tx Tx Mode: Rx ADC = OFF Tx DAC = ON Tx Bus = Enable Low Power: Slow Tx to Rx when T/R transitions 1 to 0. Ext4-Rx Rx Mode: Rx ADC = ON Tx DAC = ON Rx Bus = Enable Moderate Power: Fast Rx to Tx when T/R transitions 0 to 1. Tx Mode: Rx ADC = ON Tx DAC = ON Tx Bus = Enable Moderate Power: Fast Tx to Rx when T/R transitions 1 to 0. SLOW-FAST 1 0 0101 SLOW-SLOW 1 0 0110 FAST-FAST 1 22 DESCRIPTION FAST-SLOW 0100 0000 (16-Bit Mode) or 1000 (8-Bit Mode) FUNCTION Rx TO Tx-Tx TO Rx SWITCHING SPEED Ext4-Tx ______________________________________________________________________________________ 10-Bit, 45Msps, Ultra-Low-Power Analog Front-End MAX19707 Table 6. Tx-Rx Control Using SPI Commands ADDRESS DATA BITS A3 A2 A1 A0 E3 E2 E1 E0 1011 0000 (16-Bit Mode) or 1000 (8-Bit Mode) 1100 1101 1110 T/R MODE PIN 27 X X X X FUNCTION (Tx-Rx SWITCHING SPEED) SPI1-Rx SPI2-Tx SPI3-Rx SPI4-Tx DESCRIPTION COMMENTS SLOW Rx Mode: Rx ADC = ON Tx DAC = OFF Rx Bus = Enable Low Power: Slow Rx to Tx through SPI command. SLOW Tx Mode: Rx ADC = OFF Tx DAC = ON Tx Bus = Enable Low Power: Slow Tx to Rx through SPI command. FAST Rx Mode: Rx ADC = ON Tx DAC = ON Rx Bus = Enabled Moderate Power: Fast Rx to Tx through SPI command. FAST Tx Mode: Rx ADC = ON Tx DAC = ON Tx Bus = Enabled Moderate Power: Fast Tx to Rx through SPI command. X = Don’t care. In ENABLE-16 mode, the aux-DACs have independent control bits E4, E5, and E6, and bit E9 enables the auxADC. Table 7 shows the auxiliary DAC enable codes and Table 8 shows the auxiliary ADC enable codes. Bits E11 and E10 are reserved. Program bits E11 and E10 to logic-low. Modes aux-DAC1, aux-DAC2, and aux-DAC3 select the aux-DAC channels named DAC1, DAC2, and DAC3 and hold the data inputs for each DAC. Bits _D11–_D0 are the data inputs for each aux-DAC and can be programmed through SPI. The MAX19707 also includes two 6-bit registers that can be programmed to adjust the offsets for the Tx DAC I and Q channels independently (see Table 9). Use the COMSEL mode to select the output common-mode voltage with bits CM1 and CM0 (see Table 10). Use Aux-ADC mode to start the auxiliary ADC conversion (see the 10-Bit, 333ksps Auxiliary ADC section for details). Use ENABLE-8 mode for faster enable and switching between shutdown, idle, and standby states as well as switching between FAST, SLOW, and Rx and Tx modes. Table 7. Aux-DAC Enable Table (ENABLE-16 Mode) E6 E5 E4 AUX-DAC3 AUX-DAC2 AUX-DAC1 0 0 0 ON ON ON 0 0 1 ON ON OFF 0 1 0 ON OFF ON 0 1 1 ON OFF OFF 1 0 0 OFF ON ON 1 0 1 OFF ON OFF 1 1 0 OFF OFF ON 1 1 1 OFF OFF OFF Table 8. Aux-ADC Enable Table (ENABLE-16 Mode) E9 SELECTION 0 (Default) Aux-ADC is Powered ON 1 Aux-ADC is Powered OFF ______________________________________________________________________________________ 23 MAX19707 10-Bit, 45Msps, Ultra-Low-Power Analog Front-End Table 9. Offset Control Bits for I and Q Channels (IOFFSET or QOFFSET Mode) BITS IO5–IO0 WHEN IN IOFFSET MODE, BITS QO5–QO0 WHEN IN QOFFSET MODE IO5/QO5 IO4/QO4 IO3/QO3 IO2/QO2 IO1/QO1 IO0/QO0 OFFSET 1 LSB = (VFSP-P / 1023) 1 1 1 1 1 1 -31 LSB 1 1 1 1 1 0 -30 LSB 1 1 1 1 0 1 -29 LSB • • • • • • • • • • • • • • • • • • • • • 1 0 0 0 1 0 -2 LSB 1 0 0 0 0 1 -1 LSB 1 0 0 0 0 0 0mV 0 0 0 0 0 0 0mV (Default) 0 0 0 0 0 1 1 LSB 0 0 0 0 1 0 2 LSB • • • • • • • • • • • • • • • • • • • • • 0 1 1 1 0 1 29 LSB 0 1 1 1 1 0 30 LSB 0 1 1 1 1 1 31 LSB Note: For transmit full-scale of ±400mV: 1 LSB = (800mVP-P / 1023) = 0.7820mV. Table 10. Common-Mode Select (COMSEL Mode) CM1 CM0 Tx DAC OUTPUT COMMON MODE (V) 0 0 1.05 (Default) 0 1 0.95 1 0 0.80 1 1 0.70 Shutdown mode offers the most dramatic power savings by shutting down all the analog sections of the MAX19707 and placing the Rx ADC digital outputs in tri-state mode. When the Rx ADC outputs transition from tri-state to ON, the last converted word is placed on the digital outputs. The Tx DAC previously stored data is lost when coming out of shutdown mode. The wake-up time from shutdown mode is dominated by the time required to charge the capacitors at REFP, REFN, and COM. In internal reference mode and buffered external reference mode, the wake-up time is typically 85.2µs to enter Rx mode and 28.2µs to enter Tx mode. In idle mode, the reference and clock distribution circuits are powered, but all other functions are off. The 24 Rx ADC outputs are forced to tri-state. The wake-up time is 9.8µs to enter Rx mode and 6.4µs to enter Tx mode. When the Rx ADC outputs transition from tristate to ON, the last converted word is placed on the digital outputs. In standby mode, the reference is powered, but the rest of the device functions are off. The wake-up time from standby mode is 13.7µs to enter Rx mode and 24µs to enter Tx mode. When the Rx ADC outputs transition from tri-state to active, the last converted word is placed on the digital outputs. FAST and SLOW Rx and Tx Modes In addition to the external Tx-Rx control, the MAX19707 also features SLOW and FAST modes for switching between Rx and Tx operation. In FAST Tx mode, the Rx ADC core is powered on but the ADC core digital outputs are tri-stated on the D0–D9 bus; likewise, in FAST Rx mode, the transmit DAC core is powered on but the DAC core digital inputs are tri-stated on the D0–D9 bus. The switching time between Tx to Rx or Rx to Tx is FAST because the converters are on and do not have to recover from a power-down state. In FAST mode, the switching time between Rx to Tx and Tx to Rx is 0.5µs. ______________________________________________________________________________________ 10-Bit, 45Msps, Ultra-Low-Power Analog Front-End mode, use the T/R input (pin 27) to switch between Rx and Tx modes. Using the T/R pin provides faster switching between Rx and Tx modes. To override the external Tx-Rx control, program the MAX19707 through the serial interface. During SHDN, IDLE, or STBY modes, the T/R input is overridden. To restore external Tx-Rx control, program bit E3 low and exit the SHDN, IDLE, or STBY modes through the serial interface. SPI Timing The serial digital interface is a standard 3-wire connection compatible with SPI/QSPI™/MICROWIRE/DSP interfaces. Set CS low to enable the serial data loading at DIN or output at DOUT. Following a CS high-to-low transition, data is shifted synchronously, most significant bit first, on the rising edge of the serial clock (SCLK). After 16 bits are loaded into the serial input register, data is transferred to the latch when CS transitions high. CS must transition high for a minimum of 80ns before the next write sequence. The SCLK can idle either high or low between transitions. Figure 6 shows the detailed timing diagram of the 3-wire serial interface. R Switching Control vs. External T/R Serial-Interface Control Bit E3 in the ENABLE-16 or ENABLE-8 register determines whether the device Tx-Rx mode is controlled externally through the T/R input (E3 = low) or through the SPI command (E3 = high). By default, the MAX19707 is in the external Tx-Rx control mode. In the external control QSPI is a trademark of Motorola, Inc. 16-BIT OR 8-BIT WRITE INTO SPI (DIN) tCSS tCP 16-BIT OR 8-BIT WRITE INTO SPI DURING AUX-ADC CONVERSION 10-BIT READ OUT OF AUX-ADC (DOUT) WITH SIMULTANEOUS 16-BIT WRITE INTO SPI (DIN) tCS CS tCSW tCONV tCL tCH tCHZ tDCS tCSD tDS SCLK tCD tDH DIN DOUT MSB D11 (16-BIT) D3 (8-BIT) D10 (16-BIT) D2 (8-BIT) DOUT = TRI-STATED WHEN AUX-ADC IS IDLE LSB A0 DOUT = ACTIVE WHEN BIT AD0 IS SET MSB LSB MSB BIT D11 (DIN) AUX-ADC IS BUSY AUX-ADC DATA READY BIT D10 (DIN) MSB BIT D9 (DOUT) BIT D1 (DIN) LSB BIT D0 (DOUT) LSB BIT A0 (DIN) LSB BIT D0 (HELD) DOUT TRISTATED BIT AD0 CLEARED Figure 6. Serial-Interface Timing Diagram ______________________________________________________________________________________ 25 MAX19707 However, power consumption is higher in this mode because both the Tx and Rx cores are always on. To prevent bus contention in these states, the Rx ADC output buffers are tri-stated during Tx and the Tx DAC input bus is tri-stated during Rx. In SLOW mode, the Rx ADC core is off during Tx; likewise the Tx DAC and filters are turned off during Rx to yield lower power consumption in these modes. For example, the power in SLOW Tx mode is 49.5mW. The power consumption during Rx is 77.1mW compared to 84.6mW power consumption in FAST mode. However, the recovery time between states is increased. The switching time in SLOW mode between Rx to Tx is 7µs and Tx to Rx is 4.1µs. MAX19707 10-Bit, 45Msps, Ultra-Low-Power Analog Front-End Mode-Recovery Timing Figure 7 shows the mode-recovery timing diagram. tWAKE is the wakeup time when exiting shutdown, idle, or standby mode and entering Rx or Tx mode. tENABLE is the recovery time when switching between either Rx or Tx mode. tWAKE or tENABLE is the time for the Rx ADC to settle within 1dB of specified SINAD performance and Tx DAC settling to 10 LSB error. tWAKE and tENABLE times are measured after either the 16-bit serial command is latched into the MAX19707 by a CS transition high (SPI controlled) or a T/R logic transition (external Tx-Rx control). In FAST mode, the recovery time is 0.5µs to switch between Tx or Rx modes. System Clock Input (CLK) Both the Rx ADC and Tx DAC share the CLK input. The CLK input accepts a CMOS-compatible signal level set by OVDD from 1.8V to VDD. Since the interstage conversion of the device depends on the repeatability of the rising and falling edges of the external clock, use a clock with low jitter and fast rise and fall times (< 2ns). Specifically, sampling occurs on the rising edge of the clock signal, requiring this edge to provide the lowest possible jitter. Any significant clock jitter limits the SNR performance of the on-chip Rx ADC as follows: ⎛ ⎞ 1 SNR = 20 × log ⎜ ⎟ 2 × π × f × t ⎝ IN AJ ⎠ where fIN represents the analog input frequency and tAJ is the time of the clock jitter. Clock jitter is especially critical for undersampling applications. Consider the clock input as an analog input and route away from any analog input or other digital signal lines. The MAX19707 clock input operates with an OVDD / 2 voltage threshold and accepts a 50% ±15% duty cycle. CS SCLK DIN D0–D9 16-BIT SERIAL DATA INPUT ADC DIGITAL OUTPUT SINAD SETTLES WITHIN 1dB tWAKE, SD, ST_ TO Rx MODE OR tENABLE, RX ID/QD DAC ANALOG OUTPUT OUTPUT SETTLES TO 10 LSB ERROR tWAKE, SD, ST_ TO Tx MODE OR tENABLE, TX tENABLE, TX EXTERNAL T/R CONTROL T/R Rx - > Tx tENABLE, RX EXTERNAL T/R CONTROL T/R Tx - > Rx Figure 7. Mode-Recovery Timing Diagram 26 ______________________________________________________________________________________ 10-Bit, 45Msps, Ultra-Low-Power Analog Front-End Loading on the aux-DAC outputs should be carefully observed to achieve specified settling time and stability. The capacitive load must be kept to a maximum of 5pF including package and trace capacitance. The resistive load must be greater than 200kΩ. If capacitive loading exceeds 5pF, then add a 10kΩ resistor in series with the output. Adding the series resistor helps drive larger load capacitance (< 15pF) at the expense of slower settling time. 10-Bit, 333ksps Auxiliary ADC The MAX19707 integrates a 10-bit, 333ksps aux-ADC with an input 4:1 multiplexer. In the aux-ADC mode register, setting bit AD0 begins a conversion with the auxiliary ADC. Bit AD0 automatically clears when the conversion is complete. Setting or clearing AD0 during a conversion has no effect (see Table 11). Bit AD1 Table 11. Auxiliary ADC Convert determines the internal reference of the auxiliary ADC (see Table 12). Bits AD2 and AD3 determine the auxiliary ADC input source (see Table 13). Bits AD4, AD5, and AD6 select the number of averages taken when a single start-convert command is given. The conversion time increases as the number of averages increases (see Table 14). The conversion clock can be divided down from the system clock by properly setting bits AD7, AD8, and AD9 (see Table 15). The aux-ADC output data can be written out of DOUT by setting bit AD10 high (see Table 16). The aux-ADC features a 4:1 input multiplexer to allow measurements on four input sources. The input sources are selected by AD3 and AD2 (see Table 13). Two of the multiplexer inputs (ADC1 and ADC2) can be connected to external sources such as an RF power detector like the MAX2208 or temperature sensor like the MAX6613. The other two multiplexer inputs are internal connections to VDD and OVDD that monitor the powersupply voltages. The internal VDD and OVDD connections are made through integrated resistor-dividers that yield VDD / 2 and OVDD / 2 measurement results. The aux-ADC voltage reference can be selected between an internal 2.048V bandgap reference or V DD (see Table 12). The VDD reference selection is provided to allow measurement of an external voltage source with a full-scale range extending beyond the 2.048V level. The input source voltage range cannot extend above VDD. Table 13. Auxiliary ADC Input Source AD0 SELECTION AD3 AD2 AUX-ADC INPUT SOURCE 0 Aux-ADC Idle (Default) 0 0 ADC1 (Default) 1 Aux-ADC Start-Convert 0 1 ADC2 1 0 VDD / 2 1 1 OVDD / 2 Table 12. Auxiliary ADC Reference AD1 SELECTION 0 Internal 2.048V Reference (Default) 1 Internal VDD Reference ______________________________________________________________________________________ 27 MAX19707 12-Bit Auxiliary Control DACs The MAX19707 includes three 12-bit aux-DACs (DAC1, DAC2, DAC3) with 1µs settling time for controlling VGA, AGC, and AFC functions. The aux-DAC output range is 0.1V to 2.56V. During power-up, the VGA and AGC outputs (DAC2 and DAC3) are at zero. The AFC DAC (DAC1) is at 1.1V during power-up. The aux-DACs can be independently controlled through the SPI bus, except during SHDN mode where the aux-DACs are turned off completely and the output voltage is set to zero. In STBY and IDLE modes, the aux-DACs maintain the last value. On wakeup from SHDN, the aux-DACs resume the last values. MAX19707 10-Bit, 45Msps, Ultra-Low-Power Analog Front-End The conversion requires 12 clock edges (1 for input sampling, 1 for each of the 10 bits, and 1 at the end for loading into the serial output register) to complete one conversion cycle (when no averaging is being done). Each conversion of an average (when averaging is set greater than 1) requires 12 clock edges. The conversion clock is generated from the system clock input (CLK). An SPI-programmable divider divides the system clock by the appropriate divisor (set with bits AD7, AD8, and AD9; see Table 15) and provides the conversion clock to the auxiliary ADC. The auxiliary ADC has a maximum conversion rate of 333ksps. The maximum conversion clock frequency is 4MHz (333ksps x 12 clocks). Choose the proper divider value to keep the conversion clock frequency under 4MHz, based upon the system CLK frequency supplied to the MAX19707 (see Table 15). The total conversion time (tCONV) of the auxiliary ADC can be calculated as t CONV = (12 x N AVG x N DIV) / f CLK; where N AVG is the number of averages (see Table 14), NDIV is the CLK divisor (see Table 15), and fCLK is the system CLK frequency. DOUT is normally in a tri-state condition. Upon setting the auxiliary ADC start conversion bit (bit AD0), DOUT becomes active and goes high, indicating that the auxADC is busy. When the conversion cycle is complete (including averaging), the data is placed into an output register and DOUT goes low, indicating that the output data is ready to be driven onto DOUT. When bit AD10 is set (AD10 = 1), the aux-ADC enters a data output mode where data is available on DOUT upon the next assertion low of CS. The auxiliary ADC data is shifted out of DOUT (MSB first) with the data transitioning on the falling edge of the serial clock (SCLK). DOUT enters tristate condition when CS is deasserted high. When bit AD10 is cleared (AD10 = 0), the aux-ADC data is not available on DOUT (see Table 16). DIN can be written independent of DOUT state. A 16bit instruction at DIN updates the device configuration. To prevent modifying internal registers while reading data from DOUT, hold DIN at a high state. This effectively writes all ones into address 1111. Since address 1111 does not exist, no internal registers are affected. 28 Table 14. Auxiliary ADC Averaging AD6 AD5 AD4 AUX-ADC AVERAGING 0 0 0 1 Conversion (No Averaging) (Default) 0 0 1 Average of 2 Conversions 0 1 0 Average of 4 Conversions 0 1 1 Average of 8 Conversions 1 0 0 Average of 16 Conversions 1 0 1 Average of 32 Conversions 1 1 X Average of 32 Conversions X = Don’t care. Table 15. Auxiliary ADC Clock (CLK) Divider AD9 AD8 AD7 AUX-ADC CONVERSION CLOCK 0 0 0 CLK Divided by 1 (Default) 0 0 1 CLK Divided by 2 0 1 0 CLK Divided by 4 0 1 1 CLK Divided by 8 1 0 0 CLK Divided by 16 1 0 1 CLK Divided by 32 1 1 0 CLK Divided by 64 1 1 1 CLK Divided by 128 Table 16. Auxiliary ADC Data Output Mode AD10 SELECTION 0 Aux-ADC Data is Not Available on DOUT (Default) 1 Aux-ADC Enters Data Output Mode Where Data is Available on DOUT ______________________________________________________________________________________ 10-Bit, 45Msps, Ultra-Low-Power Analog Front-End MAX19707 Table 17. Reference Modes VREFIN REFERENCE MODE > 0.8V x VDD Internal Reference Mode. VREF is internally generated to be 0.512V. Bypass REFP, REFN, and COM each with a 0.33µF capacitor. 1.024V ±10% Buffered External Reference Mode. An external 1.024V ±10% reference voltage is applied to REFIN. VREF is internally generated to be VREFIN / 2. Bypass REFP, REFN, and COM each with a 0.33µF capacitor. Bypass REFIN to GND with a 0.1µF capacitor. Reference Configurations The MAX19707 features an internal precision 1.024V bandgap reference that is stable over the entire powersupply and temperature ranges. The REFIN input provides two modes of reference operation. The voltage at REFIN (V REFIN ) sets the reference operation mode (Table 17). In internal reference mode, connect REFIN to V DD. V REF is an internally generated 0.512V ±4%. COM, REFP, and REFN are low-impedance outputs with V COM = V DD / 2, V REFP = V DD / 2 + V REF / 2, and VREFN = VDD / 2 - VREF / 2. Bypass REFP, REFN, and COM each with a 0.33µF capacitor. Bypass REFIN to GND with a 0.1µF capacitor. In buffered external reference mode, apply 1.024V ±10% at REFIN. In this mode, COM, REFP, and REFN are low-impedance outputs with V COM = V DD / 2, VREFP = VDD / 2 + VREFIN / 4, and VREFN = VDD / 2 VREFIN / 4. Bypass REFP, REFN, and COM each with a 0.33µF capacitor. Bypass REFIN to GND with a 0.1µF capacitor. In this mode, the Tx DAC full-scale output is proportional to the external reference. For example, if the VREFIN is increased by 10% (max), the Tx DAC fullscale output is also increased by 10% or ±440mV. 25Ω IAP 0.1µF 22pF VIN COM 0.33µF 0.1µF IAN 25Ω 22pF MAX19707 25Ω QAP 0.1µF 22pF VIN 0.33µF 0.1µF QAN 25Ω 22pF Applications Information Using Balun Transformer AC-Coupling An RF transformer (Figure 8) provides an excellent solution to convert a single-ended signal source to a fully differential signal for optimum ADC performance. Connecting the center tap of the transformer to COM provides a VDD / 2 DC level shift to the input. A 1:1 transformer can be used, or a step-up transformer can be selected to reduce the drive requirements. In general, the MAX19707 provides better SFDR and THD with fully differential input signals than single-ended signals, Figure 8. Balun Transformer-Coupled Single-Ended-toDifferential Input Drive for Rx ADC especially for high input frequencies. In differential mode, even-order harmonics are lower as both inputs (IAP, IAN, QAP, QAN) are balanced, and each of the Rx ADC inputs only requires half the signal swing compared to single-ended mode. Figure 9 shows an RF transformer converting the MAX19707 Tx DAC differential analog outputs to single-ended. ______________________________________________________________________________________ 29 MAX19707 10-Bit, 45Msps, Ultra-Low-Power Analog Front-End Using Op-Amp Coupling IDP VOUT MAX19707 IDN QDP VOUT QDN Figure 9. Balun Transformer-Coupled Differential-to-SingleEnded Output Drive for Tx DAC Drive the MAX19707 Rx ADC with op amps when a balun transformer is not available. Figures 10 and 11 show the Rx ADC being driven by op amps for AC-coupled single-ended and DC-coupled differential applications. Amplifiers such as the MAX4454 and MAX4354 provide high speed, high bandwidth, low noise, and low distortion to maintain the input signal integrity. The op-amp circuit shown in Figure 11 can also be used to interface with the Tx DAC differential analog outputs to provide gain or buffering. The Tx DAC differential analog outputs cannot be used in single-ended mode because of the internally generated common-mode level. Also, the Tx DAC analog outputs are designed to drive a differential input stage with input impedance ≥ 70kΩ. If single-ended outputs are desired, use an amplifier to provide differential-to-single-ended conversion and select an amplifier with proper input commonmode voltage range. TDD Mode REFP 1kΩ VIN 0.1µF RISO 50Ω IAP 100Ω CIN 22pF 1kΩ COM REFN 0.1µF RISO 50Ω IAN 100Ω CIN 22pF TDD Application CIN 22pF Figure 12 illustrates a typical TDD application circuit. The MAX19707 interfaces directly with the radio frontends to provide a complete “RF-to-Bits” solution for TDD applications such as 802.11, 802.16, DSRC, and proprietary radio systems. The MAX19707 provides several system benefits to digital baseband developers. • Fast Time-to-Market REFP VIN 0.1µF 1kΩ MAX19707 RISO 50Ω QAP 100Ω 1kΩ REFN 0.1µF RISO 50Ω 100Ω The MAX19707 is optimized to operate in TDD applications. When FAST mode is selected, the MAX19707 can switch between Tx and Rx modes through the T/R pin in typically 0.5µs. The Rx ADC and Tx DAC operate independently. The Rx ADC and Tx DAC digital bus are shared forming a single 10-bit parallel bus. Using the 3wire serial interface or external T/R pin, select between Rx mode to enable the Rx ADC or Tx mode to enable the Tx DAC. When operating in Rx mode, the Tx DAC bus is not enabled and in Tx mode the Rx ADC bus is tri-stated, eliminating any unwanted spurious emissions and preventing bus contention. In TDD mode, the MAX19707 uses 84.6mW power at fCLK = 45MHz. QAN CIN 22pF • High-Performance, Low-Power Analog Functions • Low Risk, Proven Analog Front-End Solution • No Mixed-Signal Test Times • No NRE Charges • No IP Royalty Charges • Enables Digital Baseband to Scale with 65nm to 90nm CMOS Figure 10. Single-Ended Drive for Rx ADC 30 ______________________________________________________________________________________ 10-Bit, 45Msps, Ultra-Low-Power Analog Front-End MAX19707 R5 600Ω R4 600Ω RISO 22Ω R1 600Ω IAN CIN 5pF MAX19707 R2 600Ω R3 600Ω R6 600Ω R7 600Ω R8 600Ω R9 600Ω COM RISO 22Ω CIN 5pF IAP R11 600Ω R10 600Ω Figure 11. Rx ADC DC-Coupled Differential Drive 10-BIT ADC Rx-I 802.11X Rx ENCODE T/R Rx-Q ZIF TRANSCEIVER HALFDUPLEX BUS 10-BIT DAC D9 D0 Tx-I AGC CLK Tx SOURCE Tx-Q 12-BIT DAC DIGITAL BASEBAND ASIC SYSTEM CONTROL CLK DIST SPI REG DAC3 DAC2 TCXO DAC1 MAX19707 VDD 0VDD REF 1.024V BUFFER SCLK DIN CS SHDN REFIN REFP REFN COM BATTERY VOLTAGE MONITOR ADC TEMPERATURE MEASURE 4:1 MUX DOUT 10-BIT, 333ksps Figure 12. Typical Application Circuit for 802.11 Radio ______________________________________________________________________________________ 31 Grounding, Bypassing, and Board Layout The MAX19707 requires high-speed board layout design techniques. Refer to the MAX19707 EV kit data sheet for a board layout reference. Place all bypass capacitors as close to the device as possible, preferably on the same side of the board as the device, using surface-mount devices for minimum inductance. Bypass VDD to GND with a 0.1µF ceramic capacitor in parallel with a 2.2µF capacitor. Bypass OVDD to OGND with a 0.1µF ceramic capacitor in parallel with a 2.2µF capacitor. Bypass REFP, REFN, and COM each to GND with a 0.33µF ceramic capacitor. Bypass REFIN to GND with a 0.1µF capacitor. Multilayer boards with separated ground and power planes yield the highest level of signal integrity. Use a split ground plane arranged to match the physical location of the analog ground (GND) and the digital outputdriver ground (OGND) on the device package. Connect the MAX19707 exposed backside paddle to GND plane. Join the two ground planes at a single point so the noisy digital ground currents do not interfere with the analog ground plane. The ideal location for this connection can be determined experimentally at a point along the gap between the two ground planes. Make this connection with a low-value, surfacemount resistor (1Ω to 5Ω), a ferrite bead, or a direct short. Alternatively, all ground pins could share the same ground plane, if the ground plane is sufficiently isolated from any noisy digital system’s ground plane (e.g., downstream output buffer or DSP ground plane). Route high-speed digital signal traces away from sensitive analog traces. Make sure to isolate the analog input lines to each respective converter to minimize channel-to-channel crosstalk. Keep all signal lines short and free of 90° turns. Dynamic Parameter Definitions ADC and DAC Static Parameter Definitions Integral Nonlinearity (INL) Integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best-straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. The static linearity parameters for the device are measured using the best-straight-line fit (DAC Figure 13a). Differential Nonlinearity (DNL) Differential nonlinearity is the difference between an actual step width and the ideal value of 1 LSB. A DNL error specification of less than 1 LSB guarantees no missing codes (ADC) and a monotonic transfer function (ADC and DAC) (DAC Figure 13b). ADC Offset Error Ideally, the midscale transition occurs at 0.5 LSB above midscale. The offset error is the amount of deviation between the measured transition point and the ideal transition point. DAC Offset Error Offset error (Figure 13a) is the difference between the ideal and actual offset point. The offset point is the output value when the digital input is midscale. This error affects all codes by the same amount and usually can be compensated by trimming. 7 6 ANALOG OUTPUT VALUE 6 ANALOG OUTPUT VALUE MAX19707 10-Bit, 45Msps, Ultra-Low-Power Analog Front-End 5 4 AT STEP 011 (0.5 LSB) 3 2 AT STEP 001 (0.25 LSB) 1 DIFFERENTIAL LINEARITY ERROR (-0.25 LSB) 4 3 1 LSB 2 DIFFERENTIAL LINEARITY ERROR (+0.25 LSB) 1 0 0 000 001 010 011 100 101 DIGITAL INPUT CODE Figure 13a. Integral Nonlinearity 32 1 LSB 5 110 111 000 001 010 011 100 DIGITAL INPUT CODE Figure 13b. Differential Nonlinearity ______________________________________________________________________________________ 101 10-Bit, 45Msps, Ultra-Low-Power Analog Front-End Signal-to-Noise Plus Distortion (SINAD) SINAD is computed by taking the ratio of the RMS signal to the RMS noise. RMS noise includes all spectral components to the Nyquist frequency excluding the fundamental and the DC offset. ADC Dynamic Parameter Definitions Effective Number of Bits (ENOB) ENOB specifies the dynamic performance of an ADC at a specific input frequency and sampling rate. An ideal ADC’s error consists of quantization noise only. ENOB for a full-scale sinusoidal input waveform is computed from: Aperture Jitter Figure 14 shows the aperture jitter (tAJ), which is the sample-to-sample variation in the aperture delay. Aperture Delay Aperture delay (tAD) is the time defined between the rising edge of the sampling clock and the instant when an actual sample is taken (Figure 14). Signal-to-Noise Ratio (SNR) For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error) and results directly from the ADC’s resolution (N bits): SNR(max) = 6.02 x N + 1.76 In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the RMS signal to the RMS noise. RMS noise includes all spectral components to the Nyquist frequency excluding the fundamental, the first five harmonics, and the DC offset. CLK tAD tAJ SAMPLED DATA (T/H) TRACK HOLD Total Harmonic Distortion (THD) THD is typically the ratio of the RMS sum of the first five harmonics of the input signal to the fundamental itself. This is expressed as: ⎡ (V22 + V32 + V42 + V52 + V62 THD = 20 × log ⎢ V1 ⎢⎣ )⎤ ⎥ ⎥⎦ where V1 is the fundamental amplitude and V2–V6 are the amplitudes of the 2nd- through 6th-order harmonics. Third Harmonic Distortion (HD3) HD3 is defined as the ratio of the RMS value of the third harmonic component to the fundamental input signal. Spurious-Free Dynamic Range (SFDR) SFDR is the ratio expressed in decibels of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next-largest spurious component, excluding DC offset. Intermodulation Distortion (IMD) IMD is the total power of the intermodulation products relative to the total input power when two tones, f1 and f2, are present at the inputs. The intermodulation products are (f1 ± f2), (2 ✕ f1), (2 ✕ f2), (2 ✕ f1 ± f2), (2 ✕ f2 ± f1). The individual input tone levels are at -7dBFS. ANALOG INPUT T/H ENOB = (SINAD - 1.76) / 6.02 TRACK 3rd-Order Intermodulation (IM3) IM3 is the power of the worst 3rd-order intermodulation product relative to the input power of either input tone when two tones, f1 and f2, are present at the inputs. The 3rd-order intermodulation products are (2 x f1 ±f2), (2 ✕ f2 ±f1). The individual input tone levels are at -7dBFS. Figure 14. T/H Aperture Timing ______________________________________________________________________________________ 33 MAX19707 ADC Gain Error Ideally, the ADC full-scale transition occurs at 1.5 LSB below full scale. The gain error is the amount of deviation between the measured transition point and the ideal transition point with the offset error removed. MAX19707 10-Bit, 45Msps, Ultra-Low-Power Analog Front-End Power-Supply Rejection Power-supply rejection is defined as the shift in offset and gain error when the power supply is changed ±5%. Small-Signal Bandwidth A small -20dBFS analog input signal is applied to an ADC in so that the signal’s slew rate does not limit the ADC’s performance. The input frequency is then swept up to the point where the amplitude of the digitized conversion result has decreased by 3dB. Note that the T/H performance is usually the limiting factor for the small-signal input bandwidth. Full-Power Bandwidth A large -0.5dBFS analog input signal is applied to an ADC, and the input frequency is swept up to the point where the amplitude of the digitized conversion result has decreased by 3dB. This point is defined as the fullpower bandwidth frequency. DAC Dynamic Parameter Definitions Total Harmonic Distortion THD is the ratio of the RMS sum of the output harmonics up to the Nyquist frequency divided by the fundamental: ⎡ (V22 + V32 + ...+ Vn2 ) THD = 20 × log ⎢ V1 ⎢ ⎣ ⎤ ⎥ ⎥ ⎦ where V1 is the fundamental amplitude and V2 through Vn are the amplitudes of the 2nd through nth harmonic up to the Nyquist frequency. Spurious-Free Dynamic Range Spurious-free dynamic range (SFDR) is the ratio of RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next-largest distortion component up to the Nyquist frequency excluding DC. Selector Guide DESCRIPTION SAMPLING RATE (Msps) MAX19700 Dual 10-Bit Rx ADC, Dual 10-Bit Tx DAC, Integrated TD-SCDMA Filters, Three 12-Bit Auxiliary DACs 7.5 MAX19708 Dual 10-Bit Rx ADC, Dual 10-Bit Tx DAC, Integrated TD-SCDMA Filters, Three 12-Bit Auxiliary DACs, 10-Bit Auxiliary ADC with 4:1 Input Mux 11 Dual 10-Bit Rx ADC, Dual 10-Bit Tx DAC, Three 12-Bit Auxiliary DACs, 10-Bit Auxiliary ADC with 4:1 Input Mux 7.5/22/45 PART MAX19705/MAX19706/MAX19707 34 ______________________________________________________________________________________ 10-Bit, 45Msps, Ultra-Low-Power Analog Front-End VDD = 2.7V TO 3.3V IAP OVDD = 1.8V TO 3.3V 10-BIT ADC IAN MAX19707 SHDN T/R QAP 10-BIT ADC QAN HALFDUPLEX BUS IDP D0–D9 10-BIT DAC IDN QDP 10-BIT DAC QDN PROGRAMMABLE OFFSET/CM DAC1 12-BIT DAC DAC2 12-BIT DAC DAC3 12-BIT DAC SYSTEM CLOCK CLK SERIAL INTERFACE AND SYSTEM CONTROL DIN SCLK CS 1.024V REFERENCE BUFFER REFIN REFP REFN COM 10-BIT ADC DOUT VDD 0VDD ADC1 ADC2 4:1 MUX GND OGND ______________________________________________________________________________________ 35 MAX19707 Functional Diagram Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) E DETAIL A 32, 44, 48L QFN.EPS MAX19707 10-Bit, 45Msps, Ultra-Low-Power Analog Front-End (NE-1) X e E/2 k e D/2 C L (ND-1) X e D D2 D2/2 b L E2/2 C L k E2 C L C L L L e A1 A2 e A PACKAGE OUTLINE 32, 44, 48, 56L THIN QFN, 7x7x0.8mm 21-0144 36 ______________________________________________________________________________________ F 1 2 10-Bit, 45Msps, Ultra-Low-Power Analog Front-End PACKAGE OUTLINE 32, 44, 48, 56L THIN QFN, 7x7x0.8mm 21-0144 F 2 2 Revision History Pages changed at Rev 1: 1, 4, 6, 7, 10–15, 17, 33, 35, 36, 37 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 37 © 2007 Maxim Integrated Products Springer is a registered trademark of Maxim Integrated Products, Inc. MAX19707 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)