MAXIM MAX17528

19-4723; Rev 0; 7/09
KIT
ATION
EVALU
E
L
B
AVAILA
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
The MAX17528 comprises 1-phase Quick-PWM™ stepdown VID power-supply controllers for Intel notebook
CPUs. The Quick-PWM control provides instantaneous
response to fast-load current steps. Active voltage
positioning reduces power dissipation and bulk output
capacitance requirements and allows ideal positioning
compensation for tantalum, polymer, or ceramic bulk
output capacitors.
The MAX17528 is intended for two different notebook
CPU/GPU core applications: either bucking down the battery directly to create the core voltage, or bucking down
the +5V system supply. The single-stage conversion
method allows these devices to directly step down highvoltage batteries for the highest possible efficiency.
Alternatively, 2-stage conversion (stepping down the
+5V system supply instead of the battery) at higher
switching frequency provides the minimum possible
physical size.
A slew-rate controller allows controlled transitions
between VID codes. A thermistor-based temperature
sensor provides programmable thermal protection. A
current monitor provides an analog output current proportional to the processor load current.
The MAX17528 implements both the Intel IMVP-6.5
CPU core specifications (CLKEN pullup to 3.3V), as
well as the Intel GMCH graphics core specifications
(CLKEN = GND). The MAX17528 is available in a
32-pin, 5mm x 5mm TQFN package.
Features
o 1-Phase Quick-PWM Controller
o ±0.5% VOUT Accuracy Over Line, Load, and
Temperature
o 7-Bit IMVP-6.5 DAC
o IMVP-6.5 and GMCH Compliant
o Active Voltage Positioning with Adjustable Gain
o Accurate Droop and Current Limit
o Remote Output and Ground Sense
o Adjustable Output-Voltage Slew Rate
o Power-Good Window Comparator
o Current Monitor
o Temperature Comparator
o Drives Large Synchronous Rectifier FETs
o 2V to 26V Battery Input Range
o Adjustable Switching Frequency (600kHz max)
o Undervoltage and Thermal-Fault Protection
o Soft-Startup and Soft-Shutdown
o Internal Boost Diode
Ordering Information
PART
TEMP RANGE
o
-40 C to +105 C
MAX17528GTJ+
32 TQFN-EP*
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
Pin Configuration
PGND
D6
D5
D4
D3
24
VDD
Intel Calpella Platforms
DL
TOP VIEW
BST
Applications
IMVP-6.5 Core Power Supply
Intel GMCH 2009
PIN-PACKAGE
o
23
22
21
20
19
18
17
Graphics Core Power Supply
LX 25
16
D2
Voltage-Positioned Step-Down Converters
DH 26
15
D1
PGDIN 27
14
D0
VRHOT 28
13
GND
12
CLKEN
11
SHDN
VCC 31
10
PWRGD
CCV 32
9
TON
1-to-4 Lithium-Ion (Li+)-Cell Battery-to-CPU Core
Supply Converters
Notebooks/Desktops/Servers
MAX17528
TIME 29
PAD
GND
Quick-PWM is a trademark of Maxim Integrated Products, Inc.
1
2
3
4
5
6
7
8
IMON
GNDS
FB
CSN
CSP
SLOW
SKIP
THRM
ILIM 30
THIN QFN
5mm x 5mm
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1
MAX17528
General Description
MAX17528
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
ABSOLUTE MAXIMUM RATINGS
BST to GND ............................................................-0.3V to +36V
LX to BST..................................................................-6V to +0.3V
BST to VDD.............................................................-0.3V to +30V
DH to LX ....................................................-0.3V to (VBST + 0.3V)
Continuous Power Dissipation (32-pin, 5mm x 5mm TQFN)
Up to +70°C ..............................................................1702mW
Derating above +70°C ..........................................21.3mW/°C
Operating Temperature Range .........................-40°C to +105°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +165°C
Lead Temperature (soldering, 10s) .................................+300°C
VCC, VDD to GND .....................................................-0.3V to +6V
D0–D6 to GND..........................................................-0.3V to +6V
CSP, CSN to GND ....................................................-0.3V to +6V
ILIM, THRM, PGDIN, VRHOT, PWRGD to GND .......-0.3V to +6V
CLKEN to GND.........................................................-0.3V to +6V
SKIP, SLOW to GND.................................................-0.3V to +6V
CCV, FB, IMON, TIME to GND ...................-0.3V to (VCC + 0.3V)
SHDN to GND (Note 1)...........................................-0.3V to +30V
TON to GND ...........................................................-0.3V to +30V
GNDS, PGND to GND ...........................................-0.3V to +0.3V
DL to PGND................................................-0.3V to (VDD + 0.3V)
Note 1: SHDN can be forced to 12V for the purpose of debugging prototype breadboards using the no-fault test mode, which disables fault protection.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, VIN = 12V, VDD = VCC = 5V, CLKEN pullup to 3.3V with 1.9kΩ, SHDN = SLOW = ILIM = PGDIN = VCC, SKIP =
GNDS = PGND = GND, VFB = VCSP = VCSN = 1.200V, D0–D6 set for 1.20V (D0–D6 = 0001100). TA = 0°C to +85°C, unless otherwise
specified. Typical values are at TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
4.5
5.5
V
DAC codes from
0.8125V to 1.5000V
-0.5
+0.5
%
DAC codes from
0.3750V to 0.8000V
-7
+7
DAC codes from 0V
to 0.3625V
-20
+20
PWM CONTROLLER
Input-Voltage Range
VCC, VDD
DC Output-Voltage Accuracy
Measured at FB with
respect to GNDS;
includes loadregulation error
(Note 3)
Boot Voltage
VBOOT
Line Regulation Error
mV
IMVP-6.5 (CLKEN pullup to 3.3V with 1.9k)
GNDS Input Range
A GNDS
VOUT/VGNDS, -200mV VGNDS +200mV
GNDS Input Bias Current
IGNDS
TA = +25°C
TIME Voltage
VTIME
VCC = 4.5V to 5.5V,
ITIME = 28µA (RTIME = 71.5k)
2
1.100
1.106
0.1
-200
GNDS Gain
TIME Slew-Rate Accuracy
1.094
VCC = 4.5V to 5.5V, VIN = 4.5V to 26V
0.97
1.00
-2
1.985
2.000
+200
mV
1.03
V/V
+2
µA
2.015
V
RTIME = 71.5k (12.5mV/µs nominal)
-10
+10
RTIME = 35.7k (25mV/µs nominal) to
178k (5mV/µs nominal)
-15
+15
Soft-start and soft-shutdown;
RTIME = 35.7k (3.125mV/µs nominal) to
178k (0.625mV/µs nominal)
-20
+20
SLOW = GND,
RTIME = 35.7k (12.5mV/µs nominal) to
178k (2.5mV/µs nominal)
-20
+20
_______________________________________________________________________________________
V
%
%
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
(Circuit of Figure 1, VIN = 12V, VDD = VCC = 5V, CLKEN pullup to 3.3V with 1.9kΩ, SHDN = SLOW = ILIM = PGDIN = VCC, SKIP =
GNDS = PGND = GND, VFB = VCSP = VCSN = 1.200V, D0–D6 set for 1.20V (D0–D6 = 0001100). TA = 0°C to +85°C, unless otherwise
specified. Typical values are at TA = +25°C.) (Note 2)
PARAMETER
On-Time
SYMBOL
t ON
Minimum Off-Time
t OFF(MIN)
TON Shutdown Input Current
CONDITIONS
VIN = 12V,
VFB = 1.2V
(Note 4)
MIN
TYP
MAX
RTON = 96.75k
142
167
192
RTON = 200k
300
333
366
RTON = 303.25k
425
UNITS
ns
500
575
Measured at DH (Note 4)
300
375
ns
SHDN = GND, VIN = 26V, VCC = VDD = 0V or
5V, TA = +25°C
0.01
1
µA
BIAS CURRENTS
Quiescent Supply Current (VCC)
ICC
Measured at VCC, VSKIP = 5V, FB forced
above the regulation point
1.5
3
mA
Quiescent Supply Current (VDD)
IDD
Measured at VDD, SKIP = GND,
FB forced above the regulation point,
TA = +25°C
0.02
1
µA
Shutdown Supply Current (VCC)
Measured at VCC, SHDN = GND
Shutdown Supply Current (VDD)
Measured at VDD, SHDN = GND, TA = +25°C
15
30
µA
0.01
1
µA
-400
-350
mV
FAULT PROTECTION
Output Undervoltage-Protection
Threshold
VUVP
Measured at FB with respect to unloaded
output voltage
Output Undervoltage
Propagation Delay
tUVP
FB forced 25mV below trip threshold
IMVP-6.5 CLKEN Startup Delay
(Boot Time Period, CLKEN Pullup
to 3.3V with 1.9k)
tBOOT
PWRGD and CLKEN (IMVP-6.5,
CLKEN Pullup to 3.3V with
1.9k) Transition Blanking Time
PWRGD and CLKEN (IMVP-6.5,
CLKEN Pullup to 3.3V with
1.9k) Delay
tBLANK
µs
20
60
100
IMVP-6.5: CLKEN pullup to 3.3V with 1.9k;
measured at startup from the time when
CLKEN goes low
3
5
8
Measured at FB
with respect to
unloaded output
voltage, 15mV
hysteresis (typ)
PWRGD and CLKEN (IMVP-6.5,
CLKEN Pullup to 3.3V with
1.9k) Threshold
10
IMVP-6.5: CLKEN pullup to 3.3V with 1.9k;
measured from the time when FB reaches
the boot target voltage (Note 3); the time
needed for FB to reach this target voltage is
based on the slew rate set by RTIME
GMCH: CLKEN = GND; measured from the
time when FB reaches the target voltage (Note
3); the time needed for FB to reach this target
voltage is based on the slew rate set by RTIME
PWRGD Startup Delay
-450
µs
ms
3
5
8
Lower threshold,
falling edge
(undervoltage)
-350
-300
-250
Upper threshold, rising
edge (overvoltage)
+150
mV
+200
+250
Measured from the time when FB reaches
the target voltage (Note 3) based on the
slew rate set by RTIME
20
µs
FB forced 25mV outside the PWRGD
trip thresholds
10
µs
_______________________________________________________________________________________
3
MAX17528
ELECTRICAL CHARACTERISTICS (continued)
MAX17528
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN = 12V, VDD = VCC = 5V, CLKEN pullup to 3.3V with 1.9kΩ, SHDN = SLOW = ILIM = PGDIN = VCC, SKIP =
GNDS = PGND = GND, VFB = VCSP = VCSN = 1.200V, D0–D6 set for 1.20V (D0–D6 = 0001100). TA = 0°C to +85°C, unless otherwise
specified. Typical values are at TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
IMVP-6.5 CLKEN Output
Low Voltage
IMVP-6.5: CLKEN pullup to 3.3V with 1.9k;
I SINK = 3mA
IMVP-6.5 CLKEN High
Leakage Current
IMVP-6.5: VPGDIN = 5V, V CLKEN = 3.3V
IMVP-6.5 CLKEN Shutdown
Leakage Current
IMVP-6.5: V SHDN = GND, V CLKEN = 3.3V
PWRGD Output Low Voltage
I SINK = 3mA
PWRGD Leakage Current
VCC Undervoltage Lockout
Threshold
MIN
TYP
MAX
UNITS
0.4
V
2
4
µA
0.01
1
µA
0.4
V
1
µA
4.48
V
High state, PWRGD forced to 5V, TA = +25°C
Rising edge, 65mV typical hysteresis,
VUVLO(VCC)
controller disabled below this level
4.05
SHDN = GND and drivers disabled
(not switching)
CSN Discharge Resistance in
UVLO and Shutdown
4.27
8
THERMAL PROTECTION
Measured at THRM with respect to VCC;
falling edge; typical hysteresis = 100mV
VRHOT Trip Threshold
29.2
30
VRHOT Delay
t VRHOT
THRM forced 25mV below the VRHOT trip
threshold; falling edge
10
VRHOT Output On-Resistance
RVRHOT
Low state
2
VRHOT Leakage Current
I VRHOT
High state, VRHOT forced to 5V, TA = +25°C
THRM Input Leakage
ITHRM
VTHRM = 0V to 5V, TA = +25°C
Thermal-Shutdown Threshold
T SHDN
Typical hysteresis = 15°C
-100
30.8
%
µs
8
1
µA
+100
nA
+160
°C
VALLEY CURRENT LIMIT AND DROOP
Current-Limit Threshold Voltage
(Positive Adjustable)
VLIMIT
Current-Limit Threshold Voltage
(Positive Default) Preset
Current-Limit Threshold Voltage
(Negative) Accuracy
Current-Limit Threshold Voltage
(Zero Crossing)
VCSP - VCSN
VTIME - VILIM = 100mV
7
10
13
VTIME - VILIM = 500mV
45
50
55
20
22.5
25
mV
+4
mV
VCSP - VCSN, ILIM = VCC
VLIMIT(NEG) VCSP - VCSN, nominally -125% of VLIMIT
VZERO
VPGND - VLX, SKIP = VCC
CSP, CSN Common-Mode
Input Range
CSP, CSN Input Current
-4
TA = +25°C
1
mV
mV
0
2
V
-0.2
+0.2
µA
ILIM Input Current
TA = +25°C
-100
+100
nA
DC Droop Amplifier (GMD) Offset
(VCSP - VCSN) at IFB = 0
-0.75
+0.75
mV
DC Droop Amplifier (GMD)
Transconductance
IFB/(VCSP - VCSN); VFB = VCSN = 0.45V to
2.0V, and (VCSP - VCSN) = -15.0mV to +15.0mV
592
608
µS
4
600
_______________________________________________________________________________________
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
(Circuit of Figure 1, VIN = 12V, VDD = VCC = 5V, CLKEN pullup to 3.3V with 1.9kΩ, SHDN = SLOW = ILIM = PGDIN = VCC, SKIP =
GNDS = PGND = GND, VFB = VCSP = VCSN = 1.200V, D0–D6 set for 1.20V (D0–D6 = 0001100). TA = 0°C to +85°C, unless otherwise
specified. Typical values are at TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
GATE DRIVERS
DH Gate-Driver On-Resistance
R ON(DH)
DL Gate-Driver On-Resistance
R ON(DL)
DH Gate-Driver Source Current
DH Gate-Driver Sink Current
DL Gate-Driver Source Current
DL Gate-Driver Sink Current
High state (pullup)
0.9
2.5
Low state (pulldown)
0.7
2.0
High state (pullup)
0.7
2.0
Low state (pulldown)
0.25
0.7
IDH(SOURCE) DH forced to 2.5V, BST - LX forced to 5V
IDH(SINK)
2.2
DH forced to 2.5V, BST - LX forced to 5V
IDL(SINK)
DL Transition Time
DH Transition Time
RBST
A
2.7
A
2.7
A
DL forced to 2.5V
8
A
DH low to DL high
20
DL low to DH high
20
IDL(SOURCE) DL forced to 2.5V
Driver Propagation Delay
Internal BST Switch On-Resistance
BST - LX forced
to 5V
ns
DL falling, CDL = 3nF
20
DL rising, CDL = 3nF
20
DH falling, CDH = 3nF
20
DH rising, CDH = 3nF
20
IBST = 10mA, VDD = 5V (Note 6)
10
20
5.0
5.1
mS
+1.0
mV
1.15
V
1.0
V
ns
ns
CURRENT MONITOR
Current-Monitor
Transconductance
Gm(IMON)
Current-Monitor Offset
Referred to V(CSP, CSN)
IMON Clamp Voltage
VIMON
I IMON/(VCSP - VCSN),
VCSN = 0.45V to 2.0V
4.9
I IMON = 0
-1.0
I IMON = -1mA
1.05
2.3
1.10
LOGIC AND I/O
Logic-Input High Voltage
VIH
PGDIN
Logic-Input Low Voltage
VIL
PGDIN
Low-Voltage LogicInput High Voltage
VIHLV
SHDN, SKIP, SLOW, D0–D6
Low-Voltage LogicInput Low Voltage
VILLV
SHDN, SKIP, SLOW, D0–D6
PGDIN, SHDN, SKIP, SLOW, D0–D6 = 0 or
5V, TA = +25°C
Logic-Input Current
CLKEN Logic-Input High Voltage
for IMVP-6.5 Startup
CLKEN Logic-Input Low Voltage
for GMCH
V
0.67
-1
V
0.33
V
+1
µA
2.3
V
1.0
V
_______________________________________________________________________________________
5
MAX17528
ELECTRICAL CHARACTERISTICS (continued)
MAX17528
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, VIN = 12V, VDD = VCC = 5V, CLKEN pullup to 3.3V with 1.9kΩ, SHDN = SLOW = ILIM = PGDIN = VCC, SKIP =
GNDS = PGND = GND, VFB = VCSP = VCSN = 1.200V, D0–D6 set for 1.20V (D0–D6 = 0001100). TA = -40°C to +105°C, unless otherwise specified.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
4.5
5.5
V
DAC codes from
0.8125V to 1.5000V
-0.75
+0.75
%
DAC codes from
0.3750V to 0.8000V
-10
+10
PWM CONTROLLER
Input-Voltage Range
VCC, VDD
DC Output-Voltage Accuracy
Measured at FB with
respect to GNDS;
includes loadregulation error
(Note 3)
Boot Voltage
VBOOT
mV
DAC codes from 0V
to 0.3625V
IMVP-6.5 (CLKEN pullup to 3.3V with 1.9k)
GNDS Input Range
-25
+25
1.085
1.115
V
-200
+200
mV
GNDS Gain
A GNDS
VOUT/VGNDS, -200mV VGNDS +200mV
0.95
1.05
V/V
TIME Voltage
VTIME
VCC = 4.5V to 5.5V,
ITIME = 28µA (RTIME = 71.5k)
1.98
2.02
V
RTIME = 71.5k (12.5mV/µs nominal)
-10
+10
RTIME = 35.7k (25mV/µs nominal) to
178k (5mV/µs nominal)
-15
+15
Soft-start and soft-shutdown;
RTIME = 35.7k (3.125mV/µs nominal) to
178k (0.625mV/µs nominal)
-20
+20
SLOW = GND,
RTIME = 35.7k (12.5mV/µs nominal) to
178k (2.5mV/µs nominal)
-20
+20
TIME Slew-Rate Accuracy
On-Time
Minimum Off-Time
t ON
t OFF(MIN)
VIN = 12V, VFB = 1.2V
(Note 4)
RTON = 96.75k
142
192
RTON = 200k
300
366
RTON = 303.25k
425
575
Measured at DH (Note 4)
%
ns
400
ns
3
mA
BIAS CURRENTS
Quiescent Supply Current (VCC)
ICC
Measured at VCC, VSKIP = 5V,
FB forced above the regulation point
FAULT PROTECTION
Output Undervoltage-Protection
Threshold
IMVP-6.5 CLKEN Startup Delay
(Boot Time Period, CLKEN Pullup
to 3.3V with 1.9k)
6
VUVP
Measured at FB with respect to unloaded
output voltage
-460
-340
mV
tBOOT
IMVP-6.5, CLKEN pullup to 3.3V with
1.9k; measured from the time when FB
reaches the boot target voltage (Note 3);
the time needed for FB to reach this target
voltage is based on the slew rate set by
RTIME
20
100
µs
_______________________________________________________________________________________
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
(Circuit of Figure 1, VIN = 12V, VDD = VCC = 5V, CLKEN pullup to 3.3V with 1.9kΩ, SHDN = SLOW = ILIM = PGDIN = VCC, SKIP =
GNDS = PGND = GND, VFB = VCSP = VCSN = 1.200V, D0–D6 set for 1.20V (D0–D6 = 0001100). TA = -40°C to +105°C, unless otherwise specified.) (Note 2)
PARAMETER
SYMBOL
PWRGD Startup Delay
CONDITIONS
MIN
MAX
UNITS
IMVP-6.5, CLKEN pullup to 3.3V with 1.9k;
measured at startup from the time when
CLKEN goes low
3
8
ms
GMCH, CLKEN = GND; measured from the
time when FB reaches the target voltage
(Note 3); the time needed for FB to reach
this target voltage is based on the slew rate
set by RTIME
3
8
µs
Lower threshold, falling
edge (undervoltage)
-360
-240
Upper threshold, rising
edge (overvoltage)
+140
+260
PWRGD and CLKEN (IMVP-6.5,
CLKEN Pullup to 3.3V with
1.9k) Threshold
Measured at FB
with respect to
unloaded output
voltage, 15mV
hysteresis (typ)
IMVP-6.5 CLKEN Output
Low Voltage
IMVP-6.5: CLKEN pullup to 3.3V with
1.9k, I SINK = 3mA
IMVP-6.5 CLKEN High
Leakage Current
IMVP-6.5 = PGDIN = 5V, V CLKEN = 3.3V
PWRGD Output Low Voltage
I SINK = 3mA
VCC Undervoltage Lockout
(UVLO) Threshold
VUVLO(VCC)
mV
0.4
V
4
µA
0.4
V
Rising edge, 65mV typical hysteresis,
controller disabled below this level
4.0
4.5
V
Measured at THRM with respect to VCC;
falling edge; typical hysteresis = 100mV
29
31
%
8
THERMAL PROTECTION
VRHOT Trip Threshold
VRHOT Output On-Resistance
RVRHOT
Low state
VALLEY CURRENT LIMIT AND DROOP
Current-Limit Threshold Voltage
(Positive Adjustable)
Current-Limit Threshold Voltage
(Positive Default Preset)
Current-Limit Threshold Voltage
(Negative) Accuracy
VLIMIT
VCSP - VCSN
VTIME - VILIM = 100mV
7
13
VTIME - VILIM = 500mV
45
55
20
25
mV
-5
+5
mV
0
2
V
VCSP - VCSN, ILIM = VCC
VLIMIT(NEG) VCSP - VCSN, nominally -125% of VLIMIT
CSP, CSN Common-Mode
Input Range
mV
DC Droop Amplifier (GMD) Offset
(VCSP - VCSN) at IFB = 0
-1.0
+1.0
mV
DC Droop Amplifier (GMD)
Transconductance
IFB/(VCSP - VCSN); FB = VCSN = 0.45V to
2.0V, and (VCSP - VCSN) = -15.0mV to
+15.0mV
588
612
µS
_______________________________________________________________________________________
7
MAX17528
ELECTRICAL CHARACTERISTICS (continued)
MAX17528
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VIN = 12V, VDD = VCC = 5V, CLKEN pullup to 3.3V with 1.9kΩ, SHDN = SLOW = ILIM = PGDIN = VCC, SKIP =
GNDS = PGND = GND, VFB = VCSP = VCSN = 1.200V, D0–D6 set for 1.20V (D0–D6 = 0001100). TA = -40°C to +105°C, unless otherwise specified.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
GATE DRIVERS
DH Gate-Driver On-Resistance
R ON(DH)
DL Gate-Driver On-Resistance
R ON(DL)
Internal BST Switch
On-Resistance
BST - LX forced
to 5V
High state (pullup)
2.5
Low state (pulldown)
2.0
High state (pullup)
2.0
Low state (pulldown)
0.7
20
4.9
5.1
mS
I IMON = 0
-1.5
+1.5
mV
I IMON = -1mA
1.05
1.15
V
RBST
IBST = 10mA, VDD = 5V
Gm(IMON)
I IMON/(VCSP - VCSN),
VCSN = 0.45V to 2.0V
CURRENT MONITOR
Current-Monitor
Transconductance
Current-Monitor Offset
Referred to V(CSP, CSN)
IMON Clamp Voltage
VIMON
LOGIC AND I/O
Logic-Input High Voltage
VIH
PGDIN
Logic-Input Low Voltage
VIL
PGDIN
Low-Voltage LogicInput High Voltage
VIHLV
SHDN, SKIP, SLOW, D0–D6
Low-Voltage LogicInput Low Voltage
VILLV
SHDN, SKIP, SLOW, D0–D6
CLKEN Logic-Input High Voltage
for IMVP-6.5 Startup
2.3
V
1.0
0.67
V
0.33
2.3
CLKEN Logic-Input Low Voltage
for GMCH
V
V
V
1.0
V
Note 2: Limits are 100% production tested at TA = +25°C. Maximum and minimum limits over temperature are guaranteed by design
and characterization.
Note 3: The equation for the target voltage VTARGET is:
VTARGET = the slew-rate-controlled version of VDAC, where VDAC = 0V for shutdown, VDAC = VBOOT (IMVP-6.5) or VVID
(GMCH) during startup, and VDAC = VVID otherwise (the VVID voltages for all possible VID codes are given in Table 2).
In pulse-skipping mode, the output rises by approximately 1.5% when transitioning from continuous conduction to no load.
Note 4: On-time and minimum off-time specifications are measured from 50% to 50% at the DH pin, with LX forced to 0V, BST forced
to 5V, and a 500pF capacitor from DH to LX to simulate external MOSFET gate capacitance. Actual in-circuit times can be
different due to MOSFET switching speeds.
8
_______________________________________________________________________________________
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
70
20V
90
0.90
SKIP MODE
PWM MODE
50
0.01
0.1
1
10
0.88
PWM MODE
80
70
20V
60
50
0.84
100
12V
7V
0.86
60
0
5
10
15
20
0.01
25
0.1
1
10
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
0.65V OUTPUT VOLTAGE
vs. LOAD CURRENT
OUTPUT EFFICIENCY
vs. LOAD CURRENT
OUTPUT VOLTAGE
vs. LOAD CURRENT
90
EFFICIENCY (%)
0.65
0.64
12V
7V
SKIP MODE
80
70
PWM MODE
20V
MAX17528 toc06
SKIP MODE
PWM MODE
1.10
OUTPUT VOLTAGE (V)
0.66
1.12
MAX17528 toc05
100
MAX17528 toc04
0.67
OUTPUT VOLTAGE (V)
SKIP MODE
PWM MODE
EFFICIENCY (%)
80
100
MAX17528 toc02
SKIP MODE
OUTPUT VOLTAGE (V)
EFFICIENCY (%)
12V
7V
0.92
MAX17528 toc01
100
90
0.65V OUTPUT EFFICIENCY
vs. LOAD CURRENT
0.9V OUTPUT VOLTAGE
vs. LOAD CURRENT
MAX17528 toc03
0.9V OUTPUT EFFICIENCY
vs. LOAD CURRENT
SKIP MODE
1.08
1.06
PWM MODE
1.04
1.02
60
0.63
1.00
0.62
2
4
6
8
0
10
2
4
6
8
VOUT = 0.9V NO-LOAD
SUPPLY CURRENT vs. INPUT VOLTAGE
VOUT = 0.65V
VOUT = 0.9V
PWM MODE
200
150
100
IIN (PWM)
ICC + IDD (PWM)
10
ICC + IDD (SKIP)
1
IIN (SKIP)
SKIP MODE
50
SKIP MODE
PWM MODE
50
0
0.1
0
0.1
1
LOAD CURRENT (A)
10
100
MAX17528 toc09
MAX17528 toc08
250
100
SUPPLY CURRENT (mA)
250
300
SWITCHING FREQUENCY (kHz)
300
0.01
10
SWITCHING FREQUENCY
vs. LOAD CURRENT
MAX17528 toc07
SWITCHING FREQUENCY (kHz)
1
SWITCHING FREQUENCY
vs. LOAD CURRENT
350
100
0.1
LOAD CURRENT (A)
400
200
0.01
LOAD CURRENT (A)
SKIP MODE
PWM MODE
450
10
LOAD CURRENT (A)
500
150
0.98
50
0
0.01
0.1
1
INPUT VOLTAGE (V)
10
6
9
12
15
18
21
24
INPUT VOLTAGE (V)
_______________________________________________________________________________________
9
MAX17528
Typical Operating Characteristics
(TA = +25°C, unless otherwise noted. Circuit of Figure 1.)
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted. Circuit of Figure 1.)
VOUT = 0.65V NO-LOAD
SUPPLY CURRENT vs. INPUT VOLTAGE
100
IIN (PWM)
ICC + IDD (PWM)
10
10
IBIAS (mA)
ICC + IDD (PWM)
ICC + IDD (SKIP)
1
ICC + IDD (SKIP)
1
IIN (SKIP)
IIN (SKIP)
24
6
IMON TRANSCONDUCTANCE
DISTRIBUTION
MAX17528 toc12
75
60
12
45
8
30
VCSP-N (mV)
606
604
602
600
0.8175
0.8165
0.8155
0.8145
0.8135
0.8125
0.8115
0
0.8105
0
598
20
10
0.8095
5.06
30
10
OUTPUT VOLTAGE (V)
TRANSCONDUCTANCE (µS)
______________________________________________________________________________________
MAX17528 toc15
SAMPLE SIZE = 100
40
592
20
50
+85°C
+25°C
590
30
60
SAMPLE PERCENTAGE (%)
40
MAX17528 toc14
SAMPLE SIZE = 100
50
0.8085
5.04
Gm (FB) TRANSCONDUCTANCE DISTRIBUTION
0.8125V OUTPUT VOLTAGE DISTRIBUTION
0.8075
5.02
IMON TRANSCONDUCTANCE (mS)
70
+85°C
+25°C
5.00
0
16
4.98
14
4.96
12
4.94
10
596
8
594
6
30
4.92
0
4
40
10
0
2
50
20
15
SKIP
PWM
SAMPLE SIZE = 100
60
4.90
4
+85°C
+25°C
70
PERCENTAGE (%)
16
24
90
IMON (µA)
ERROR (%)
21
IMON CURRENT AND ERROR
vs. LOAD CURRENT
80
60
18
15
INPUT VOLTAGE (V)
20
0
12
9
5.10
21
5.08
18
15
INPUT VOLTAGE (V)
610
12
9
608
6
SKIP MODE
PWM MODE
0.1
MAX17528 toc13
SKIP MODE
PWM MODE
0.1
10
MAX17528 toc11
IIN (PWM)
SUPPLY CURRENT (mA)
NO-LOAD SUPPLY CURRENT
vs. INPUT VOLTAGE
MAX17528 toc10
100
SAMPLE PERCENTAGE (%)
MAX17528
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
IMVP-6.5 SOFT-START
WAVEFORM (UP TO CLKEN)
IMVP-6.5 SOFT-START
WAVEFORM (UP TO PWRGD)
MAX17528 toc16
5V
A
0
5V
0
IMVP-6.5 SHUTDOWN WAVEFORM
MAX17528 toc17
B
MAX17528 toc18
5V
A
5V
0
5V
B
0
3.3V
0
5V
C
0
1V
1V
A
B
0
5V
C
0
5V
C
D
D
0
0.9V
0
D
0
E
0
200µs/div
A. SHDN, 5V/div
B. CLKEN, 5V/div
E
0
F
0
1ms/div
C. VOUT, 500mV/div
D. INDUCTOR CURRENT,
10A/div
A. SHDN, 5V/div
B. PWRGD, 5V/div
C. CLKEN, 5V/div
100µs/div
D. VOUT, 500mV/div
E. INDUCTOR CURRENT,
10A/div
A. SHDN, 5V/div
B. CLKEN, 3.3V/div
C. PWRGD, 5V/div
LOAD-TRANSIENT RESPONSE
(IMVP-6.5 HFM MODE)
GMCH SHUTDOWN WAVEFORM
GMCH SOFT-START WAVEFORM
MAX17528 toc21
MAX17528 toc20
MAX17528 toc19
5V
A
5V
A
0
5V
B
0
E. DL, 5V/div
D. VOUT, 1V/div
F. INDUCTOR CURRENT,
5A/div
0
5V
A
B
5.5A
0
5V
0.9V
C
23A
C
0
1.0815V
0.9V
0.863V
B
23A
0
D
0
D
E
0
0
100µs/div
1ms/div
A. SHDN, 5V/div
B. PWRGD, 5V/div
C. VOUT, 500mV/div
D. INDUCTOR CURRENT,
10A/div
A. SHDN, 5V/div
B. PWRGD, 5V/div
C. DL, 5V/div
D. VOUT, 500mV/div
E. INDUCTOR CURRENT,
5A/div
C
5.5A
20µs/div
A. IOUT = 5.5A TO 23A,
10A/div
B. VOUT, 50mV/div
C. INDUCTOR CURRENT,
10A/div
______________________________________________________________________________________
11
MAX17528
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted. Circuit of Figure 1.)
MAX17528
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted. Circuit of Figure 1.)
LOAD-TRANSIENT RESPONSE
(IMVP-6.5 LFM MODE)
DPRSLPVR = HIGH, SLOW = LOW,
VID5 TRANSITION
LOAD-TRANSIENT RESPONSE
MAX17528 toc24
MAX17528 toc23
MAX17528 toc22
8A
9.5A
A
3.5A
1V
0
1.5A
1V
1.0815V
0.8375V
A
A
B
0.825V
B
B
1.03V
0.6V
8A
C
C
9.5A
3.5A
C
1.5A
0
A. IOUT = 3.5A TO 9.5A,
5A/div
B. VOUT, 20mV/div
A. IOUT = 1.5A TO 8A,
5A/div
B. VOUT, 50mV/div
C. INDUCTOR CURRENT,
10A/div
A. VID5, 1V/div
B. VOUT, 200mV/div
C. INDUCTOR CURRENT,
5A/div
C. INDUCTOR CURRENT,
10A/div
IOUT = 1A
D0 12.5mV DYNAMIC VID
CODE CHANGE
DPRSLPVR = HIGH, SLOW = HIGH,
VID5 TRANSITION
D2 50mV DYNAMIC VID
CODE CHANGE
MAX17528 toc26
MAX17528 toc25
5V
1V
40µs/div
20µs/div
20µs/div
MAX17528 toc27
A
A
A
0
0
0
5V
1V
B
B
0.9V
0.8875V
0.85V
0.6V
C
0
C
0
C. INDUCTOR CURRENT,
10A/div
C
0
10µs/div
40µs/div
A. VID5, 1V/div
B. VOUT, 200mV/div
B
0.9V
A. D0, 5V/div
B. VOUT, 20mV/div
C. INDUCTOR CURRENT,
2A/div
10µs/div
A. D2, 5V/div
B. VOUT, 50mV/div
IOUT = 1A
12
______________________________________________________________________________________
C. INDUCTOR CURRENT,
2A/div
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
BIAS SUPPLY REMOVAL
(UVLO RESPONSE)
OUTPUT OVERLOAD WAVEFORM
MAX17528 toc29
MAX17528 toc28
5V
1V
A
0.9V
A
0
5V
B
0
5V
B
0
5V
C
0
C
0
5V
D
0
D
0
10A
E
0
100µs/div
A. VOUT, 500mV/div
B. PGOOD, 5V/div
C. DL, 5V/div
D. INDUCTOR CURRENT,
10A/div
200µs/div
A. 5V BIAS SUPPLY, 5V/div D. PGOOD, 5V/div
B. VOUT, 500mV/div
E. INDUCTOR CURRENT,
C. DL, 5V/div
10A/div
______________________________________________________________________________________
13
MAX17528
Typical Operating Characteristics (continued)
(TA = +25°C, unless otherwise noted. Circuit of Figure 1.)
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
MAX17528
Pin Description
PIN
NAME
FUNCTION
Current Monitor Output. The MAX17528 IMON output sources a current that is directly proportional
to the current-sense voltage as defined by:
I IMON = Gm(IMON) x (VCSP - VCSN)
where Gm(IMON) = 5mS (typ).
The IMON current is unidirectional (sources current out of IMON only) for positive current-sense
values. For negative current-sense voltages, the IMON current is zero.
Connect an external resistor between IMON and VSS_SENSE to create the desired IMON gain
based on the following equation:
1
2
IMON
GNDS
RIMON = 0.999V/(IMAX x R SENSE x Gm(IMON))
where IMAX is defined in the Current Monitor (IMON) section of the Intel IMVP-6.5 specification and
based on discrete increments (20A, 30A, 40A, etc.,), RSENSE is the typical effective value of the
current-sense element (sense resistor or inductor DCR) that is used to provide the current-sense
voltage, and Gm(IMON) is the typical transconductance amplifier gain as defined in the Electrical
Characteristics table.
The IMON voltage is internally clamped to a maximum of 1.1V (typ).
The transconductance amplifier and voltage clamp are internally compensated, so IMON cannot
directly drive large capacitance values. To filter the IMON signal, use an RC filter as shown in
Figure 1. IMON is pulled to ground when the MAX17528 is in shutdown.
Remote Ground-Sense Input. Connect directly to the CPU or GMCH VSS sense pin (ground sense)
or directly to the ground connection of the load. GNDS internally connects to a transconductance
amplifier that adjusts the feedback voltage, compensating for voltage drops between the
regulator’s ground and the processor’s ground.
Output of the Voltage-Positioning Transconductance Amplifier. Connect a resistor, RFB, between
FB and the positive side of the feedback remote sense to set the steady-state droop based on the
voltage-positioning gain requirement.
RFB = RDROOP/(RSENSE x GMD)
3
14
FB
4
CSN
5
CSP
6
SLOW
where RDROOP is the desired voltage-positioning slope, GMD = 600µS typ and RSENSE is the
value of the current-sense resistor that is used to provide the (CSP, CSN), current-sense voltage. If
lossless sensing is used, R SENSE = RL. In this case, consider using a thermistor-resistor network
to minimize the temperature dependence of the voltage-positioning slope. Droop can be disabled
by shorting FB to the positive remote-sense point, but doing so increases the minimum ESR
requirement of the output capacitance for stability, and FB might therefore need to be driven by a
carefully designed feed-forward network. FB is high impedance in shutdown.
Negative Inductor Current-Sense Input. Connect CSN to the negative terminal of the inductor
current-sensing resistor or directly to the negative terminal of the inductor if the lossless DCR
sensing method is used (see Figure 4).
Under VCC UVLO conditions and after soft-shutdown is completed, CSN is internally pulled to GND
through a 10 FET to discharge the output.
Positive Inductor Current-Sense Input. Connect CSP to the positive terminal of the inductor currentsensing resistor or directly to the positive terminal of the filtering capacitor used when the
lossless DCR sensing method is used (see Figure 4).
Active-Low Slew-Rate Select Input. This 1.0V logic input signal selects between the nominal and
slow (half of nominal rate) slew rates. When SLOW is forced high, the selected nominal slew rate is
set by the time resistance. When SLOW is forced low, the slew rate is reduced to half of the
nominal slew rate.
For IMVP-6.5 applications (CLKEN pullup to 3.3V with 1.9k), the fast slew rate is not needed.
Connect SLOW to GND.
For GMCH 2009 applications (CLKEN = GND), connect to the system GFXDPRSLPVR signal.
______________________________________________________________________________________
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
PIN
7
8
NAME
SKIP
THRM
FUNCTION
Pulse-Skipping Control Input. This 1.0V logic input signal indicates power usage and sets the
operating mode of the MAX17528. When SKIP is forced high, the controller is immediately set to
automatic pulse-skipping mode. The controller returns to forced-PWM mode when SKIP is forced low
and the output is in regulation. The PWRGD upper threshold is blanked during any downward outputvoltage transition that happens when the controller is in skip mode, and stays blanked until the
transition-related PWRGD blanking period is complete and the output reaches regulation.
IMVP-6.5: The MAX17528 is in skip mode during startup and while in boot mode, but is in forced-PWM
mode during the transition from boot mode to VID mode plus 20µs, and during soft-shutdown,
irrespective of the skip logic level. Connect to the system DPRSLPVR signal.
GMCH 2009: The MAX17528 is in skip mode during startup, while in standby mode, and while exiting
standby mode, but is in forced-PWM mode during soft-shutdown, and while entering standby mode,
irrespective of the skip logic level. Connect to the system GFXDPRSLPVR signal.
Comparator Input for Thermal Protection. THRM connects to the positive input of an internal
comparator. The comparator’s negative input connects to an internal resistive voltage-divider that
accurately sets the THRM threshold to 30% of the VCC voltage. Connect the output of a resistor
and thermistor-divider (between VCC and GND) to THRM with the values selected so the voltage at
THRM falls below 30% of VCC (1.5V when VCC = 5V) at the desired high temperature.
Switching Frequency Setting Input. An external resistor between the input power source and this
pin sets the switching period (tSW = 1/f SW) according to the following equation:
9
TON
t SW = 16.3pF x (RTON + 6.5k)
TON becomes high impedance in shutdown to reduce the input quiescent current. If the TON
current is less than 10µA, the MAX17528 disables the controller, sets the TON open fault latch,
and pulls DL and DH low.
10
11
PWRGD
Open-Drain Power-Good Output. PWRGD is high impedance after output-voltage transitions (except
during power-up and power-down) if FB is in regulation.
During startup, PWRGD is held low.
IMVP-6.5: PWRGD continues to be low while the output is at the boot voltage, and stays low until
5ms (typ) after CLKEN goes low.
GMCH 2009: PWRGD starts monitoring the FB voltage 5ms (typ) after startup (from shutdown or
standby mode) is complete. PWRGD is also held low while in standby mode, and while entering
and exiting standby mode.
PWRGD is forced low during soft-shutdown and while in shutdown. PWRGD is forced high
impedance whenever the slew-rate controller is active (output-voltage transitions), and continues
to be forced high impedance for an additional 20µs after the transition is completed.
The PWRGD upper threshold is blanked during any downward output-voltage transition that
happens when the MAX17528 is in skip mode, and stays blanked until the transition-related
PWRGD blanking period is complete and the output reaches regulation.
A pullup resistor on PWRGD causes additional finite shutdown current.
SHDN
Active-Low Shutdown Control Input. Connect to VCC for normal operation. Connect to ground to put
the controller into the low-power 1µA (max) shutdown state. During startup, the controller ramps up
the output voltage at 1/8 the slew rate set by the TIME resistor to the target voltage defined by the
application circuit:
For IMVP-6.5 (CLKEN pullup to 3.3V with 1.9k), the startup target is the 1.1V boot voltage.
For GMCH 2009 (CLKEN = GND), the startup target is the voltage set by the VID inputs.
During the shutdown transition, the MAX17528 softly ramps down the output voltage at 1/8 the
slew rate set by the TIME resistor. Forcing SHDN to 11V~13V disables UVP, thermal shutdown, and
clears the fault latches.
______________________________________________________________________________________
15
MAX17528
Pin Description (continued)
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
MAX17528
Pin Description (continued)
PIN
NAME
FUNCTION
12
CLKEN
Dual-Function GMCH/IMVP-6.5 Select Input and Active-Low IMVP-6.5 CPU Clock Enable OpenDrain Output. Connect to system 3.3V supply through pullup resistors for proper IMVP-6.5
operation. CLKEN voltage has to be higher than 2.3V before SHDN is pulled high. Connect to GND
to select the Intel GMCH feature set. This active-low logic output indicates when the feedback
voltage is in regulation. The MAX17528 forces CLKEN low during dynamic VID transitions and for
an additional 20µs after the VID transition is completed. CLKEN is the inverse of PWRGD, except
for the 5ms PWRGD startup delay period after CLKEN is pulled low. See the startup timing diagram
(Figure 9). The CLKEN upper threshold is blanked during any downward output-voltage transition
that happens when the MAX17528 are in skip mode, and stays blanked until the transition-related
PWRGD blanking period is complete and the output reaches regulation.
13
GND
14–20
D0–D6
Low-Voltage (1.0V Logic) VID DAC Code Inputs. The D0–D6 inputs do not have internal pullups.
These 1.0V logic inputs are designed to interface directly with the CPU. The output voltage is set
by the VID code indicated by the logic-level voltages on D0–D6 (see Table 2).
The 1111111 code corresponds to standby mode. When this code is detected, the MAX17528
enters standby mode while in forced-PWM mode, and slews to 0V at 1/8 the slew rate set by the
TIME resistor. After slewing to 0V, the IC enters skip mode (DH and DL low). If D6–D0 is changed
from 1111111 to a different code, the MAX17528 exits standby mode (while in skip mode) and
slews the output voltage to the target voltage set by the VID code at 1x the slew rate set by the
TIME resistor. Note that the standby supply current consumed by the MAX17528 is the same as its
quiescent supply current, because no analog blocks are turned off. This is necessary because of
the fast wake-up requirement.
21
PGND
Power Ground. Ground connection for the DL driver. Also used as an input to the MAX17528’s zerocrossing comparator.
22
DL
Low-Side Gate-Driver Output. DL swings from PGND to VDD. DL is forced low after shutdown. DL is
forced low in skip mode after detecting an inductor current zero-crossing.
23
VDD
Supply Voltage Input for the DL Driver. VDD is also the supply voltage used to internally recharge
the BST flying capacitor during the time DL is high. Connect VDD to the 4.5V to 5.5V system supply
voltage. Bypass VDD to PGND with a 1µF or greater ceramic capacitor.
24
BST
Boost Flying Capacitor Connection. BST provides the upper supply rail for the DH high-side gate
driver. An internal switch between VDD and BST charges the flying capacitor while the low-side
MOSFET is on (DL pulled high and LX pulled to ground).
25
LX
Inductor Connection. LX is the internal lower supply rail for the DH high-side gate driver. Also used
as an input to the MAX17528’s zero-crossing comparator.
26
DH
High-Side Gate-Driver Output. DH swings from LX to BST. The controller pulls DH low in shutdown.
PGDIN
IMVP-6.5 Power-Good Logic Input. PGDIN indicates the power status of other system rails used to
power the chipset and CPU VCCP supplies. For the IMVP-6.5 (CLKEN pullup to 3.3V with 1.9k), the
MAX17528 powers up and remains at the boot voltage (VBOOT) as long as PGDIN remains low.
When PGDIN is forced high, the MAX17528 transitions the output to the voltage set by the VID
code, and CLKEN is allowed to go low.
If PGDIN is pulled low at any time, the MAX17528 immediately forces CLKEN high and PWRGD low
and sets the output to the boot voltage. The output remains at the boot voltage until the system
either disables the controller or until PGDIN goes high again.
For GMCH 2009 applications (CLKEN = GND), connect PGDIN to the 5V bias supply.
27
16
Analog Ground
______________________________________________________________________________________
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
PIN
NAME
28
VRHOT
FUNCTION
Active-Low Open-Drain Output of Internal Comparator. VRHOT is pulled low when the voltage at
THRM goes below 1.5V (30% of VCC). VRHOT is high-impedance in shutdown.
Slew-Rate Adjustment Pin. TIME regulates to 2.0V and the load current determines the slew rate of
the internal error-amplifier target. The sum of the resistance between TIME and GND (RTIME)
determines the nominal slew rate:
Slew rate = (12.5mV/µs) x (71.5k/RTIME)
29
TIME
The guaranteed RTIME range is between 35.7k and 178k. This nominal slew rate applies to VID
transitions and to the transition from boot mode to VID. If the VID DAC inputs are clocked, the slew
rate for all other VID transitions is set by the rate at which they are clocked, up to a maximum slew
rate equal to the nominal slew rate defined above.
The startup and shutdown slew rates are always 1/8 of nominal slew rate to minimize surge currents.
If SLOW is high, the slew rate is reduced to 1/2 of nominal.
30
ILIM
Valley Current-Limit Adjustment Input. The valley current-limit threshold voltage at CSP to CSN
equals precisely 1/10 the differential TIME to ILIM voltage over a 0.1V to 0.5V range (10mV to 50mV
current-sense range). The negative current-limit threshold is nominally -125% of the corresponding
valley current-limit threshold. Connect ILIM directly to VCC to set the default current-limit threshold
setting of 22.5mV (typ) nominal.
31
VCC
Controller Supply Voltage. Connect to a 4.5V to 5.5V source. Bypass to GND with 1µF minimum.
32
CCV
Integrator Capacitor Connection. Connect a capacitor (CCCV) from CCV to GND to set the
integration time constant. Choose the capacitor value according to:
16 x (CCCV/Gm(CCV)) x f SW >> 1
where Gm(CCV) = 320µS (max) is the integrator’s transconductance and fSW is the switching
frequency set by the RTON value.
The integrator is internally disabled during any downward output-voltage transition that occurs in
pulse-skipping mode, and remains disabled until the transition blanking period expires and the
output reaches regulation (error amplifier transition detected).
—
EP (GND)
Exposed Pad (Back Side) and Analog Ground. Internally connected to GND. Connect to the ground
plane through a thermally enhanced via.
______________________________________________________________________________________
17
MAX17528
Pin Description (continued)
MAX17528
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
11
ON OFF (VRON)
6
AGND
7
27
SYSTEM I/O
POWER-GOOD
14
15
16
17
18
19
20
VCC
SHDN
AGND
SKIP
VDD
D0
D1
D2
TON
D3
D4
BST
DH
24
PGND
ILIM
RTON
200kΩ
CIN
RPWRGD
10kΩ
12
28
RTHRM
7.87kΩ
8
VCC
CPU
IMON
22
C8
0.022µF
COUT
R12
10kΩ
21
PWR
PWR
5
R11
1.50kΩ
CCSP
OPEN
4
CSENSE
0.47µF
NTC1
10kΩ
B = 4500
AGND
CCSN
OPEN
DCR THERMAL COMPENSATION
AGND
PWRGD
VRHOT
FB
R15
10Ω
RFB
4.53kΩ
1%
CLKEN
3
VCC_SENSE
C9
1000pF
R13
10Ω
REMOTE-SENSE
INPUTS
THRM
CCV
AGND
R4
13.0kΩ
R10
1.00kΩ
NLO
LOAD-LINE ADJUSTMENT:
RFB = RDROOP/(RSENSE x 600µs)
GNDS
1
CORE
OUTPUT
D1
TIME
NTC2
100kΩ
B = 4700
R3
1kΩ
L1
0.36µH
0.8mΩ
25
MAX17528
10
PWR
NHI
3.3V
1.9kΩ
INPUT
7V TO 24V
RBST
0Ω
26
R2
5.90kΩ
CSN
RVRHOT
10kΩ
SWITCHING FREQUENCY (fSW = 1/tSW):
tSW = 16.3pF x (RTON + 6.5kΩ)
CBST
0.1µF
CSP
AGND
PWR
9
D5
D6
DL
29
23
PGDIN
LX
R3
64.9kΩ
5V BIAS
INPUT
C2
1.0µF
C1
1.0µF
SLOW
VALLEY CURRENT LIMIT SET BY TIME TO ILIM
VLIMIT = 0.2V x R2/(R2 + R3)
SLEW RATE SET BY TIME BIAS CURRENT
dV/dt = 12.5mV/µs x 71.5kΩ/(R2 + R3)
30
R1
10Ω
31
GND
IMON
AGND
2
VSS_SENSE
CCCV
100pF
C10
1000pF
32
AGND
EP
VSS_SENSE
AGND
RGND
0Ω
R16
10Ω
AGND
13
AGND
GND
R14
10Ω
REMOTE-SENSE FILTERS
PWR
CATCH RESISTORS
REQUIRED WHEN CPU
NOT POPULATED
PWR
Figure 1. IMVP-6.5 CPU Core Application Circuit
18
______________________________________________________________________________________
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
DESIGN
PARAMETERS
Circuit
AUBURNDALE
IMVP-6.5 ULV
AUBURNDALE
IMVP-6.5 ULV
AUBURNDALE
RENDER GMCH SV
AUBURNDALE
RENDER GMCH ULV
Figure 1
Figure 1
Figure 2
Figure 2
7V to 20V
5V
7V to 20V
7V to 20V
Maximum Load Current
(TDC Current)
20A
(15A)
20A
(15A)
15A
(10A)
7A
(5A)
Transient Load Current
14A
(10A/µs)
14A
(10A/µs)
12A
(10A/µs)
5A
(10A/µs)
3mV/A
3mV/A
7mV/A
7mV/A
20A
20A
20A
20A
200k
(fSW = 300kHz)
120k
(fSW = 500kHz)
200k
(fSW = 300kHz)
200k
(fSW = 300kHz)
NEC/TOKIN
MPC1055LR36
0.36µH, 32A, 0.8m
NEC/TOKIN
MPC1055LR36
0.36µH, 32A, 0.8m
NEC/TOKIN
MPCG0740LR42
0.42µH, 20A, 1.55m
NEC/TOKIN
MPC1040LR88C
0.88µH, 24A, 2.3m
Input-Voltage Range
Load Line
POC Setting
COMPONENTS
TON Resistance (RTON)
Inductance (L)
High-Side MOSFET (NH)
Siliconix
Siliconix
1x Si4386DY
1x Si4386DY
7.8m/9.5m (typ/max) 7.8m/9.5m (typ/max)
Siliconix
1x Si4386DY
7.8m/9.5m (typ/max)
Siliconix
1x Si4386DY
7.8m/9.5m (typ/max)
Low-Side MOSFET (NL)
Siliconix
Siliconix
2x Si4642DY
2x Si4642DY
3.9m/4.7m (typ/max) 3.9m/4.7m (typ/max)
Siliconix
1x Si4642DY
3.9m/4.7m (typ/max)
Siliconix
1x Si4642DY
3.9m/4.7m (typ/max)
Output Capacitors
(COUT)
4x 330µF, 6m, 2.5V
Panasonic
EEFSX0D0D331XR
32x 10µF, 6V ceramic
(0805)
4x 330µF, 6m, 2.5V
Panasonic
EEFSX0D0D331XR
32x 10µF, 6V ceramic
(0805)
1x 470µF, 6m, 2.5V
SANYO 2R5TPD470M6L
10x 10µF, 6V ceramic
(0805)
1x 220µF, 7m, 2V
SANYO 2TPF220M7L
10x 10µF, 6V ceramic
(0805)
Input Capacitors (CIN)
4x 10µF, 25V ceramic
(1210)
6x 10µF, 6V ceramic
(0805)
2x 10µF, 25V ceramic
(1210)
2x 10µF, 25V ceramic
(1210)
TIME-ILIM Resistance
(R1)
5.90k
5.90k
6.65k
6.65k
ILIM-GND Resistance
(R2)
64.9k
64.9k
64.9k
64.9k
FB Resistance (RFB)
4.53k
4.53k
10.0k
5.62k
IMON Resistance (R4)
13.0k
13.0k
7.68k
4.42k
LX-CSP Resistance (R5)
1.00k
1.00k
1.50k
0.806k
CSP-CSN Series
Resistance (R6)
1.50k
1.50k
1.50k
1.20k
Parallel NTC
Resistance (R7)
10.0k
10.0k
4.02k
15.0k
10k NTC B = 3380
TDK NTCG163JH103F
10k NTC B = 3380
TDK NTCG163JH103F
10k NTC B = 3380
TDK NTCG163JH103F
10k NTC B = 3380
TDK NTCG163JH103F
0.47µF, 6V ceramic
(0805)
0.47µF, 6V ceramic
(0805)
0.22µF, 6V ceramic
(0805)
0.47µF, 6V ceramic
(0805)
DCR Sense NTC (NTC1)
DCR Sense
Capacitance (CSENSE)
______________________________________________________________________________________
19
MAX17528
Table 1. IMVP-6.5 Component Selection
MAX17528
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
11
ON OFF (VRON)
6
7
27
14
15
16
17
18
19
20
VID INPUTS
VCC
SHDN
SLOW
AGND
SKIP
VDD
D0
D1
D2
TON
D3
D4
D5
D6
BST
DH
PGND
ILIM
TIME
CSP
R2
6.65kΩ
AGND
CSN
3.3V
RVRHOT
10kΩ
RPWRGD
10kΩ
12
28
GFX
IMON
C8
0.022µF
8
CIN
RBST
0Ω
26
PWR
NHI
L1
0.42µH
1.55mΩ
25
GFX
OUTPUT
D1
22
R10
1.50kΩ
NLO
COUT
R12
4.02kΩ
21
PWR
PWR
5
R11
1.50kΩ
CCSP
OPEN
4
CSENSE
0.22µF
NTC1
10kΩ
B = 4500
AGND
CCSN
OPEN
DCR THERMAL COMPENSATION
AGND
CLKEN
VRHOT
3
VCCGFX_SENSE
R13
10Ω
REMOTE-SENSE
INPUTS
THRM
GNDS
AGND
1
R15
10Ω
RFB
10.0kΩ
1%
C9
1000pF
CCV
R4
7.68kΩ
INPUT
7V TO 24V
LOAD-LINE ADJUSTMENT:
RFB = RDROOP/(RSENSE x 600µs)
NTC2
100kΩ
B = 4700
R3
6.2kΩ
24
PWRGD
FB
VCC
RTON
200kΩ
9
MAX17528
10
RTHRM
7.87kΩ
PWR
SWITCHING FREQUENCY (fSW = 1/tSW):
tSW = 16.3pF x (RTON + 6.5kΩ)
CBST
0.1µF
DL
29
23
PGDIN
LX
30
5V BIAS
INPUT
C2
1.0µF
C1
1.0µF
VALLEY CURRENT LIMIT SET BY TIME TO ILIM
VLIMIT = 0.2V x R2/(R2 + R3)
SLEW RATE SET BY TIME BIAS CURRENT
dV/dt = 12.5mV/µs x 71.5kΩ/(R2 + R3)
R3
64.9kΩ
R1
10Ω
31
GND
IMON
AGND
2
VSSGFX_SENSE
CCCV
100pF
C10
1000pF
32
AGND
EP
VSSGFX_SENSE
AGND
RGND
0Ω
R16
10Ω
AGND
13
AGND
GND
R14
10Ω
REMOTE-SENSE FILTERS
PWR
CATCH RESISTORS
REQUIRED WHEN CPU
NOT POPULATED
PWR
Figure 2. GMCH (Render Core) Application Circuit
20
______________________________________________________________________________________
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
Free-Running, Constant On-Time
Controllers with Input Feed-Forward
The Quick-PWM control architecture is a pseudo-fixedfrequency, constant-on-time, current-mode regulator
with voltage feed-forward (Figure 3). This architecture
relies on the output filter capacitor’s ESR and the load
regulation to provide the proper current-mode compensation, so the resulting feedback ripple voltage provides
the PWM ramp signal. The control algorithm is simple:
the high-side switch on-time is determined solely by a
one-shot whose period is inversely proportional to input
voltage, and directly proportional to the feedback voltage (see the On-Time One-Shot section). Another oneshot sets a minimum off-time. The on-time one-shot
triggers when the error comparator goes low (the feedback voltage drops below the target voltage), the
inductor current is below the valley current-limit threshold, and the minimum off-time one-shot times out.
+5V Bias Supply (VCC and VDD)
The Quick-PWM controller requires an external +5V bias
supply in addition to the battery. Typically, this +5V bias
supply is the notebook’s 95%-efficient, +5V system supply. Keeping the bias supply external to the IC improves
efficiency and eliminates the cost associated with the
+5V linear regulator that would otherwise be needed to
supply the PWM circuit and gate drivers. If stand-alone
capability is needed, the +5V bias supply can be generated with an external linear regulator.
The +5V bias supply must provide V CC (PWM controller) and VDD (gate-drive power), so the maximum
current drawn is:
(
IBIAS = ICC + fSW QG(LOW) + QG(HIGH)
)
where ICC is provided in the Electrical Characteristics
table, fSW is the switching frequency, and QG(LOW) and
Q G(HIGH) are the MOSFET data sheet’s total gatecharge specification limits at VGS = 5V.
VIN and VDD can be connected if the input power source
is a fixed +4.5V to +5.5V supply. If the +5V bias supply is
powered up prior to the battery supply, the enable signal
(SHDN going from low to high) must be delayed until the
battery voltage is present to ensure startup.
Switching Frequency (TON)
Connect a resistor (RTON) between TON and VIN to set
the switching period (tSW = 1/fSW):
A 96.75kΩ to 303.25kΩ corresponds to switching periods of 1.67µs (600kHz) to 5µs (200kHz), respectively.
High-frequency (over 500kHz) operation optimizes the
application for the smallest component size, trading off
efficiency due to higher switching losses. This may be
acceptable in ultra-portable devices where the load
currents are lower and the controller is powered from a
lower voltage supply. Low-frequency (under 300kHz)
operation offers the best overall efficiency at the
expense of component size and board space.
TON Open-Circuit Fault Protection
The TON input includes open-circuit protection to avoid
long, uncontrolled on-times that could result in an overvoltage condition on the output. The MAX17528 detects
an open-circuit fault if the TON current drops below
10µA for any reason—the TON resistor (R TON ) is
unpopulated, a high resistance value is used, the input
voltage is low, etc. Under these conditions, the
MAX17528 stops switching (DH and DL pulled low) and
immediately sets the fault latch. Toggle SHDN or cycle
the VCC power supply below 0.5V to clear the fault latch
and reactivate the controller.
On-Time One-Shot
The core contains a fast, low-jitter, adjustable one-shot
that sets the high-side MOSFET’s on-time. The one-shot
varies the on-time in response to the input and feedback
voltages. The main high-side switch on-time is inversely
proportional to the input voltage as measured by the RTON
input, and proportional to the feedback voltage (VFB):
⎛V ⎞
tON = tSW ⎜ FB ⎟
⎝ VIN ⎠
where the switching period (tSW = 1/fSW) is set by the
resistor between VIN and TON.
This algorithm results in a nearly constant switching frequency despite the lack of a fixed-frequency clock
generator. The benefits of a constant switching frequency are twofold: first, the frequency can be selected to avoid noise-sensitive regions, such as the 455kHz
IF band; second, the inductor ripple-current operating
point remains relatively constant, resulting in easy
design methodology and predictable output voltage
ripple. The on-time one-shots have good accuracy at
the operating points specified in the Electrical
Characteristics table. On-times at operating points far
removed from the conditions specified in the Electrical
Characteristics table can vary over a wider range.
tSW = 16.3pF x (RTON + 6.5kΩ)
______________________________________________________________________________________
21
MAX17528
Detailed Description
MAX17528
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
CSP
CURRENT
MONITOR
10x
CSN
ILIM
IMON
Gm(IMON)
5mS
MINIMUM
OFF-TIME
TIME
Q
TRIG
MAX17528
ONE-SHOT
FB
ON-TIME
TON
ONE-SHOT
TRIG
Q
VCC
REF
(2.0V)
BST
R
Q
DH
S
GND
LX
S
D0–D6
DAC
PGDIN
Q
PGND
LX
1mV
CURRENT
SCALING
SHDN
R
VDD
TARGET
DL
PGND
FAULT
SKIP
REF
500kΩ
Gm(CCV)
160µS
MODE
CONTROL
TARGET
+ 200mV
R
CLKEN
TARGET
- 300mV
5ms
STARTUP
DELAY
CSP
GNDS
Gm(FB)
600µS
CSN
SLOW
60µs
STARTUP
DELAY
REF
FB
SKIP
BLANK
SLEW_RATE
CCV
TARGET
+ 300mV
PWRGD
FAULT
VRHOT
Gm(GNDS)
TARGET
- 400mV
0.3 x VCC
THRM
Figure 3. Functional Diagram
22
______________________________________________________________________________________
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
fSW =
(VOUT + VDIS )
t ON (VIN + VDIS − VCHG )
where VDIS is the sum of the parasitic voltage drops in
the inductor discharge path, including synchronous rectifier, inductor, and PCB resistances; VCHG is the sum of
the parasitic voltage drops in the inductor charge path,
including high-side switch, inductor, and PCB resistances; and tON is the on-time as determined above.
Current Sense
The output current is differentially sensed by the highimpedance current-sense inputs (CSP and CSN). Lowoffset amplifiers are used for voltage-positioning gain,
current-limit protection, and current monitoring. Sensing
the current at the output offers advantages, including less
noise sensitivity and the flexibility to use either a currentsense resistor or the DC resistance of the power inductor.
Using the DC resistance (RDCR) of the inductor allows
higher efficiency. In this configuration, the initial tolerance and temperature coefficient of the inductor’s DCR
must be accounted for in the output-voltage drooperror budget and current monitor. This current-sense
method uses an RC filtering network to extract the current information from the inductor (see Figure 4). The
resistive divider used should provide a current-sense
resistance (RCS) low enough to meet the current-limit
requirements (RCS x IOUT(MAX) < 50mV), and the time
constant of the RC network should match the inductor’s
time constant (L/RDCR):
⎛ R2 ⎞
RCS = ⎜
⎟R
⎝ R1+ R2 ⎠ DCR
and:
RDCR =
L
CEQ
1⎤
⎡1
⎢ R1 + R2 ⎥
⎣
⎦
where RCS is the required current-sense resistance, and
RDCR is the inductor’s series DC resistance. Use the
worst-case inductance and RDCR values provided by
the inductor manufacturer, adding some margin for the
inductance drop over temperature and load. To minimize the current-sense error due to the current-sense
inputs’ bias current (ICSP), choose R1 || R2 to be less
than 2kΩ and use the above equation to determine the
sense capacitance (CEQ). Choose capacitors with 5%
tolerance and resistors with 1% tolerance specifications.
Temperature compensation is recommended for this
current-sense method. See the Voltage Positioning and
Loop Compensation section for detailed information.
When using a current-sense resistor for accurate outputvoltage positioning, the circuit requires a differential RC
filter to eliminate the AC voltage step caused by the
equivalent series inductance (LESL) of the current-sense
resistor (see Figure 4). The ESL-induced voltage step
does not affect the average current-sense voltage, but
results in a significant peak current-sense voltage error
that results in unwanted offsets in the regulation voltage
and results in early current-limit detection. Similar to the
inductor DCR sensing method, the RC filter’s time constant should match the L/R time constant formed by the
current-sense resistor’s parasitic inductance:
LESL
= CEQR1
RSENSE
where LESL is the equivalent series inductance of the
current-sense resistor, R SENSE is the current-sense
resistance value, CEQ and R1 are the time-constant
matching components.
______________________________________________________________________________________
23
MAX17528
On-times translate only roughly to switching frequencies. The on-times guaranteed in the Electrical
Characteristics table are influenced by switching
delays in the external high-side MOSFET. Resistive
losses, including the inductor, both MOSFETs, and
printed-circuit board (PCB) copper losses in the output
and ground tend to raise the switching frequency as
the load current increases. Under light-load conditions,
the dead-time effect increases the effective on-time,
reducing the switching frequency. It occurs only during
forced-PWM operation and dynamic output-voltage
transitions when the inductor current reverses at lightor negative-load currents. With reversed inductor current, the inductor’s EMF causes LX to go high earlier
than normal, extending the on-time by a period equal to
the DH-rising dead time. For loads above the critical
conduction point, where the dead-time effect is no
longer a factor, the actual switching frequency is:
MAX17528
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
INPUT (VIN)
DH
NH
CIN
SENSE RESISTOR
L
LESL
RSENSE
LX
DL
MAX17528
NL
COUT
DL
CEQR1 =
PGND
R1
LSENSE
RSENSE
CEQ
CSP
CSN
A) OUTPUT SERIES RESISTOR SENSING
INPUT (VIN)
DH
NH
CIN
INDUCTOR
L
DCR
LX
DL
NL
DL
R1
R2
MAX17528 PGND
CSP
CSN
B) LOSSLESS INDUCTOR SENSING
CEQ
COUT
RCS =
(R1R2+ R2) R
RDCR =
DCR
L
CEQ
[
1
R1
+
1
R2
]
FOR THERMAL COMPENSATION:
R2 SHOULD CONSIST OF AN NTC RESISTOR IN
SERIES WITH A STANDARD THIN-FILM RESISTOR.
Figure 4. Current-Sense Methods
Current Limit
The current-limit circuit employs a “valley” current-sensing algorithm that uses a current-sense element (see
Figure 4) between the current-sense inputs (CSP to
CSN) to detect the inductor current. If the differential
current-sense voltage exceeds the current-limit threshold, the PWM controller does not initiate a new cycle
until the inductor current drops below the valley currentlimit threshold. Since only the valley current level is
actively limited, the actual peak inductor current
exceeds the valley current-limit threshold by an amount
equal to the inductor ripple current. Therefore, the exact
current-limit characteristic and maximum load capability
are a function of the current-sense impedance, inductor
value, and battery voltage. When combined with the
undervoltage protection circuit, this current-limit method
is effective in almost every circumstance.
24
The positive valley current-limit threshold voltage at
CSP to CSN equals precisely 1/10 of the differential
TIME to ILIM voltage over a 0.1V to 0.5V range (10mV
to 50mV current-sense range). Connect ILIM directly to
VCC to set the default current-limit threshold setting of
22.5mV nominal.
The negative current-limit threshold (forced-PWM mode
only) is nominally -125% of the corresponding valley
current-limit threshold. When the inductor current drops
below the negative current limit, the controller immediately activates an on-time pulse—DL turns off, and DH
turns on—allowing the inductor current to remain above
the negative current threshold.
Carefully observe the PCB layout guidelines to ensure
that noise and DC errors do not corrupt the current-sense
signals seen by the current-sense inputs (CSP, CSN).
______________________________________________________________________________________
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
VTARGET = VFB = VDAC + VGNDS
where VDAC is the selected VID voltage. On startup,
IMVP-6.5 (CLKEN pullup to 3.3V with 1.9kΩ) applications slew the target voltage from ground to the preset
1.1V boot voltage and GMCH (CLKEN = GND) applications slew the target voltage directly to the VID-selected
DAC target.
Voltage-Positioning Amplifier
(Steady-State Droop)
The MAX17528 includes a transconductance amplifier
for adding gain to the voltage-positioning sense path.
The amplifier’s input is generated by the differential
current-sense inputs that sense the inductor current by
measuring the voltage across either current-sense
resistors or the inductor’s DCR. The amplifier’s output
connects directly to the regulator’s voltage-positioned
feedback input (FB), so the resistance between FB and
the output-voltage sense point determines the voltagepositioning gain:
VOUT = VTARGET − RFBIFB
where the target voltage (VTARGET = VFB) is defined by
the selected VID code (Table 3 for IMVP6 or Table 4 for
GMCH), and the FB amplifier’s output current (IFB) is
determined by the sum of the current-sense voltages:
IFB = Gm(FB) (VCSP − VCSN )
where G m(FB) is typically 600µS as defined in the
Electrical Characteristics table.
Differential Remote Sense
The MAX17528 includes differential, remote-sense
inputs to eliminate the effects of voltage drops along the
PCB traces and through the processor’s power pins.
The feedback-sense node connects to the voltage-positioning resistor (RFB). The ground-sense (GNDS) input
connects to an amplifier that adds an offset directly to
the feedback voltage, effectively adjusting the output
voltage to counteract the voltage drop in the ground
path. Connect the voltage-positioning resistor (RFB) and
ground-sense (GNDS) input directly to the processor’s
remote-sense outputs as shown in Figures 1 and 2.
Integrator Amplifier
An integrator amplifier forces the DC average of the FB
voltage to equal the target voltage. This transconductance amplifier integrates the feedback voltage and
provides a fine adjustment to the regulation voltage
(Figure 3), allowing accurate DC output-voltage regulation regardless of the output ripple voltage. The integrator amplifier has the ability to shift the output voltage by
±50mV (typ). The integration time constant can be set
easily with an external compensation capacitor
between CCV and analog ground, with the minimum
recommended CCV capacitor value determined by:
CCCV >> Gm(CCV)/(16π x fSW)
where G m(CCV) = 320µS (max) is the integrator’s
transconductance and fSW is the switching frequency
set by the RTON resistance.
The MAX17528 disables the integrator by connecting
the amplifier inputs together at the beginning of all
downward VID transitions done in pulse-skipping mode
(SKIP = high). The integrator remains disabled until
20µs after the transition is completed (the internal target settles) and the output is in regulation (edge detected on the error comparator).
DAC Inputs (D0–D6)
The digital-to-analog converter (DAC) programs the
output voltage using the D0–D6 inputs. D0–D6 are lowvoltage (1.0V) logic inputs designed to interface directly with the CPU. Do not leave D0–D6 unconnected.
Changing D0–D6 initiates a transition to a new outputvoltage level. Change D0–D6 together, avoiding
greater than 20ns skew between bits. Otherwise, incorrect DAC readings can cause a partial transition to the
wrong voltage level followed by the intended transition
to the correct voltage level, lengthening the overall transition time. The available DAC codes and resulting output voltages are compatible with the Intel IMVP-6.5/
GMCH specifications (Table 2).
______________________________________________________________________________________
25
MAX17528
Feedback
The nominal no-load output voltage (V TARGET ) is
defined by the VID-selected DAC voltage (see Table 2)
plus the remote ground-sense adjustment (VGNDS) as
defined in the following equation:
MAX17528
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
Table 2. IMVP-6.5 Output Voltage VID DAC Codes
D6
D5
D4
D3
D2
D1
D0
IMVP-6.5
OUTPUT
VOLTAGE
(V)
0
0
0
0
0
0
0
1.5000
1
0
0
0
0
0
0
0.7000
0
0
0
0
0
0
1
1.4875
1
0
0
0
0
0
1
0.6875
0
0
0
0
0
1
0
1.4750
1
0
0
0
0
1
0
0.6750
0
0
0
0
0
1
1
1.4625
1
0
0
0
0
1
1
0.6625
0
0
0
0
1
0
0
1.4500
1
0
0
0
1
0
0
0.6500
0
0
0
0
1
0
1
1.4375
1
0
0
0
1
0
1
0.6375
0
0
0
0
1
1
0
1.4250
1
0
0
0
1
1
0
0.6250
0
0
0
0
1
1
1
1.4125
1
0
0
0
1
1
1
0.6125
0
0
0
1
0
0
0
1.4000
1
0
0
1
0
0
0
0.6000
0
0
0
1
0
0
1
1.3875
1
0
0
1
0
0
1
0.5875
0
0
0
1
0
1
0
1.3750
1
0
0
1
0
1
0
0.5750
0
0
0
1
0
1
1
1.3625
1
0
0
1
0
1
1
0.5625
0
0
0
1
1
0
0
1.3500
1
0
0
1
1
0
0
0.5500
0
0
0
1
1
0
1
1.3375
1
0
0
1
1
0
1
0.5375
0
0
0
1
1
1
0
1.3250
1
0
0
1
1
1
0
0.5250
0
0
0
1
1
1
1
1.3125
1
0
0
1
1
1
1
0.5125
0
0
1
0
0
0
0
1.3000
1
0
1
0
0
0
0
0.5000
0
0
1
0
0
0
1
1.2875
1
0
1
0
0
0
1
0.4875
0
0
1
0
0
1
0
1.2750
1
0
1
0
0
1
0
0.4750
0
0
1
0
0
1
1
1.2625
1
0
1
0
0
1
1
0.4625
0
0
1
0
1
0
0
1.2500
1
0
1
0
1
0
0
0.4500
0
0
1
0
1
0
1
1.2375
1
0
1
0
1
0
1
0.4375
0
0
1
0
1
1
0
1.2250
1
0
1
0
1
1
0
0.4250
0
0
1
0
1
1
1
1.2125
1
0
1
0
1
1
1
0.4125
0
0
1
1
0
0
0
1.2000
1
0
1
1
0
0
0
0.4000
0
0
1
1
0
0
1
1.1875
1
0
1
1
0
0
1
0.3875
0
0
1
1
0
1
0
1.1750
1
0
1
1
0
1
0
0.3750
0
0
1
1
0
1
1
1.1625
1
0
1
1
0
1
1
0.3625
0
0
1
1
1
0
0
1.1500
1
0
1
1
1
0
0
0.3500
0
0
1
1
1
0
1
1.1375
1
0
1
1
1
0
1
0.3375
0
0
1
1
1
1
0
1.1250
1
0
1
1
1
1
0
0.3250
0
0
1
1
1
1
1
1.1125
1
0
1
1
1
1
1
0.3125
0
1
0
0
0
0
0
1.1000
1
1
0
0
0
0
0
0.3000
0
1
0
0
0
0
1
1.0875
1
1
0
0
0
0
1
0.2875
0
1
0
0
0
1
0
1.0750
1
1
0
0
0
1
0
0.2750
0
1
0
0
0
1
1
1.0625
1
1
0
0
0
1
1
0.2625
0
1
0
0
1
0
0
1.0500
1
1
0
0
1
0
0
0.2500
0
1
0
0
1
0
1
1.0375
1
1
0
0
1
0
1
0.2375
26
D6
D5
D4
D3
D2
D1
D0
IMVP-6.5
OUTPUT
VOLTAGE
(V)
______________________________________________________________________________________
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
D6
D5
D4
D3
D2
D1
D0
IMVP-6.5
OUTPUT
VOLTAGE
(V)
0
1
0
0
1
1
0
1.0250
1
1
0
0
1
1
0
0.2250
0
1
0
0
1
1
1
1.0125
1
1
0
0
1
1
1
0.2125
0
1
0
1
0
0
0
1.0000
1
1
0
1
0
0
0
0.2000
0
1
0
1
0
0
1
0.9875
1
1
0
1
0
0
1
0.1875
0
1
0
1
0
1
0
0.9750
1
1
0
1
0
1
0
0.1750
0
1
0
1
0
1
1
0.9625
1
1
0
1
0
1
1
0.1625
0
1
0
1
1
0
0
0.9500
1
1
0
1
1
0
0
0.1500
0
1
0
1
1
0
1
0.9375
1
1
0
1
1
0
1
0.1375
0
1
0
1
1
1
0
0.9250
1
1
0
1
1
1
0
0.1250
0
1
0
1
1
1
1
0.9125
1
1
0
1
1
1
1
0.1125
0
1
1
0
0
0
0
0.9000
1
1
1
0
0
0
0
0.1000
0
1
1
0
0
0
1
0.8875
1
1
1
0
0
0
1
0.0875
0
1
1
0
0
1
0
0.8750
1
1
1
0
0
1
0
0.0750
0
1
1
0
0
1
1
0.8625
1
1
1
0
0
1
1
0.0625
0
1
1
0
1
0
0
0.8500
1
1
1
0
1
0
0
0.0500
0
1
1
0
1
0
1
0.8375
1
1
1
0
1
0
1
0.0375
0
1
1
0
1
1
0
0.8250
1
1
1
0
1
1
0
0.0250
0
1
1
0
1
1
1
0.8125
1
1
1
0
1
1
1
0.0125
0
1
1
1
0
0
0
0.8000
1
1
1
1
0
0
0
0
0
1
1
1
0
0
1
0.7875
1
1
1
1
0
0
1
0
0
1
1
1
0
1
0
0.7750
1
1
1
1
0
1
0
0
0
1
1
1
0
1
1
0.7625
1
1
1
1
0
1
1
0
0
1
1
1
1
0
0
0.7500
1
1
1
1
1
0
0
0
0
1
1
1
1
0
1
0.7375
1
1
1
1
1
0
1
0
0
1
1
1
1
1
0
0.7250
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
0.7125
1
1
1
1
1
1
1
0
Output-Voltage Transition Timing
The MAX17528 perform mode transitions in a controlled
manner, automatically minimizing input surge currents.
This feature allows the circuit designer to achieve nearly
ideal transitions, guaranteeing just-in-time arrival at the
new output voltage level with the lowest possible peak
currents for a given output capacitance.
At the beginning of an output-voltage transition, the
MAX17528 blanks both PWRGD thresholds, preventing
the PWRGD open-drain output and the CLKEN opendrain output from changing states during the transition.
The controllers reenable the lower PWRGD threshold
D6
D5
D4
D3
D2
D1
D0
IMVP-6.5
OUTPUT
VOLTAGE
(V)
approximately 20µs after the slew-rate controller reaches the target output voltage. The controllers reenable
the upper PWRGD threshold 20µs after the slew-rate
controllers reach the target output voltage only for
upward VID transitions. For downward VID transitions,
the MAX17528 must also detect an error amplifier transition (feedback drops below the new target threshold)
before reenabling the upper PWRGD transition to avoid
false PWRGD errors under pulse-skipping conditions.
The slew rate (set by resistor RTIME) must be set fast
enough to ensure that the transition can be completed
within the maximum allotted time.
______________________________________________________________________________________
27
MAX17528
Table 2. IMVP-6.5 Output Voltage VID DAC Codes (continued)
MAX17528
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
The MAX17528 automatically controls the current to the
minimum level required to complete the transition in the
calculated time. The slew-rate controller uses an internal capacitor and current-source programmed by
RTIME to transition the output voltage. The total transition time depends on RTIME, the voltage difference,
and the accuracy of the slew-rate controller (CSLEW
accuracy). The slew rate is not dependent on the total
output capacitance, as long as the surge current is less
than the current limit. For all dynamic VID transitions,
the transition time (tTRAN) is given by:
t TRAN =
VNEW − VOLD
( dVTARGET / dt )
where dVTARGET/dt = 12.5mV/µs x 71.5kΩ/RTIME is the
slew rate, V OLD is the original output voltage, and
VNEW is the new target voltage. See TIME Slew-Rate
Accuracy in the Electrical Characteristics table for
slew-rate limits. For soft-start and shutdown, the controller automatically reduces the slew rate to 1/8.
The output voltage tracks the slewed target voltage,
making the transitions relatively smooth. Excluding the
load current, the average inductor current required to
make an output voltage transition is:
where dVTARGET/dt is the required slew rate and COUT
is the total output capacitance.
IMVP-6.5 Low-Power Sleep Transition
The IMVP-6.5 CPU enters a low-power state to conserve power (Figure 5). The processor enters this state
by initially setting the core voltage to the LFM voltage
level (no LSB stepping). Upon reaching the LFM voltage level, the processor asserts DPRLPVR, which is
connected to SKIP as shown in Figure 1, signaling that
a very low current state has been entered. However,
the processor can still lower the core voltage by LSB
increments to further reduce power consumption under
this very low-power sleep state. The processor exits the
sleep state by pulling DPRSLVPR low and ramping up
the core voltage by LSB increments. During all VID
transitions, the MAX17528 blanks PWRGD (forced high
impedance) and CLKEN (forced low) until 20µs after
the internal target (which moves at the slew rate set by
RTIME) reaches the selected VID code.
IL ≅ COUT × (dVTARGET / dt)
ACTIVE VID
HFM VID
CPU CORE
VOLTAGE
LFM VID
VID (D0–D6)
LFM VID
POSSIBLE VID CHANGE
HFM VID
DPRSLPVR
PULSE SKIPPING
1-PHASE FORCED PWM
PWRGD
BLANK HIGH IMPEDANCE
BLANK HIGH IMPEDANCE
CLKEN
BLANK LOW
BLANK LOW
DH
tBLANK
20µs typ
tBLANK
20µs typ
NOTE: DPRSLPVR = SKIP.
Figure 5. IMVP-6.5 Sleep Transition
28
______________________________________________________________________________________
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
The exit transition begins by pulling GFXDPRSLPVR
low, followed by LSB VID steps every 2.5µs until the
active VID target is reached (Figure 6).
Fast GMCH sleep exit: When quickly exiting from the
sleep state, the system immediately changes the VID
code to the active VID code (no LSB stepping) and
keeps GFXDPRSLPVR asserted to select the fast
10mV/µs slew rate. Upon completion of the transition,
the system pulls GFXDPRSLPVR low to signal the
beginning of active state operation.
During all VID transitions, the MAX17528 blanks
PWRGD (forced high impedance) until 20µs after the
internal target (which moves at the slew rate set by
RTIME) reaches the selected VID code.
ACTIVE VID
ACTIVE VID
CPU CORE
VOLTAGE
DPRSLP VID
VID (D0–D6)
DEEPER SLEEP VID
GFXDPRSLPVR
PULSE SKIPPING
PWRGD
BLANK HIGH IMPEDANCE
1-PHASE FORCED PWM
BLANK HIGH IMPEDANCE
DH
tBLANK
20µs typ
tBLANK
20µs typ
NOTE: GFXDPRSLPVR = SKIP = SLOW.
Figure 6. Slow Render GMCH Sleep Transition
______________________________________________________________________________________
29
MAX17528
GMCH Sleep Transition
For GMCH applications (CLKEN = GND), the system
enters the sleep state by stepping the VID code down to
the deeper sleep VID code. During these VID transitions,
the MAX17528 blanks PWRGD (forced high impedance)
until 20µs after the last VID transition is completed. Upon
reaching the low-voltage code, the system asserts
GFXDPRSLPVR, which is connected to the MAX17528
SKIP and SLOW pins as shown in Figure 2, allowing the
voltage regulator to enter a pulse-skipping mode (for
best light-load efficiency).
Slow GMCH sleep exit: To avoid audible noise, the system reduces the exit slew rate to minimize surge currents from the input capacitors to the output capacitors.
MAX17528
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
Forced-PWM Operation (Normal Mode)
Light-Load Pulse-Skipping Operation
During soft-shutdown and normal operation—when the
CPU is actively running (SKIP = low, Table 3), the
MAX17528 operates with the low-noise, forced-PWM
control scheme. Forced-PWM operation disables the
zero-crossing comparator, forcing the low-side gatedrive waveforms to constantly be the complement of
the high-side gate-drive waveforms. This keeps the
switching frequency constant and allows the inductor
current to reverse under light loads, providing fast,
accurate negative output-voltage transitions by quickly
discharging the output capacitors.
Forced-PWM operation comes at a cost: the no-load
+5V bias supply current remains between 10mA to
50mA, depending on the external MOSFETs and switching frequency. To maintain high efficiency under lightload conditions, the processor can switch the controller
to a low-power pulse-skipping control scheme after
entering suspend mode. The MAX17528 automatically
uses pulse-skipping operation during soft-start, regardless of the SKIP configuration.
During soft-start and sleep states—SKIP is pulled
high—the MAX17528 operates in pulse-skipping mode.
The pulse-skipping mode enables the driver’s zerocrossing comparator, so the controller pulls DL low
when the low-side MOSFET voltage drop (LX to GND
voltage) detects “zero” inductor current. This keeps the
inductor from sinking current and discharging the output
capacitors and forces the controller to skip pulses under
light-load conditions to avoid overcharging the output.
Upon entering pulse-skipping operation, the controller
temporarily blanks the upper PWRGD and CLKEN
thresholds, when the transition to pulse-skipping operation coincides with a VID code change. Once the error
amplifier detects that the output voltage is in regulation,
the upper PWRGD and upper CLKEN, resume tracking
the selected VID DAC code. The MAX17528 automatically uses forced-PWM operation during soft-shutdown,
regardless of the SKIP configuration.
10mV/µs
ACTIVE VID
ACTIVE VID
CPU CORE
VOLTAGE
DPRSLP VID
VID (D0–D6)
DEEPER SLEEP VID
GFXDPRSLPVR
PULSE SKIPPING
PWRGD
BLANK HIGH IMPEDANCE
1-PHASE FORCED PWM
BLANK HIGH IMPEDANCE
DH
tBLANK
20µs typ
tBLANK
20µs typ
NOTE: GFXDPRSLPVR = SKIP = SLOW.
Figure 7. Fast Render GMCH Sleep Transition
30
______________________________________________________________________________________
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
⎛t V
⎞ ⎛ V − VOUT ⎞
ILOAD(SKIP) = ⎜ SW OUT ⎟ ⎜ IN
⎟⎠
⎝
⎠⎝
L
VIN
The switching waveforms might appear noisy and asynchronous when light loading activates pulse-skipping
operation, but this is a normal operating condition that
results in high light-load efficiency. Trade-offs between
PFM noise and light-load efficiency are made by
varying the inductor value. Generally, low inductor values produce a broader efficiency vs. load curve, while
higher values result in higher full-load efficiency
(assuming that the coil resistance remains fixed) and
less output voltage ripple. Penalties for using higher
INDUCTOR CURRENT
∆i VBATT - VOUT
=
∆t
L
IPEAK
ILOAD = IPEAK/2
0
ON-TIME
TIME
inductor values include larger physical size and
degraded load-transient response, especially at low
input-voltage levels.
Power-Up Sequence (POR, UVLO)
The MAX17528 is enabled when SHDN is driven high
(Figures 9 and 10). The internal reference powers up
first, followed by the analog control circuitry. Roughly
50µs after the analog control circuitry powers up, the
PWM controller is enabled and begins the soft-start
sequence.
Power-on reset (POR) occurs when VCC rises above
approximately 2V, resetting the fault latch and preparing the controller for operation. The VCC UVLO circuitry
inhibits switching until VCC rises above 4.25V. The controller powers up the reference once the system
enables the controller, VCC is above 4.25V, and SHDN
is driven high. The soft-start sequence ramps the output voltage up to the target voltage—either the 1.1V
boot voltage for IMVP-6.5 (CLKEN pullup to 3.3V with
1.9kΩ) or the selected VID voltage for GMCH (CLKEN
= GND)—at 1/8 the nominal slew rate set by RTIME:
t TRAN(START) =
8VSTART
(dVTARGET / dt)
where dVTARGET/dt = 12.5mV/µs x 71.5kΩ/RTIME is the
nominal slew rate. The soft-start circuitry does not use a
variable current limit, so full output current is available
immediately. The MAX17528 automatically uses pulseskipping mode during soft-start and uses forced-PWM
mode during soft-shutdown, regardless of the SKIP
configuration.
For IMVP-6.5 applications (CLKEN pullup to 3.3V with
1.9kΩ), the MAX17528 pulls CLKEN low approximately
60µs after reaching PGDIN is pulled high and the controller reaches the 1.1V boot voltage. At the same time,
the MAX17528 slews the output to the selected VID
voltage at the programmed nominal slew rate. PWRGD
becomes high impedance approximately 5ms after
CLKEN is pulled low.
For GMCH applications (CLKEN = GND), PWRGD
becomes high impedance approximately 60µs after
reaching the selected VID voltage.
For automatic startup, the battery voltage should be
present before VCC rises above its UVLO threshold. If
the controller attempts to bring the output into regulation without the battery voltage present, the output
undervoltage fault latch disables the controller. The
MAX17528 remains shut down until the fault latch is
cleared by toggling SHDN or cycling the VCC power
supply below 0.5V.
Figure 8. Pulse-Skipping/Discontinuous Crossover Point
______________________________________________________________________________________
31
MAX17528
Automatic Pulse-Skipping Switchover
In skip mode (SKIP = high), an inherent automatic
switchover to PFM takes place at light loads (Figure 8).
This switchover is affected by a comparator that truncates
the low-side switch on-time at the inductor current’s zero
crossing. The zero-crossing comparator senses the
inductor current across the low-side MOSFETs. Once
VLX drops below the zero-crossing comparator threshold
(see the Electrical Characteristics table), the comparator
forces DL low (Figure 3). This mechanism causes the
threshold between pulse-skipping PFM and nonskipping
PWM operation to coincide with the boundary between
continuous and discontinuous inductor-current operation. The PFM/PWM crossover occurs when the load-current is equal to 1/2 the peak-to-peak ripple current,
which is a function of the inductor value (Figure 8). For a
battery input range of 7V to 20V, this threshold is relatively constant, with only a minor dependence on the input
voltage due to the typically low duty cycles. The total
load current at the PFM/PWM crossover threshold
(ILOAD(SKIP)) is approximately:
MAX17528
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
If the VCC voltage drops below 4.25V, the controller
assumes that there is not enough supply voltage to make
valid decisions. To protect the output from overvoltage
faults, the controller shuts down immediately and forces
a high-impedance output (DL and DH pulled low) and
pulls CSN low through a 10Ω discharge MOSFET.
VCC
SHDN
VID (D0–D6)
INVALID VID
VALID VID
INVALID VID
SOFT-START
1/8 RTIME SLEW RATE
SOFT-SHUTDOWN
1/8 RTIME SLEW RATE
1.1V BOOT
CPU CORE
VOLTAGE
INTERNAL
PWM MODE
PULSE SKIPPING
FORCED-PWM MODE
CLKEN
PWRGD
tBLANK
60µs typ
tBLANK
5ms typ
tBLANK
60µs typ
tBLANK
20µs typ
NOTE: PGDIN = VCC.
Figure 9. IMVP-6.5 Power-Up and Shutdown Sequence Timing Diagram
VCC
SHDN
VID (D0–D6)
VALID VID
INVALID VID
SOFT-START
1/8 RTIME SLEW RATE
SOFT-SHUTDOWN
1/8 RTIME SLEW RATE
GMCH CORE
VOLTAGE
INTERNAL
PWM MODE
PULSE SKIPPING
FORCED-PWM
PWRGD
tBLANK
5ms typ
tBLANK
60µs typ
Figure 10. GMCH Power-Up and Shutdown Sequence Timing Diagram
32
______________________________________________________________________________________
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
SHDN
SLOW
SKIP
GND
X
X
DISABLED
LOW-POWER SHUTDOWN. DL forced low, and the controller is disabled. The
supply current drops below 30µA.
STARTUP. When SHDN is pulled high, the MAX17528 begins the startup
sequence after the internal circuitry powers up. The MAX17528 enables the
PWM controller and ramps the output voltage up to the startup voltage. See
Figures 9 and 10.
MAX17528
Table 3. Operating Mode Truth Table
OPERATING MODE
Rising
X
X
Pulse skipping
1/8 RTIME slew
rate
High
X
Low
Forced-PWM
nominal RTIME
slew rate
FULL POWER. The no-load output voltage is determined by the selected VID
DAC code (Table 2).
High
Pulse-skipping
nominal RTIME
slew rate
LOW-POWER MODE (NOMINAL TRANSITION). The no-load output voltage is
determined by the selected VID DAC code (Table 2). When SKIP is pulled high,
the controller immediately enters pulse-skipping operation, allowing automatic
PWM/PFM switchover under light loads. The PWRGD and CLKEN upper
thresholds are blanked during the transition.
High
Pulse-skipping
1/2 RTIME slew
rate
LOW-POWER MODE (SLOW TRANSITION). The no-load output voltage is
determined by the selected VID DAC code (Table 2). When SKIP is pulled high,
the MAX17528 enters pulse-skipping operation, allowing automatic PWM/PFM
switchover under light loads. The PWRGD and CLKEN thresholds are blanked
during the transition.
SHUTDOWN. When SHDN is pulled low, the MAX17528 immediately pulls
PWRGD low, CLKEN becomes high impedance, and the output voltage is
ramped down to ground. Once the output reaches zero, the controller enters the
low-power shutdown state. See Figures 9 and 10.
FAULT MODE. The fault latch has been set by the MAX17528 UVP fault, RTON
open fault, or thermal-shutdown protection. The controller remains in FAULT
mode until VCC power is cycled or SHDN toggled.
High
High
High
Low
Falling
X
X
Forced-PWM
1/8 RTIME slew
rate
High
X
X
DISABLED
Shutdown
When SHDN goes low, the MAX17528 enters lowpower shutdown mode. PWRGD is pulled low immediately, and the output voltage ramps down at 1/8 the
slew rate set by RTIME:
8VOUT
t TRAN(SHDN) =
(dVTARGET / dt)
where dVTARGET/dt = 12.5mV/µs x 71.5kΩ/RTIME is the
nominal slew rate. Slowly discharging the output capacitors by slewing the output over a long period of time
keeps the average negative inductor current low
(damped response), thereby eliminating the negative
output-voltage excursion that occurs when the controller
discharges the output quickly by permanently turning on
the low-side MOSFET (underdamped response). This
eliminates the need for the Schottky diode connected
between the output and ground to clamp the negative
output-voltage excursion. After the controller reaches
the zero target, the MAX17528 shuts down completely—
the drivers are disabled (DL and DH are pulled low)—
the internal reference turns off, and the supply currents
drop to about 30µA (max).
When an output undervoltage fault condition activates
the shutdown sequence, the protection circuitry sets the
UVP fault latch to prevent the controller from restarting.
To clear the fault latch and reactivate the controller,
toggle SHDN or cycle VCC power below 0.5V.
Current Monitor (IMON)
The MAX17528 includes a unidirectional transconductance amplifier that sources current proportional to the
positive current-sense voltage. The IMON output current is defined by:
IIMON = Gm(IMON) x (VCSP - VCSN)
where Gm(IMON) = 5mS (typ) and the IMON current is
unidirectional (sources current out of IMON only) for
positive current-sense values. For negative currentsense voltages, the IMON current is zero.
______________________________________________________________________________________
33
MAX17528
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
The current monitor allows the processor to accurately
monitor the CPU load and quickly calculate the power
dissipation to determine if the system is about to overheat before the significantly slower temperature sensor
signals an overtemperature alert.
Connect an external resistor between IMON and
VSS_SENSE to create the desired IMON gain based on
the following equation:
RIMON = 0.999V/(IMAX x RSENSE x Gm(IMON))
where IMAX is defined in the Current Monitor section of
the Intel IMVP-6.5 specification and based on discrete
increments (10A, 20A, 30A, 40A, etc.,), RSENSE is the
typical effective value of the current-sense element
(sense resistor or inductor DCR) that is used to provide
the current-sense voltage, and Gm(IMON) is the typical
transconductance amplifier gain as defined in the
Electrical Characteristics table.
The IMON voltage is internally clamped to a maximum
of 1.1V (typ), preventing the IMON output from exceeding the IMON voltage rating even under overload or
short-circuit conditions. When the controller is disabled,
IMON is pulled to ground.
The transconductance amplifier and voltage clamp are
internally compensated, so IMON cannot directly drive
large capacitance values. To filter the IMON signal, use
an RC filter as shown in Figure 1.
Temperature Comparator (VRHOT)
The MAX17528 also features an independent comparator with an accurate threshold that tracks the analog
supply voltage (VHOT = 0.3 x VCC). This makes the thermal trip threshold independent of the VCC supply voltage tolerance. Use a resistor- and thermistor-divider
between VCC and GND to generate a voltage-regulator
overtemperature monitor. Place the thermistor as close
as possible to the MOSFETs and inductors.
Output Undervoltage (UVP) Protection
The output UVP function limits the power loss by disabling the regulator if the MAX17528 output voltage
drops 400mV below the target voltage; the controller
activates the shutdown sequence and sets the fault
latch. Once the controller ramps down to zero, it forces
DL high and DH low. Toggle SHDN or cycle the VCC
power supply below 0.5V to clear the fault latch and
reactivate the controller.
UVP protection can be disabled through the no-fault
test mode (see the No-Fault Test Mode section).
34
Thermal Fault Protection
The MAX17528 features a thermal-fault-protection circuit. When the junction temperature rises above
+160°C, a thermal sensor sets the fault latch, forces DL
low, and pulls DH low. Toggle SHDN or cycle the VCC
power supply below 0.5V to clear the fault latch and
reactivate the controller after the junction temperature
cools by 15°C. Thermal shutdown can be disabled
through the no-fault test mode (see the No-Fault Test
Mode section).
No-Fault Test Mode
The latched fault-protection feature can complicate the
process of debugging prototype breadboards since
there are (at most) a few milliseconds in which to determine what went wrong. Therefore, a “no-fault” test
mode is provided to disable the fault protection—UVP,
thermal shutdown, and TON open-circuit fault protection. The “no-fault” test mode also disables the BST
switch, although the switch’s body diode provides sufficient power for the high-side driver to function properly.
Additionally, the test mode clears the fault latch if it has
been set. The no-fault test mode is entered by forcing
11V to 13V on SHDN.
MOSFET Gate Drivers
The DH and DL drivers are optimized for driving moderate-sized high-side and larger low-side power
MOSFETs. This is consistent with the low duty factor
seen in notebook applications, where a large V IN VOUT differential exists. The high-side gate drivers (DH)
source and sink 2.2A, and the low-side gate drivers
(DL) source 2.7A and sink 8A. This ensures robust gate
drive for high-current applications. The DH high-side
MOSFET driver is powered by an internal charge-pump
boost switch at BST, while the DL synchronous-rectifier
driver is powered directly by the 5V bias supply (VDD).
Adaptive dead-time circuits monitor the DL and DH drivers and prevent either FET from turning on until the
other is fully off. The adaptive driver dead time allows
operation without shoot-through with a wide range of
MOSFETs, minimizing delays and maintaining efficiency.
There must be a low-resistance, low-inductance path
from the DL and DH drivers to the MOSFET gates for
the adaptive dead-time circuits to work properly; otherwise, the sense circuitry in the MAX17528 interprets the
MOSFET gates as “off” while charge actually remains.
Use very short, wide traces (50 mils to 100 mils wide if
the MOSFET is 1in from the driver).
______________________________________________________________________________________
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
MAX17528
BST
MAX17528
The internal pulldown transistor that drives DL low is
robust, with a 0.25Ω (typ) on-resistance. This helps prevent DL from being pulled up due to capacitive coupling
from the drain to the gate of the low-side MOSFETs
when the inductor node (LX) quickly switches from
ground to VIN. Applications with high input voltages and
long inductive driver traces must guarantee rising LX
edges do not pull up the low-side MOSFET’s gate, causing shoot-through currents. The capacitive coupling
between LX and DL created by the MOSFET’s gate-todrain capacitance (CRSS), gate-to-source capacitance
(CISS - CRSS), and additional board parasitics should
not exceed the following minimum threshold:
(RBST)*
INPUT (VIN)
CBST
DH
NH
L
LX
VDD
CBYP
⎛C
⎞
VGS(TH) < VIN ⎜ RSS ⎟
⎝ CISS ⎠
DL
Typically, adding a 4700pF between DL and power
ground (C NL in Figure 11), close to the low-side
MOSFETs, greatly reduces coupling. Do not exceed
22nF of total gate capacitance to prevent excessive
turn-off delays.
Alternatively, shoot-through currents can be caused by
a combination of fast high-side MOSFETs and slow lowside MOSFETs. If the turn-off delay time of the low-side
MOSFET is too long, the high-side MOSFETs can turn
on before the low-side MOSFETs have actually turned
off. Adding a resistor less than 5Ω in series with BST
slows down the high-side MOSFET turn-on time, eliminating the shoot-through currents without degrading
the turn-off time (RBST in Figure 11). Slowing down the
high-side MOSFET also reduces the LX node rise time,
thereby reducing EMI and high-frequency coupling
responsible for switching noise.
PGND
(RBST)* OPTIONAL—THE RESISTOR LOWERS EMI BY DECREASING
THE SWITCHING NODE RISE TIME.
(CNL)* OPTIONAL—THE CAPACITOR REDUCES LX TO DL CAPACITIVE
COUPLING THAT CAN CAUSE SHOOT-THROUGH CURRENTS.
Figure 11. Gate-Drive Circuit
•
Maximum load current: There are two values to
consider. The peak load current (I LOAD(MAX) )
determines the instantaneous component stresses
and filtering requirements, and thus, drives output
capacitor selection, inductor saturation rating, and
the design of the current-limit circuit. The continuous load current (ILOAD) determines the thermal
stresses, and thus, drives the selection of input
capacitors, MOSFETs, and other critical heat-contributing components. Modern notebook CPUs generally exhibit ILOAD = ILOAD(MAX) x 80%.
•
Load line (voltage positioning): The load line (output voltage vs. load slope) dynamically lowers the
output voltage in response to the load current, reducing the output capacitance requirement and the
processor’s power dissipation. The Intel specification
clearly defines the load-line requirement in the powersupply specifications for each processor family.
Quick-PWM
Design Procedure
Firmly establish the input voltage range and maximum
load current before choosing a switching frequency
and inductor operating point (ripple-current ratio). The
primary design trade-off lies in choosing a good switching frequency and inductor operating point, and the following five factors dictate the rest of the design:
• Input voltage range: The maximum value
(VIN(MAX)) must accommodate the worst-case high
AC adapter voltage. The minimum value (VIN(MIN))
must account for the lowest input voltage after
drops due to connectors, fuses, and battery selector switches. If there is a choice at all, lower input
voltages result in better efficiency.
NL
(CNL)*
______________________________________________________________________________________
35
MAX17528
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
•
•
Switching frequency: This choice determines the
basic trade-off between size and efficiency. The
optimal frequency is largely a function of maximum
input voltage due to MOSFET switching losses that
are proportional to frequency and VIN2. The optimum frequency is also a moving target due to rapid
improvements in MOSFET technology that are making higher frequencies more practical.
Inductor operating point: This choice provides
trade-offs between size vs. efficiency and transient
response vs. output noise. Low inductor values provide better transient response and smaller physical
size, but also result in lower efficiency and higher
output noise due to increased ripple current. The
minimum practical inductor value is one that causes
the circuit to operate at the edge of critical conduction (where the inductor current just touches zero
with every cycle at maximum load). Inductor values
lower than this grant no further size-reduction benefit. The optimum operating point is usually found
between 20% and 50% ripple current.
Inductor Selection
The switching frequency and operating point (% ripple
current or LIR) determine the inductor value as follows:
⎛
⎞⎛ V
VIN − VOUT
OUT ⎞
L=⎜
⎟⎜
⎟
f
I
LIR
V
⎝ SW LOAD(MAX)
⎠ ⎝ IN ⎠
Find a low-loss inductor having the lowest possible DC
resistance that fits in the allotted dimensions. Molded
cores are often the best choice, although powdered
iron and ferrite cores are inexpensive and can work
well at 300kHz. The core must be large enough not to
saturate at the peak inductor current (IPEAK):
⎛ LIR ⎞
IPEAK = ILOAD(MAX) ⎜1 +
⎟
⎝
2 ⎠
Transient Response
The inductor ripple current impacts transient-response
performance, especially at low VIN - VOUT differentials.
Low inductor values allow the inductor current to slew
faster, replenishing charge removed from the output filter capacitors by a sudden load step. The amount of
output sag is also a function of the maximum duty factor, which can be calculated from the on-time and minimum off-time. The worst-case output sag voltage can
be determined by:
36
⎡⎛ VOUT tSW ⎞
⎤
+ tOFF(M
⎢⎜
MIN) ⎥
⎟
VIN ⎠
⎣⎝
⎦
VSAG =
⎡⎛ ( VIN − VOUT ) tSW ⎞
⎤
2COUT VOUT ⎢⎜
⎟ − tOFF(MIN) ⎥
V
⎠
⎢⎣⎝
⎥⎦
IN
(
L ∆ILOAD(MAX)
)2
where t OFF(MIN) is the minimum off-time (see the
Electrical Characteristics table).
The amount of overshoot due to stored inductor energy
can be calculated as:
VSOAR
2
∆ILOAD(MAX) ) L
(
≈
2COUT VOUT
Current-Limit and Slew-Rate Control
(TIME and ILIM)
TIME and ILIM are used to control the slew rate and
current limit. TIME regulates to a fixed 2.0V. The
MAX17528 uses the TIME source current to set the
slew rate (dVTARGET/dt). The higher the source current,
the faster the nominal output-voltage slew rate:
⎛ 71.5kΩ ⎞
dVTARGET / dt = 12.5mV / µs × ⎜
⎝ RTIME ⎟⎠
where RTIME is the sum of resistance values between
TIME and ground.
The ILIM voltage determines the valley current-sense
threshold. When ILIM = VCC, the controller uses the
preset 22.5mV (typ) current-limit threshold. In an
adjustable design, ILIM is connected to a resistive voltage-divider connected between TIME and ground. The
differential voltage between TIME and ILIM sets the
current-limit threshold (VLIMIT), so the valley currentsense threshold is:
V
−V
VLIMIT = TIME ILIM
10
where the VLIMIT tolerances are defined in the Electrical
Characteristics table.
This allows design flexibility since the DCR sense circuit or sense resistor does not have to be adjusted to
meet the current limit as long as the current-sense voltage never exceeds 50mV. Keeping VLIMIT between
20mV to 40mV leaves room for future current-limit
adjustment.
______________________________________________________________________________________
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
⎛ LIR ⎞
IVALLEY > ILOAD(MAX) ⎜1 −
⎟
⎝
2 ⎠
In CPU VCORE converters and other applications where
the output is subject to large-load transients, the output
capacitor’s size typically depends on how much ESR is
needed to prevent the output from dipping too low
under a load transient. Ignoring the sag due to finite
capacitance:
(RESR + RPCB ) ≤ ∆I
VSTEP
LOAD(MAX)
where:
IVALLEY =
VLIMIT
VLIMIT
=
RSENSE DCR × RCSP−CSN
RLX −CSN
where RSENSE is the sensing resistor and RCSP-CSN/
R LX-CSN is the ratio of resistor-divider with DCRsensing approach.
In non-CPU applications, the output capacitor’s size
often depends on how much ESR is needed to maintain
an acceptable level of output ripple voltage. The output
ripple voltage of a step-down controller equals the total
inductor ripple current multiplied by the output capacitor’s ESR. The maximum ESR to meet ripple requirements is:
⎡
⎤
VINfSWL
RESR ≤ ⎢
⎥VRIPPLE
⎢⎣ (VIN − VOUT )VOUT ⎥⎦
Voltage Positioning and
Loop Compensation
Voltage positioning dynamically lowers the output voltage in response to the load current, reducing the output capacitance and processor’s power dissipation
requirements. The controller uses a transconductance
amplifier to set the transient and DC output voltage
droop (Figure 3) as a function of the load. This adjustability allows flexibility in the selected current-sense
resistor value or inductor DCR, and allows smaller current-sense resistance to be used, reducing the overall
power dissipated.
Steady-State Voltage Positioning
Connect a resistor (RFB) between FB and VOUT to set
the DC steady-state droop (load line) based on the
required voltage-positioning slope (RDROOP):
RFB =
RDROOP
RSENSEGm(FB)
where the effective current-sense resistance (RSENSE)
depends on the current-sense method (see the Current
Sense section), and the voltage-positioning amplifier’s
transconductance (G m(FB) ) is typically 600µS as
defined in the Electrical Characteristics table. When the
inductors’ DCR is used as the current-sense element
(R SENSE = R DCR), the current-sense design should
include a thermistor to minimize the temperature
dependence of the voltage-positioning slope as shown
in Figure 1.
Output Capacitor Selection
The output filter capacitor must have low enough effective series resistance (ESR) to meet output ripple and
load-transient requirements, yet have high enough ESR
to satisfy stability requirements.
where f SW is the switching frequency. The actual
capacitance value required relates to the physical size
needed to achieve low ESR, as well as to the chemistry
of the capacitor technology. Thus, the capacitor is usually selected by ESR and voltage rating rather than by
capacitance value (this is true of polymer types).
When using low-capacity ceramic filter capacitors,
capacitor size is usually determined by the capacity
needed to prevent V SAG and V SOAR from causing
problems during load transients. Generally, once
enough capacitance is added to meet the overshoot
requirement, undershoot at the rising load edge is no
longer a problem (see the VSAG and VSOAR equations
in the Transient Response section).
Output Capacitor Stability Considerations
For Quick-PWM controllers, stability is determined by
the value of the ESR zero relative to the switching frequency. The boundary of instability is given by the following equation:
f
fESR ≤ SW
π
where:
fESR =
1
2πREFFCOUT
and:
REFF = RESR + RDROOP + RPCB
where COUT is the total output capacitance, RESR is the
total ESR, RDROOP is the voltage-positioning slope, and
______________________________________________________________________________________
37
MAX17528
The minimum current-limit threshold must be high
enough to support the maximum load current when the
current limit is at the minimum tolerance value. The valley of the inductor current occurs at ILOAD(MAX) minus
half the ripple current; therefore:
MAX17528
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
RPCB is the parasitic board resistance between the output capacitors and sense resistors.
For a standard 300kHz application, the ESR zero frequency must be well below 95kHz, preferably below
50kHz. Tantalum, SANYO POSCAP, and Panasonic SP
capacitors in widespread use at the time of publication
have typical ESR zero frequencies below 50kHz. In the
standard GMCH application circuit, the ESR needed to
support a 10mVP-P ripple is 10mV/(10A x 0.3) = 3.3mΩ.
Two 330µF/2.5V Panasonic SP (type SX) capacitors in
parallel provide 3.0mΩ (max) ESR. With a 5mΩ droop
and 0.5mΩ PCB resistance, the typical combined ESR
results in a zero at 28kHz.
Ceramic capacitors have a high-ESR zero frequency,
but applications with significant voltage positioning can
take advantage of their size and low ESR. Do not put
high-value ceramic capacitors directly across the output without verifying that the circuit contains enough
voltage positioning and series PCB resistance to
ensure stability. When only using ceramic output
capacitors, output overshoot (VSOAR) typically determines the minimum output capacitance requirement.
Their relatively low capacitance value can cause output
overshoot when stepping from full-load to no-load conditions, unless a small inductor value is used (high
switching frequency) to minimize the energy transferred
from inductor to capacitor during load-step recovery.
Unstable operation manifests itself in two related, but
distinctly different ways: double pulsing and feedback
loop instability. Double pulsing occurs due to noise on
the output or because the ESR is so low that there is
not enough voltage ramp in the output voltage signal.
This “fools” the error comparator into triggering a new
cycle immediately after the minimum off-time period
has expired. Double pulsing is more annoying than
harmful, resulting in nothing worse than increased output ripple. However, it can indicate the possible presence of loop instability due to insufficient ESR. Loop
instability can result in oscillations at the output after
line or load steps. Such perturbations are usually
damped, but can cause the output voltage to rise
above or fall below the tolerance limits.
The easiest method for checking stability is to apply a
very fast zero-to-max load transient and carefully
observe the output voltage ripple envelope for overshoot and ringing. It can help to simultaneously monitor
the inductor current with an AC current probe. Do not
allow more than one cycle of ringing after the initial
step-response under/overshoot.
38
Input Capacitor Selection
The input capacitor must meet the ripple current
requirement (IRMS) imposed by the switching currents.
The IRMS requirements can be determined by the following equation:
⎛I
⎞
IRMS = ⎜ LOAD ⎟ VOUT (VIN − VOUT )
V
⎝ IN ⎠
The worst-case RMS current requirement occurs when
operating with VIN = 2 x VOUT. At this point, the above
equation simplifies to IRMS = 0.5 x ILOAD.
For most applications, nontantalum chemistries (ceramic,
aluminum, or OS-CON) are preferred due to their resistance to inrush surge currents typical of systems with a
mechanical switch or connector in series with the input.
If the Quick-PWM controller is operated as the second
stage of a two-stage power-conversion system, tantalum input capacitors are acceptable. In either configuration, choose an input capacitor that exhibits less than
+10°C temperature rise at the RMS input current for
optimal circuit longevity.
Power-MOSFET Selection
Most of the following MOSFET guidelines focus on the
challenge of obtaining high load-current capability
when using high-voltage (> 20V) AC adapters. Lowcurrent applications usually require less attention.
The high-side MOSFET (NH) must be able to dissipate
the resistive losses plus the switching losses at both
VIN(MIN) and VIN(MAX). Calculate both of these sums.
Ideally, the losses at VIN(MIN) should be roughly equal
to losses at VIN(MAX), with lower losses in between. If
the losses at VIN(MIN) are significantly higher than the
losses at VIN(MAX), consider increasing the size of NH
(reducing RDS(ON) but with higher CGATE). Conversely,
if the losses at VIN(MAX) are significantly higher than the
losses at VIN(MIN), consider reducing the size of NH
(increasing RDS(ON) to lower CGATE). If VIN does not vary
over a wide range, the minimum power dissipation occurs
where the resistive losses equal the switching losses.
Choose a low-side MOSFET that has the lowest possible on-resistance (R DS(ON)), comes in a moderatesized package (i.e., one or two 8-pin SOs, DPAK, or
D2PAK), and is reasonably priced. Make sure that the
DL gate driver can supply sufficient current to support
the gate charge and the current injected into the parasitic gate-to-drain capacitor caused by the high-side
MOSFET turning on; otherwise, cross-conduction problems can occur (see the MOSFET Gate Drivers section).
______________________________________________________________________________________
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
⎛V
⎞
2
PD(NHRe sistive) = ⎜ OUT ⎟ (ILOAD ) RDS(ON)
⎝ VIN ⎠
Generally, a small high-side MOSFET is desired to
reduce switching losses at high input voltages.
However, the RDS(ON) required to stay within package
power dissipation often limits how small the MOSFET
can be. Again, the optimum occurs when the switching
losses equal the conduction (RDS(ON)) losses. Highside switching losses do not usually become an issue
until the input is greater than approximately 15V.
Calculating the power dissipation in high-side MOSFET
(NH) due to switching losses is complicated since it
must allow for difficult quantifying factors that influence
the turn-on and turn-off times. These factors include the
internal gate resistance, gate charge, threshold voltage, source inductance, and PCB layout characteristics. The following switching-loss calculation provides
only a very rough estimate and is no substitute for
breadboard evaluation, preferably including verification
using a thermocouple mounted on NH:
⎛ QG(SW) ⎞ COSSVIN2fSW
PD(NHSwitching) = VIN(MAX)ILOADfSW ⎜
⎟+
2
⎝ IGATE ⎠
where COSS is the NH MOSFET’s output capacitance,
QG(SW) is the charge needed to turn on the NH MOSFET,
and IGATE is the peak gate-drive source/sink current
(2.2A typ).
Switching losses in the high-side MOSFET can become
an insidious heat problem when maximum AC adapter
voltages are applied, due to the squared term in the
C x VIN2 x fSW switching-loss equation. If the high-side
MOSFET chosen for adequate RDS(ON) at low battery
voltages becomes extraordinarily hot when biased from
V IN(MAX) , consider choosing another MOSFET with
lower parasitic capacitance.
For the low-side MOSFET (NL), the worst-case power
dissipation always occurs at maximum input voltage:
⎡ ⎛ V
⎞⎤
2
PD(NL Re sistive) = ⎢1 − ⎜ OUT ⎟ ⎥(ILOAD ) RDS(ON)
⎢⎣ ⎝ VIN(MAX) ⎠ ⎥⎦
ILOAD(MAX), but are not quite high enough to exceed
the current limit and cause the fault latch to trip. To protect against this possibility, you can “over design” the
circuit to tolerate:
∆I
⎛
⎞
ILOAD = ⎜ IVALLEY(MAX) + INDUCTOR ⎟ = IVALLEY(MAX)
⎝
⎠
2
where I VALLEY(MAX) is the maximum valley current
allowed by the current-limit circuit, including threshold
tolerance and on-resistance variation. The MOSFETs
must have a good-size heatsink to handle the overload
power dissipation.
Choose a Schottky diode (DL) with a forward voltage
low enough to prevent the low-side MOSFET body
diode from turning on during the dead time. Select a
diode that can handle the load current during the dead
times. This diode is optional and can be removed if efficiency is not critical.
Boost Capacitors
The boost capacitors (CBST) must be selected large
enough to handle the gate-charging requirements of
the high-side MOSFETs. Typically, 0.1µF ceramic
capacitors work well for low-power applications driving
medium-sized MOSFETs. However, high-current applications driving large, high-side MOSFETs require boost
capacitors larger than 0.1µF. For these applications,
select the boost capacitors to avoid discharging the
capacitor more than 200mV while charging the highside MOSFETs’ gates:
CBST =
N × QGATE
200mV
where N is the number of high-side MOSFETs used for
one regulator, and QGATE is the gate charge specified
in the MOSFET’s data sheet. For example, assume (2)
IRF7811W n-channel MOSFETs are used on the high
side. According to the manufacturer’s data sheet, a single IRF7811W has a maximum gate charge of 24nC
(VGS = 5V). Using the above equation, the required
boost capacitance would be:
CBST =
2 × 24nC
= 0.24µF
200mV
Selecting the closest standard value, this example
requires a 0.22µF ceramic capacitor.
The worst case for MOSFET power dissipation occurs
under heavy overloads that are greater than
______________________________________________________________________________________
39
MAX17528
MOSFET Power Dissipation
Worst-case conduction losses occur at the duty factor
extremes. For the high-side MOSFET (NH), the worstcase power dissipation due to resistance occurs at the
minimum input voltage:
MAX17528
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
Applications Information
•
CSP and CSN connections for current limiting and
voltage positioning must be made using Kelvinsense connections to guarantee the current-sense
accuracy.
•
Route high-speed switching nodes (LX, DH, BST,
and DL) away from sensitive analog areas (FB,
CSP, CSN, CCV, etc.).
PCB Layout Guidelines
Careful PCB layout is critical to achieve low switching
losses and clean, stable operation. The switching
power stage requires particular attention. If possible,
mount all the power components on the top side of the
board with their ground terminals flush against one
another. Follow the MAX17528 Evaluation Kit layout and
use the following guidelines for good PCB layout:
•
High-current path/components: Keep the high-current paths short, especially at the ground terminals.
This is essential for stable, jitter-free operation.
•
Keep the power traces and load connections short.
This is essential for high efficiency. The use of thick
copper PCBs (2oz vs. 1oz) can enhance full-load
efficiency by 1% or more. Correctly routing PCB
traces is a difficult task that must be approached in
terms of fractions of centimeters, where a single
mΩ of excess trace resistance causes a measurable efficiency penalty.
•
When trade-offs in trace lengths must be made, it is
preferable to allow the inductor charging path to be
made longer than the discharge path. For example,
it is better to allow some extra distance between the
input capacitors and the high-side MOSFET than to
allow distance between the inductor and the lowside MOSFET or between the inductor and the output filter capacitor.
•
MOSFET drivers: Keep the high-current, gate-driver traces (DL, DH, LX, and BST) short and wide
to minimize trace resistance and inductance. This
is essential for high-power MOSFETs that require
low-impedance gate drivers to avoid shootthrough currents.
•
Analog control signals: Connect all analog grounds
to a separate solid copper plane, which connects to
the GND pin of the Quick-PWM controller as shown
in Figures 1 and 2. This includes the VCC bypass
capacitor, remote-sense bypass capacitors, and
the compensation (CCV) components.
40
Layout Procedure
1) Place the power components first, with ground terminals adjacent (low-side MOSFET source, CIN,
COUT, and D1 anode). If possible, make all these
connections on the top layer with wide, copperfilled areas.
2) Mount the controller IC adjacent to the low-side
MOSFET. The DL gate traces must be short and
wide (50 mils to 100 mils wide if the MOSFET is 1in
from the controller IC).
3) Group the gate-drive components (BST capacitor,
VDD bypass capacitor) together near the controller IC.
4) Make the DC-DC controller ground connections as
shown in the standard application circuits. This diagram can be viewed as having three separate
ground planes: input/output system ground, where
all the high-power components go; the power
ground plane, where the PGND pin and V DD
bypass capacitor go; and the controller’s analog
ground plane where sensitive analog components,
the analog GND pin, and VCC bypass capacitor go.
The analog GND plane must meet the PGND plane
only at a single point directly beneath the controller.
This star ground point (where the power and analog
grounds are connected) should connect to the
high-power system ground with a low-impedance
connection (short trace or multiple vias) from PGND
to the source of the low-side MOSFET.
5) Connect the output power planes (VCORE and system ground planes) directly to the output filter
capacitor positive and negative terminals with multiple vias. Place the entire DC-DC converter circuit
as close as is practical to the CPU.
______________________________________________________________________________________
1-Phase Quick-PWM
Intel IMVP-6.5/GMCH Controllers
PROCESS: BiCMOS
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages.
PACKAGE TYPE
PACKAGE CODE
DOCUMENT NO.
32 TQFN
T3255-3
21-0140
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 41
© 2009 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
MAX17528
Package Information
Chip Information