AP702 USB Host and PLL Interface with DSP and MCU Controller AP702 USB Host and PLL Interface with DSP and MCU Controller Data Sheet Revision 0.5 September 01, 2008 AP702 USB Host and PLL Interface with DSP and MCU Controller Table of Contents 1. OVERVIEW............................................................................................................................................1 2. APPLICATIONS ....................................................................................................................................1 3. FEATURES .............................................................................................................................................1 4. ORDERING INFORMATION..............................................................................................................1 5. BLOCK DIAGRAM ...............................................................................................................................2 6. PIN CONFIGURATION........................................................................................................................3 7. DEVICE PIN DESCRIPTION ..............................................................................................................3 8. EXTERNAL MEMORY CONFIGURATION ....................................................................................6 8.1 SUPPORTING MEMORY DEVICES ..................................................................................................................................................................6 8.2 EXTERNAL MEMORY CONNECTION..............................................................................................................................................................6 9. ELECTRICAL SPECIFICATION .......................................................................................................6 9.1 ABSOLUTE MAXIMUM RATINGS ..................................................................................................................................................................6 9.2 RECOMMENDED OPERATING CONDITION .....................................................................................................................................................6 9.3 ELECTRICAL CHARACTERISTICS ..................................................................................................................................................................6 10. PACKAGE INFORMATION................................................................................................................6 11. SOLDERING INDICATION.................................................................................................................6 1. REFLOW SOLDERING ...................................................................................................................................................................................6 2. WAVE SOLDERING ......................................................................................................................................................................................6 3. MANUAL SOLDERING ..................................................................................................................................................................................6 4. SUITABILITY OF SURFACE MOUNT IC PACKAGES FOR WAVE AND REFLOW SOLDERING METHODS ...............................................................6 Figures FIGURE 1. BLOCK DIAGRAM OF AP702......................................................................................................................................................................2 FIGURE 2. 128 PIN LQFP PACKAGE OF AP702 ..........................................................................................................................................................3 FIGURE 3. LQFP PACKAGE DIMENSION DRAWING ......................................................................................................................................................6 Revision 0.5 September 01, 2008 AP702 USB Host and PLL Interface with DSP and MCU Controller 1. OVERVIEW AP702 is an USB Host and PLL Interface with DSP and MCU Controller. It has a built-in 24-bit DSP for MP3 and WMA decoding, an 8-bit MCU for CD servo control, ISO9660 file system handling and user interface function control. An USB host controller is included in AP702 to support the data control and playback of MP3 files on portable MP3 players. AP702 also offers SD card support, giving the end customers a luxury of a SD card plug-and-play element. This chip also has an on-chip PLL controller for external tuner IC to form a complete digital tuning system. This system-on-chip solution is ideal for CD-base audio products 2. APPLICATIONS Micro or mini stereo sound system iPod docking system Boom box • • • 3. FEATURES CD Servo Interface and Control • • Interface to external CD servo controller Built-in CD ROM C3 ECC and EDC error detection and correction MP2 Decoding • Support 11.025/32/48/44.1/48kHz sampling frequencies and bit rate from 32kbps to 320kbps • Support mono and stereo audio playback • Support 22.05/24KHz sampling frequencies and bit rate from 8kbps to 160kbps MP3 Decoding • Support 16/22.05/24/32/44.1/48kHz sampling frequencies and bit rate from 32kbps to 320kbps • Support single channel, dual channel, stereo, and joint stereo audio playback • Support any combination of intensity stereo and MS stereo • Support MP3 ID3 version up to version 2.4 MP3 Encoding • Support 44.1kHz sampling frequency and bit rate from 64kbps to 128kbps • Support stereo audio encoding • 1x encode speed WMA Decoding • Support 32/44.1/48kHz sampling frequencies and bit rates of 64kbps to 320kbps • Support single channel, dual channel, stereo, and joint stereo audio playback USB Host and SD Card Support • Support direct connection of USB mass storage class device into the system, such as portable MP3 player and USB flash drive • USB card reader support • Normal, Mini Micro SD Card support • SDHC SD Card support • Support FAT 12, 16 and 32 file system 4. ORDERING INFORMATION Ordering Number Pins Package AP702-LQ-L 128 LQFP P Revision 0.5 Page 1 of 11 September 01, 2008 AP702 USB Host and PLL Interface with DSP and MCU Controller 5. BLOCK DIAGRAM Figure 1. Block Diagram of AP702 P Revision 0.5 Page 2 of 11 September 01, 2008 AP702 USB Host and PLL Interface with DSP and MCU Controller 6. PIN CONFIGURATION Figure 2. 128 Pin LQFP Package of AP702 7. DEVICE PIN DESCRIPTION Pin No. 1 2 Name P0[2] P0[3]/LCMCS Type IO IO Drive (mA) 4 4 3 FWEB/DQML/LCASB O 8 4 RWEB O 8 5 CASB O 8 6 FOEB/DQHM/HCASB O 8 Descriptions General purpose IO port General purpose IO port or LCM chip select 1. WEB for NOR-Flash 2. DQML for SDRAM 3. CASB for EDO 1. WEB for SDRAM or EDO 2. WEB for NOR Flash CASB for SDRAM 1. OEB for NOR-Flash 2. DQMH for SDRAM 3. HCASB for 16-bit EDO P Revision 0.5 Page 3 of 11 September 01, 2008 AP702 USB Host and PLL Interface with DSP and MCU Controller Pin No. 7 8 9 Name RAMCLK VCCIO GND Type O - Drive (mA) 8 - 10 RAMCKE/OEB O 8 11 RAS0B O 8 12 CSB/RAS1B O 8 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 MA14/CFG3 MA11/CFG0 MA9 MA8 MA7 MA6 MA5 VDD GND MA4 MA3 MA2 MA1 MA0 MA10 O O O O O O O 8 8 8 8 8 8 8 O O O O O O 8 8 8 8 8 8 28 MA23/P11[3]/I2C_SCK1 IO 8 29 MA22/P11[2]/I2C_SD1 IO 8 30 MA21/P11[1]/MCLKO IO 8 31 MA20/P11[0]/AUD_SDI2 IO 8 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 MA19/P10[3] P9[0]/SIN P1[0] P5[0]/EIRQ[5] MA12/CFG1 MA13/CFG2 MA15 MA16/P10[0] MA17/P10[1] MA18/P10[2] VCCIO GND MCLK OLRCLK OBCLK OAUDO DSP_EINT ILRCLK IBCLK AUD_SDI VDD GND EIRQ[0] IO IO IO IO O O O IO IO IO 8 4 4 4 8 8 8 8 8 8 IO IO IO IO I I I I 4 4 4 4 - I - 55 P9[2]/SYNCK IO 4 56 P9[1]/SYNIO IO 4 57 58 59 60 61 62 63 64 P4[1] P4[2] P4[3] P4[0] P5[2]/EIRQ[7] P5[3]/EIRQ[8] P6[0]/EIRQ[9] P6[1]/EIRQ[10] IO IO IO IO IO IO IO IO 4 4 4 4 4 4 4 4 Descriptions SDRAM operating clock 3.3V IO power supply Ground 1. CKE for SDRAM 2. OEB for EDO RASB for SDRAM or EDO 1. CSB for SDRAM nd 2. RASB for 2 EDO device Memory address and reset options control bits Memory address and reset options control bits Memory address Memory address Memory address Memory address Memory address 1.8V core supply Ground Memory address Memory address Memory address Memory address Memory address Memory address 1. Memory address 2. General IO port pin 3. I2C clock output 1. Memory address 2. General IO port pin 3. I2C clock output 1. Memory address 2. General IO port pin 3. 16.9344MHz clock output Memory address or general IO port pin or external ADC audio data input Memory address or general IO port pin General IO port pin or synchronous interface data input General purpose IO port General purpose IO port or MCU external interrupt input Memory address and reset options control bits Memory address and reset options control bits Memory address General purpose IO port or memory address. General purpose IO port or memory address. General purpose IO port or memory address. 3.3V IO power supply Ground 16.9344MHz output clock to external DAC or ADC Sampling clock for external DAC or ADC Bit clock for external DAC or ADC Serial data for external DAC or ADC DSP external interrupt input Sampling clock input Bit clock input Audio data input 1.8V core supply Ground MCU external interrupt input pin General purpose IO port or synchronous serial interface clock output General purpose IO port or synchronous serial interface bidirectional data General purpose IO port General purpose IO port General purpose IO port General purpose IO port General purpose IO port or MCU external interrupt input General purpose IO port or MCU external interrupt input General purpose IO port or MCU external interrupt input General purpose IO port or MCU external interrupt input P Revision 0.5 Page 4 of 11 September 01, 2008 AP702 USB Host and PLL Interface with DSP and MCU Controller Pin No. 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 Name P6[2]/TX P6[3]/RX P7[0]/RCK P7[1]/RCD P7[2]/BOUT ATONE P3[3]/ACIN P3[2] FMIN AMIN IFIN DTSPLLFLT VCCIO ROSCO ROSCI GND P3[1] P3[0] P2[0]/TONE P2[1]/TONE EIRQ[1] EIRQ[2] EIRQ[3] EIRQ[4] VDD GND P9[3]/REMO I2C_SD0 I2C_SCK P12[0] P8[0]/SPIDO P8[1]/SPISCLK P8[2]/SPICSB P8[3]/SPISDI P12[1] P12[2] P12[3]/EMU_SDO DM DP VCCIO XOSCO XOSCI GND TESTB[0] PLLFLT AVDD AGND VDD GND RSTB FCSB MD0 MD1 MD2 MD3 MD7 MD6 MD5 MD4 TESTB[1]/EMU_SCLR TESTB[2]/EMU_SCLK TESTB[3]/EMU_SDI P0[0] P0[1] Type IO IO IO IO IO A IO IO I I I IO Drive (mA) 4 4 4 4 4 4 4 4 O I - IO IO IO IO I I I I 4 4 4 4 - IO IO IO IO IO IO IO IO IO IO IO IO IO 4 4 4 4 4 4 4 4 4 4 4 O I I A - I O IO IO IO IO IO IO IO IO I I I IO IO 8 8 8 8 8 8 8 8 8 4 4 Descriptions General purpose IO port or UART TX output General purpose IO port pin or UART RX input General purpose IO port pin or rotary switch counter input General purpose IO port pin or rotary switch counter input General purpose IO port pin or UART clock output Buzzer output with level control General purpose IO port pin or 50/60Hz AC detection input General purpose IO port pin FM input clock AM input clock IF input clock DTS PLL control voltage output 3.3V IO power supply 75kHz oscillator output 75kHz oscillator input Ground General purpose IO port pin General purpose IO port pin General purpose IO port pin or buzzer output General purpose IO port pin or buzzer output MCU external interrupt input pin MCU external interrupt input pin MCU external interrupt input pin MCU external interrupt input pin 1.8V core supply Ground General purpose IO port pin or remote receiver input I2C bus data I2C bus clock General purpose IO port pin General purpose IO port pin or SPI data output General purpose IO port pin or SPI clock General purpose IO port pin or SPI chip select General purpose IO port pin or SPI data input General purpose IO port pin General purpose IO port pin General purpose IO port pin or emulator data output USB transceiver negative data pin USB transceiver positive data pin 3.3V IO power supply 16.9344MHz oscillator output 16.9344MHz oscillator input Ground Active low chip test enable PLL filter 1.8V supply for PLL Analog ground for PLL 1.8V core supply Ground Active low chip reset input Flash chip select Memory data bus Memory data bus Memory data bus Memory data bus Memory data bus Memory data bus Memory data bus Memory data bus Active low chip test enable or emulator reset input Active low chip test enable or emulator data clock input Active low chip test enable or emulator serial data input General purpose IO port General purpose IO port P Revision 0.5 Page 5 of 11 September 01, 2008 AP702 USB Host and PLL Interface with DSP and MCU Controller 8. EXTERNAL MEMORY CONFIGURATION 8.1 Supporting Memory Devices Memory Device Configurations 8 bits 64k x 8 128k x 8 256k x 8 512k x 8 1M x 8 2M x 8 8M x 8 16M x 8 32M x 8 512k x 8 2M x 8 4 bits NOR Flash - SDRAM - EDO 1M x 4 4M x 4 16 bits Number of support device - 1 1M x 16 4M x 16 8M x 16 16M x 16 1 - 2 8.2 External Memory Connection QFP128 Pin No. Pin Name 115 116 117 118 119 120 121 122 123 2 3 4 5 6 7 10 11 12 13 14 15 16 17 18 19 22 23 24 25 26 27 36 37 38 39 40 41 FCSB MD[0] MD[1] MD[2] MD[3] MD[7] MD[6] MD[5] MD[4] P0[3]/LCMCS FWEB/DQML/LCASB RWEB CASB FOEB/DQHM/HCASB RAMCLK RAMCKE/OEB RAS0B CSB/RAS1B MA14/CFG3 MA11/CFG0 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0 MA10 MA12/CFG1 MA13/CFG2 MA15 MA16/P10[0] MA17/P10[1] MA18/P10[2] Data RAM NOR Flash SDRAM EDO D0/D8 D1/D9 D2/D10 D3/D11 D7/D15 D6/D14 D5/D13 D4/D12 D0 D1 D2 D3 D7 D6 D5 D4 CS# D0 D1 D2 D3 D7 D6 D5 D4 DQML WE# CAS# DQMH CLK CKE RAS# CS# CAS# WE# CAS# OE# LCM D0 D1 D2 D3 D7 D6 D5 D4 CS OE# RAS# (device 1) RAS# (device 2) A11 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A10 A12 (BA1) A13 (BA0) A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A10 A14 A11 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A10 A12 A13 A15 A16 A17 A18 A0 P Revision 0.5 Page 6 of 11 September 01, 2008 AP702 USB Host and PLL Interface with DSP and MCU Controller 9. ELECTRICAL SPECIFICATION 9.1 Absolute Maximum Ratings Under no circumstances the absolute maximum ratings given below should be violated. Caution: exceeding one or more of the limiting values may cause permanent damage to the device. Parameter Symbol Rating Power Supply Voltage (IO) VCCIO Power Supply Voltage (Core) Unit -0.3 to 4.0 V VDD -0.3 to 2.16 V AVDD -0.3 to 2.16 V Input Voltage VIN -0.3 to 4.0 V Power Dissipation (Ta = 70°C) Pd TBD mW TSTG -40 to 150 °C IIN 20 mA IOUT 20 mA Power Supply Voltage (analog) Storage Temperature DC input current for each I/O pin Output short circuit current for each I/O pin 9.2 Recommended Operating Condition Parameter Symbol Min. Typ. Max. Unit Power Supply Voltage (IO) VCCIO 3.0 3.3 3.6 V Power Supply Voltage (Core Logic) VDD 1.62 1.8 1.98 V AVDD 1.62 1.8 1.98 V Input Voltage (Digital) VIN 0 - VCCIO V Input Voltage (Analog) VIN 0 - AVDD V Operating Temperature TOPR -20 - +85 °C Power Supply Voltage (Analog) 9.3 Electrical Characteristics (VCCIO=3.3V±10%, VDD=1.8V±10%, AVDD=1.8V±10%, Operating temperature = 0°C - 70°C) Symbol Parameter Condition Min. Typ. Max. Unit VIH Input High Voltage 2.0 - - V VIL Input Low Voltage - - 0.8 V RPU Pull-Up Resistance 10 12 18 Vina FMIN,AMIN,IFIN Input Voltage IOL1 Low Level Output Current for 4mA Pins VOL = 0.4V VCCIO = 3.3V 4 - mA IOL2 Low Level Output Current for 8mA Pins VOL = 0.4V VCCIO = 3.3V 8 - mA 1 High Level Output Current for 4mA Pins VOH = VCCIO – 0.4V VCCIO = 3.3V 4 - mA 2 High Level Output Current for 8mA Pins VOH = VCCIO – 0.4V VCCIO = 3.3V 8 - mA Idd_opr Core operating Current Idd @ VDD Full Functional Mode, DSP Run at 96 MHz - 30 - mA Idd_idle Power Down Current Idd @ VDD STOP Mode VCCIO = 3.6V VDD = 1.98V - 300 800 μA IOH IOH VIN = 0V, VCCIO = 3.3V 150 kΩ mVpp P Revision 0.5 Page 7 of 11 September 01, 2008 AP702 USB Host and PLL Interface with DSP and MCU Controller 10. PACKAGE INFORMATION Figure 3. LQFP Package Dimension Drawing P Revision 0.5 Page 8 of 11 September 01, 2008 AP702 USB Host and PLL Interface with DSP and MCU Controller 11. SOLDERING INDICATION This section gives a very brief insight to a complex technology. There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 1. Reflow Soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stenciling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 220 °C for thick/large packages, and below 235 °C for small/thin packages. 2. Wave Soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used, the following conditions must be observed for optimal results: z Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. z For packages with leads on two sides and a pitch: – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. z For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 3. Manual Soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. P Revision 0.5 Page 9 of 11 September 01, 2008 AP702 USB Host and PLL Interface with DSP and MCU Controller 4. Suitability of Surface Mount IC Packages for Wave and Reflow Soldering Methods Package BGA, HBGA, LFBGA, SQFP, TFBGA HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, SMS PLCC (3), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Soldering Method Wave Reflow (1) (2) Not suitable Suitable Not suitable Suitable Suitable Suitable Not recommended (3)(4) Suitable Not recommended (5) Suitable Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch equal to or smaller than 0.5 mm. P Revision 0.5 Page 10 of 11 September 01, 2008 AP702 USB Host and PLL Interface with DSP and MCU Controller Valence Semiconductor Design Limited Unit 2001, 20/F, APEC Plaza, 49 Hoi Yuen Road, Kwun Tong, Hong Kong Tel: (852) 2797 3288 Fax: (852) 2776 7770 Email: [email protected] Website: http://www.valencetech.com IMPORTANT NOTICE “Preliminary” product information describes products that are in production, but for which full characterization data is not yet available. ValenceTech Ltd. and its affiliates (“Valence”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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