TPS53321 www.ti.com SLUSAF3 – DECEMBER 2010 5-A Step-Down Regulator with Integrated Switcher Check for Samples: TPS53321 FEATURES LOW VOLTAGE APPLICATIONS • • • • • • 1 2 • • • • • • • • • • • • • 96% Maximum Efficiency Continuous 5-A Output Current Supports All MLCC Output Capacitor SmoothPWM™ Auto-Skip Eco-mode™ for Light-Load Efficiency Optimized Efficiency at Light and Heavy Loads Voltage Mode Control Supports Master-Slave Interleaved Operation Synchronization up to ±20% of Nominal Frequency Conversion Voltage Range Between 2.9 V and 6.0 V Soft-Stop Output Discharge During Disable Adjustable Output Voltage Ranging Between 0.6 V and 0.84 V × VIN Overcurrent, Overvoltage and Over-Temperature Protection Small 3 × 3 , 16-Pin QFN Package Open-Drain Power Good Indication Internal Boot Strap Switch Low RDS(on), 24 mΩ with 3.3-V Input and 19-mΩ with 5-V Input Supports Pre-bias Start-Up 5-V Step-down Rail 3.3-V Step-down Rail DESCRIPTION The TPS53321 provides a fully integrated 3-V to 5-V VIN integrated synchronous FET converter solution with 16 total components, in 200 mm2 of PCB area. Due to the low on-resistance and TI's Proprietary SmoothPWM™ Skip mode of operation, it enables 96% peak efficiency, and over 90% efficiency at loads as light as 100 mA. It requires only two 22-µF ceramic output capacitors for a power dense 5-A solution. The TPS53321 features a 1.1-MHz switching frequency, skip mode operation support, pre-bias startup, internal softstart, output soft discharge, internal VBST switch, power good, EN/input UVLO, overcurrent, overvoltage, undervoltage and over-temperature protections and all ceramic output capacitor support. It supports supply voltage from 2.9 V to 3.5 V and conversion voltage from 2.9 V to 6.0 V, and output voltage is adjustable from 0.6 V to 0.84 V × VIN. The TPS53321 is available in the 3 mm × 3 mm 16-pin QFN package (Green RoHs compliant and Pb free) and operates between –40°C and 85°C. TYPICAL APPLICATION CIRCUIT Output All MLCCs VIN 2.9 V to 6 V VDD 2.9 V to 3.5 V 13 14 5 VIN VIN 6 7 CBST SW SW SW 12 VDD VBST 4 PGD 3 VIN 11 AGND SYNC 2 SYNC EN 1 EN 8 PS TPS53321 PGD FB 10 PGND PGND 15 Pad COMP 9 16 UDG-10204 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SmoothPWM, Eco-mode are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010, Texas Instruments Incorporated TPS53321 SLUSAF3 – DECEMBER 2010 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION TA PACKAGE –40°C to 85°C Plastic QFN (RGT) ORDERABLE DEVICE NUMBER PINS OUTPUT SUPPLY MINIMUM QUANTITY TPS53321RGTR 16 Tape and reel 3000 TPS53321RGTT 16 Mini reel 250 ECO PLAN Green (RoHS and no Pb/Br) ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) VALUE MIN Input voltage range VIN, EN –0.3 7 VBST –0.3 17 VBST(with respect to SW) –0.3 7 FB, PS, VDD –0.3 3.7 DC –0.3 7 –3 10 PGD –0.3 7 COMP, SYNC –0.3 3.7 PGND –0.3 SW Output voltage range Electrostatic Discharge UNIT MAX Pulse < 20ns, E= 5mJ V V 0.3 Human Body Model (HBM) 2000 Charged Device Model (CDM) V 500 Ambient temperature TA –40 85 ˚C Storage temperature Tstg –55 150 ˚C Junction temperature TJ –40 150 ˚C 300 ˚C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds (1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS VALUE MIN Input voltage range 3.3 3.5 2.9 VDD 2.9 VBST –0.1 13.5 VBST(with respect to SW) –0.1 6 EN –0.1 6 FB, PS –0.1 3.5 –1 6.5 –0.1 6 COMP, SYNC –0.1 3.5 PGND –0.1 0.1 –40 125 Submit Documentation Feedback UNIT 6 PGD Junction temperature range, TJ 2 MAX VIN SW Output voltage range NOM V V °C Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TPS53321 TPS53321 www.ti.com SLUSAF3 – DECEMBER 2010 PACKAGE DISSIPATION RATINGS PACKAGE THERMAL IMPEDANCE, JUNCTION TO THERMAL PAD THERMAL IMPEDANCE, JUNCTION TO CASE THERMAL IMPEDANCE, JUNCTION TO AMBIENT 16-Pin Plastic QFN (RGT) 5°C/W 16°C/W 40°C/W Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TPS53321 3 TPS53321 SLUSAF3 – DECEMBER 2010 www.ti.com ELECTRICAL CHARACTERISTICS over recommended free-air temperature range, VIN = 3.3 V, VVDD = 3.3 V, PGND = GND (Unless otherwise noted). PARAMETER CONDITIONS MIN TYP MAX UNIT SUPPLY: VOLTAGE, CURRENTS, and UVLO VIN VIN supply voltage Nominal input voltage range IVINSDN VIN shutdown current EN = 'LO' 2.9 VUVLO VIN UVLO threshold Ramp up; EN = 'HI' 2.8 V VUVLOHYS VIN UVLO hysteresis VIN UVLO Hysteresis 130 mV VDD Internal circuitry supply voltage Nominal 3.3-V input voltage range IDDSDN VDD shut down current EN = 'LO' IDD Standby current EN = 'HI', no switching 2.2 VDDUVLO 3.3V UVLO threshold Ramp up; EN =’HI’ 2.8 V VDDUVLOHYS 3.3V UVLO hysteresis 75 mV 2.9 3.3 6.0 V 3 µA 3.5 V 5 µA 3.5 mA VOLTAGE FEEDBACK LOOP: VREF AND ERROR AMPLIFIER VVREF VREF TOLVREF VREF Tolerance UGBW (1) Unity gain bandwidth AOL (1) Internal precision reference voltage 0.6 0°C ≤ TA ≤ 85°C –40°C ≤ TA ≤ 85°C V –1% 1% –1.25% 1.25% 14 Open loop gain MHz 80 IFBINT FB input leakage current Sourced from FB pin IEAMAX (1) Output sinking and sourcing current CCOMP = 20 pF SR (1) Slew rate dB 30 nA 5 mA 5 V/µs OCP: OVERCURRENT AND ZERO CROSSING IOCPL Overcurrent limit on upper FET When IOUT exceeds this threshold for 4 consecutive cycles. VIN=3.3 V, VOUT=1.5 V with 1-µH inductor, TA = 25°C IOCPH One time overcurrent latch off on the lower FET Immediately shut down when sensed current reach this value. VIN=3.3 V, VOUT=1.5 V with 1-µH inductor, TA = 25°C tHICCUP Hiccup time interval VZXOFF (1) Zero crossing comparator internal offset PGND – SW, skip mode 6.0 6.5 7.0 A 6.25 6.80 7.35 A 12.5 14.5 16.5 ms –4.5 –3.0 –1.5 mV PROTECTION: OVP, UVP, PGD, AND INTERNAL THERMAL SHUTDOWN VOVP Overvoltage protection threshold voltage Measured at FB w/r/t VREF 114% 117% 120% VUVP Undervoltage protection threshold voltage Measured at FB w/r/t VREF 80% 83% 86% VPGDL PGD low threshold Measured at FB w/r/t VREF 80% 83% 86% VPGDU PGD upper threshold Measured at FB w/r/t VREF. 114% 117% 120% VINMINPG Minimum Vin voltage for valid PGD at start up. Measured at VIN with 1-mA (or 2-mA) sink current on PGD pin at start up Thermal shutdown Latch off controller, attempt soft-stop Thermal Shutdown hysteresis Controller restarts after temperature has dropped THSD (1) THSDHYS (1) 4 (1) 1 130 140 40 V 150 °C °C Ensured by design. Not production tested. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TPS53321 TPS53321 www.ti.com SLUSAF3 – DECEMBER 2010 ELECTRICAL CHARACTERISTICS (continued) over recommended free-air temperature range, VIN = 3.3 V, VVDD = 3.3 V, PGND = GND (Unless otherwise noted). PARAMETER CONDITIONS MIN TYP MAX UNIT 0.2 0.4 V 0 2 µA LOGIC PINS: I/O VOLTAGE AND CURRENT VPGPD PGD pull down voltage Pull-down voltage with 4-mA sink current IPGLK PGD leakage current Hi-Z leakage current, apply 3.3-V in off state RENPU Enable pull up resistor VENH EN logic high threshold VENHYS EN hysteresis –2 1.35 1.10 Level 1 to level 2 (2) PSTHS PS mode threshold voltage MΩ 1.18 1.30 V 0.18 0.24 V 0.12 Level 2 to level 3 0.4 Level 3 to level 4 0.8 Level 4 to level 5 1.4 Level 5 to level 6 2.2 IPS PS source 10-µA pull-up current when enabled. 8 fSYNCSL Slave SYNC frequency range Versus nominal switching frequency –20% PWSYNC SYNC low pulse width 110 ns ISYNC SYNC pin sink current TA = 25°C 10 µA SYNC threshold Falling edge 1.0 V 0.5 V (3) VSYNCTHS VSYNCHYS (3) SYNC hysteresis 10 V 12 µA 20% BOOT STRAP: VOLTAGE AND LEAKAGE CURRENT IVBSTLK VBST leakage current VIN = 3.3V, VVBST = 6.6 V, TA = 25°C 1 µA TIMERS: SS, FREQUENCY, RAMP, ON-TIME AND I/O TIMING tSS_1 Delay after EN asserting EN = 'HI', master or HEF mode 0.2 ms tSS_2 Delay after EN asserting EN = 'HI', slave waiting time 0.5 ms tSS_3 Soft-start ramp-up time Rising from VSS = 0 V to VSS = 0.6 V 0.4 ms tPGDENDLY PGD startup delay time Rising from VSS = 0 V to VSS = 0.6 V, from VSS reaching 0.6 V to VPGD going high 1.2 ms tOVPDLY Overvoltage protection delay time Time from FB out of +20% of VREF to OVP fault tUVPDLY Undervoltage protection delay time Time from FB out of -20% of VREF to UVP fault fSW Switching frequency control FCCM Ramp amplitude (3) 2.9 V < VIN < 6.0 V VIN/4 FCCM or DE mode 100 140 HEF mode 175 250 tMIN(off) DMAX RSFTSTP (2) (3) Minimum OFF time Maximum duty cycle, FCCM and DE mode Maximum duty cycle, HEF mode Soft-discharge transistor resistance 1.0 1.7 2.5 11 0.99 1.1 84% 89% 75% 81% µs µs 1.21 MHz V ns fSW = 1.1 MHz, 0°C ≤ TA ≤ 85°C VEN = Low, VIN = 3.3 V, VOUT = 0.5 V 60 Ω See PS pin description for levels. Ensured by design. Not production tested. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TPS53321 5 TPS53321 SLUSAF3 – DECEMBER 2010 www.ti.com EN 1 SYNC 2 PGND PGND VIN VIN RGT Package (Top View) 16 15 14 13 12 VDD 11 AGND TPS53321 VBST 4 9 COMP 5 6 7 8 PS FB SW 10 SW 3 SW PGD PIN FUNCTIONS I/O (1) PIN DESCRIPTION NAME NO. AGND 11 G Device analog ground terminal. COMP 9 O Error amplifier compensation terminal. Type III compensation method is recommended for stability. EN 1 I Enable. Internally pulled up to VDD with a 1.35-MΩ resistor. FB 10 I Voltage feedback. Also used for OVP, UVP and PGD determination. PGD 3 O Power good output flag. Open drain output. Pull up to an external rail via a resistor. P IC power GND terminal. PGND 15 16 PS 8 I Mode configuration pin (with 10 µA current): Connecting to ground: FCCM slave Pulled high or floating (internal pulled high): FCCM master Connect a 24.3-kΩ resistor to GND: DE slave Connect a 57.6-kΩ resistor to GND: HEF mode Connect a 105-kΩ resistor to GND : reserved mode Connect a 174-kΩ resistor to GND: DE master SYNC 2 B Synchronization signal for input interleaving. Master SYNC pin sends out 180° out-of-phase signal to slave SYNC. SYNC frequency must be within ±20% of slave nominal frequency. B Output inductor connection to integrated power devices. 5 SW 6 7 VBST 4 P Supply input for high-side MOSFET (bootstrap terminal). Connect capacitor from this pin to SW terminal. VDD 12 P Input bias supply for analog functions. P Gate driver supply and power conversion voltage input. VIN (1) 6 13 14 I – Input; B – Bidirectional; O – Output; G – Ground; P – Supply (or Ground) Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TPS53321 TPS53321 www.ti.com SLUSAF3 – DECEMBER 2010 FUNCTIONAL BLOCK DIAGRAM 0.6 V–17% UV/OV Threshold Generation 0.6 V + 0.6 V+17% VIN 14 13 + OV Control Logic HDRV PWM + COMP 9 E/A 0.6 V + Ramp 4 VBST 5 SW 6 SW 7 SW VIN UVLO UV FB 10 VIN + XCON PWM LL One-Shot Overtemp VOUT Discharge SS LDRV 15 PGND 16 PGND OSC Enable Control OCP Logic Mode Scanner VDD UVLO 12 VDD 2 1 8 3 11 SYNC EN PS PGD AGND TPS53321 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TPS53321 UDG-10205 7 TPS53321 SLUSAF3 – DECEMBER 2010 www.ti.com TYPICAL CHARACTERISTICS 100 95 95 90 90 Efficiency (%) Efficiency (%) Inductor PCMC065T-1R0 (1 µH, 5.6 mΩ) is used. 100 85 80 VOUT = 1.0 V VOUT = 1.2 V VOUT = 1.5 V VOUT = 1.8 V VOUT = 2.5 V 75 70 0.0 0.5 1.0 1.5 4.0 4.5 95 95 90 90 Efficiency (%) 100 VOUT = 1.0 V VOUT = 1.2 V VOUT = 1.5 V VOUT = 1.8 V VOUT = 2.5 V VOUT = 3.3 V 80 75 70 0.0 0.5 1.0 1.5 4.0 4.5 1.0 1.5 2.0 2.5 3.0 3.5 Output Current (A) 4.0 4.5 5.0 85 VOUT = 1.0 V VOUT = 1.2 V VOUT = 1.5 V VOUT = 1.8 V VOUT = 2.5 V VOUT = 3.3 V 80 75 Skip Mode VIN = 5 V 2.0 2.5 3.0 3.5 Output Current (A) 0.5 FCCM VIN = 3.3 V Figure 2. Efficiency vs. Output Current, FCCM, VIN = 3.3 V 100 85 VOUT = 1.0 V VOUT = 1.2 V VOUT = 1.5 V VOUT = 1.8 V VOUT = 2.5 V 70 0.0 5.0 Figure 1. Efficiency vs. Output Current, Skip Mode, VIN = 3.3 V Efficiency (%) 80 75 Skip Mode VIN = 3.3 V 2.0 2.5 3.0 3.5 Output Current (A) 85 70 0.0 5.0 Figure 3. Efficiency vs. Output Current, Skip Mode, VIN = 5 V 0.5 1.0 1.5 FCCM VIN = 5 V 2.0 2.5 3.0 3.5 Output Current (A) 4.0 4.5 5.0 Figure 4. Efficiency vs. Output Current, FCCM, VIN = 5 V 0.620 0.5 Output Voltage Change (%) Feedback Voltage (V) 0.615 0.610 0.605 0.600 0.595 0.590 0.3 0.1 −0.1 −0.3 VIN = 3.3 V VIN = 5.0 V 0.585 0.580 −40 −25 −10 5 20 35 50 65 Temperature (°C) 80 95 110 125 Figure 5. Feedback Voltage vs. Ambient Temperature 8 −0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 Output Current (A) 4.0 4.5 5.0 Figure 6. Output Voltage Change vs. Output Current Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TPS53321 TPS53321 www.ti.com SLUSAF3 – DECEMBER 2010 TYPICAL CHARACTERISTICS (continued) Inductor PCMC065T-1R0 (1 µH, 5.6 mΩ) is used. 10000 10000 VIN = 5.0 V Frequency (kHz) Frequency (kHz) VIN = 3.3 V 1000 100 1000 100 FCCM HEF Mode DE Mode 10 0.01 0.1 1 Output Current (A) 10 Figure 7. Frequency vs. Output Current at VIN = 3.3 V HEF Mode VIN = 3.3 V IOUT = 0 A EN (5 V/div) VOUT (1 V/div) FCCM HEF Mode DE Mode 10 0.01 0.1 1 Output Current (A) 10 Figure 8. Frequency vs. Output Current at VIN = 5.0 V HEF Mode VIN = 3.3 V IOUT = 0 A EN (5 V/div) 0.5 V pre-biased PGD (5 V/div) t – Time – 200 ms/div VOUT (1 V/div) PGD (5 V/div) t – Time – 200 ms/div Figure 9. Normal Start Up Waveform Figure 10. Pre-Bias Start Up Waveform Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TPS53321 9 TPS53321 SLUSAF3 – DECEMBER 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) Inductor PCMC065T-1R0 (1 µH, 5.6 mΩ) is used. EN (5 V/div) HEF Mode VIN = 3.3 V IOUT = 0 A 90 VOUT (1 V/div) PGD (5 V/div) Temperature (°C) 80 70 No Air Flow 60 50 40 30 VIN = 5 V @ VOUT = 0.6 V VOUT = 1.2 V VOUT = 1.8 V VOUT = 2.5 V VOUT = 3.3 V VIN = 3.3 V @ VOUT = 0.6 V VOUT = 1.2 V VOUT = 1.8 V VOUT = 2.5 V 20 0.0 0.5 t – Time – 4 ms/div Figure 11. Soft-Stop Waveform 10 Submit Documentation Feedback 1.0 1.5 2.0 2.5 3.0 Output Current (A) 3.5 4.0 4.5 5.0 Figure 12. Safe Operating Area Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TPS53321 TPS53321 www.ti.com SLUSAF3 – DECEMBER 2010 APPLICATION INFORMATION Application Circuit Diagram L1 1 mH Output all MLCCs VIN C5 22 mF R6 2.2 W C6 0.1 mF C8 1 mF 13 14 VIN VIN 5 6 7 C4 VIN 0.1 mF SW SW SW 12 VDD VBST 4 PGD 3 R7 20 kW 11 AGND TPS53321 SYNC EN 2 SYNC 1 EN 8 PS FB 10 R5 57.6 kW PGND PGND COMP 15 COUT 3 x 22 mF PGD R3 20 W R4 C2 2.2 nF 4.02 kW R1 9 4.02 kW R2 4.02 kW C3 100 pF 16 C1 2.2 nF UDG-10206 Figure 13. Typical 3.3-V input Application Circuit Diagram Overview The TPS53321 is a high-efficiency switching regulator with two integrated N-channel MOSFETs and is capable of delivering up to 5 A of load current. The TPS53321 provides output voltage between 0.6 V and 0.84 × VIN from 2.9 V to 6.0 V wide input voltage range. This device employs five operation modes to fit various application needs. The master/slave mode enables a two-phase interleaved operation to reduce input ripple. The skip mode operation provides reduced power loss and increases the efficiency at light load. The unique, patented PWM modulator enables smooth light load to heavy load transition while maintaining fast load transient. Operation Modes The TPS53321 offers five operation modes determined by the PS pin connections listed in Table 1. Table 1. Operation Mode Selection PS PIN CONNECTION OPERATION MODE GND FCCM Slave AUTO-SKIP AT LIGHT LOAD MASTER/SLAVE SUPPORT Slave 24.3 kΩ to GND DE Slave Yes 57.6 kΩ to GND HEF Mode Yes 174 kΩ to GND DE Master Yes Floating or pulled to VDD FCCM Master Slave Master Master In forced continuous conduction mode (FCCM), the high-side FET is ON during the on-time and the low-side FET is ON during the off-time. The switching is synchronized to the internal clock thus the switching frequency is fixed. In diode emulation (DE) mode, the high-side FET is ON during the on-time and low-side FET is ON during the off-time until the inductor current reaches zero. An internal zero-crossing comparator detects the zero crossing of inductor current from positive to negative. When the inductor current reaches zero, the comparator sends a signal to the logic control and turns off the low-side FET. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TPS53321 11 TPS53321 SLUSAF3 – DECEMBER 2010 www.ti.com When the load is increased, the inductor current is always positive and the zero-crossing comparator does not send a zero-crossing signal. The converter enters into continuous conduction mode (CCM) when no zero-crossing is detected for two consecutive PWM pulses. The switching synchronizes to the internal clock and the switching frequency is fixed. In high-efficiency (HEF) mode, the operation is the same as DE mode at light load. However, the converter does not synchronize to the internal clock during CCM. Instead, the PWM modulator determines the switching frequency. Eco-mode™ Light-Load Operation In skip modes (DE and HEF) when the load inductor current becomes negative by the end turned off when the inductor current reaches increased compared to the normal PWM mode loss is reduced, thereby improving efficiency. current is less than one-half of the inductor peak current, the of off-time. During light load operation, the low-side MOSFET is zero. The energy delivered to the load per switching cycle is operation and the switching frequency is reduced. The switching In both DE and HEF mode, the switching frequency is reduced in discontinuous conduction mode (DCM). When the load current is 0 A, the minimum switching frequency is reached. The difference between VVBST and VSW must be maintained at a value higher than 2.4 V. Forced Continuous Conduction Mode (FCCM) When the PS pin is grounded or greater than 2.2 V, the TPS53321 is operating in forced continuous conduction mode in both light-load and heavy-load conditions. In this mode, the switching frequency remains constant over the entire load range, making it suitable for applications that need tight control of switching frequency at a cost of lower efficiency at light load. Soft-Start The soft-start function reduces the inrush current during the start up sequence. A slow-rising reference voltage is generated by the soft-start circuitry and sent to the input of the error amplifier. When the soft-start ramp voltage is less than 600 mV, the error amplifier uses this ramp voltage as the reference. When the ramp voltage reaches 600 mV, the error amplifier switches to a fixed 600-mV reference. The typical soft-start time is 400 µs. Power Good The TPS53321 monitors the voltage on the FB pin. If the FB voltage is between 83% and 117% of the reference voltage, the power good signal remains high. If the FB voltage falls outside of these limits, the internal open drain output pulls the power good pin (PGD) low. During start-up, VIN must be higher than 1 V in order to have valid power good logic, and the power good signal is delayed for 1.2 ms after the FB voltage falls to within the power good limits. There is also 10-µs delay during the shut down sequence. Undervoltage Lockout (UVLO) Protection The TPS53321 provides undervoltage lockout (UVLO) protection for both power input (VIN) and bias input (VDD) voltage. If either of them is lower than the UVLO threshold voltage minus the hysteresis, the device shuts off. When the voltage rises above the threshold voltage, the device restarts. The typical UVLO rising threshold is 2.8 V for both VIN and VVDD. A hysteresis voltage of 130 mV for VIN and 75 mV for VVDD is also provided to prevent glitch. Overcurrent Protection The TPS53321 continuously monitors the current flowing through the high-side and the low-side MOSFETs. If the current through the high-side FET exceeds 6.5 A, the high-side FET turns off and the low-side FET turns on until the next PWM cycle. An overcurrent (OC) counter starts to increment each occurrence of an overcurrent event. The converter shuts down immediately when the OC counter reaches four. The OC counter resets if the detected current is less 6.5 A after an OC event. 12 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TPS53321 TPS53321 www.ti.com SLUSAF3 – DECEMBER 2010 Another set of overcurrent circuitry monitors the current flowing through low-side FET. If the current through the low-side FET exceeds 6.8 A, the overcurrent protection is enabled and immediately turns off both the high-side and the low-side FETs and shuts down the converter. The device is fully protected against overcurrent during both on-time and off-time. The device attempts to restart after a hiccup delay of 14.5 ms (typical). If the overcurrent condition clears before restart, the device starts up normally. Overvoltage Protection The TPS53321 monitors the voltage divided feedback voltage to detect overvoltage and undervoltage conditions. When the feedback voltage is greater than 117% of the reference, the high-side MOSFET turns off and the low-side MOSFET turns on. The output voltage then drops until it reaches the undervoltage threshold. At that point the low-side MOSFET turns off and the device enters a high-impedance state. Undervoltage Protection When the feedback voltage is lower than 83% of the reference voltage, the undervoltage protection timer starts. If the feedback voltage remains lower than the undervoltage threshold voltage after 10 ms, the device turns off both the high-side and the low-side MOSFETs and goes into a high-impedance state. The device attempts to restart after a hiccup delay of 14.5 ms (typical). Overtemperature Protection The TPS53321 continuously monitors the die temperature. If the die temperature exceeds the threshold value (140˚C typical), the device shuts off. When the device temperature falls to 40˚C below the overtemperature threshold, it restarts and returns to normal operation. Output Discharge When the enable pin is low, the TPS53321 discharges the output capacitors through an internal MOSFET switch between SW and PGND while high-side and low-side MOSFETs remain off. The typical discharge switch-on resistance is 60 Ω. This function is disabled when VIN is less than 1 V. Master/Slave Operation and Synchronization Two TPS53321 can operate interleaved when configured as master/slave. The SYNC pins of the two devices are connected together for synchronization. In CCM, the master device sends the 180° out-of-phase pulse to the slave device through the SYNC pin, which determines the leading edge of the PWM pulse. If the slave device does not receive the SYNC pulse from the master device or if the SYNC connection is broken during operation, the slave device continues to operate using its own internal clock. In DE mode, the master/slave switching node does not synchronize to each other if either one of them is operating in DCM. When both master and slave enter CCM, the switching nodes of the master and the slave synchronize to each other. The SYNC pin of the slave device can also connect to external clock source within ±20% of the 1.1-MHz switching frequency. The falling edge of the SYNC triggers the rising edge of the PWM signal. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TPS53321 13 TPS53321 SLUSAF3 – DECEMBER 2010 www.ti.com External Components Selection 1. DETERMINE THE VALUE OF R1 AND R2 The output voltage is programmed by the voltage-divider resistor, R1 and R2 shown in Figure 13. R1 is connected between the FB pin and the output, and R2 is connected between the FB pin and GND. The recommended value for R1 is from 1 kΩ to 5 kΩ. Determine R2 using equation in Equation 1. 0.6 R2 = ´ R1 VOUT - 0.6 (1) 2. CHOOSE THE INDUCTOR The inductance value should be determined to give the ripple current of approximately 20% to 40% of maximum output current. The inductor ripple current is determined by Equation 2: IL(ripple ) = (VIN - VOUT )´ VOUT 1 ´ L ´ fSW VIN (2) The inductor also needs to have low DCR to achieve good efficiency, as well as enough room above peak inductor current before saturation. 3. CHOOSE THE OUTPUT CAPACITOR(S) The output capacitor selection is determined by output ripple and transient requirement. When operating in CC mode, the output ripple has three components: VRIPPLE = VRIPPLE(C ) + VRIPPLE(ESR ) + VRIPPLE(ESL ) (3) VRIPPLE(C ) = IL(ripple ) 8 ´ COUT ´ fSW (4) VRIPPLE(ESR ) = IL(ripple ) ´ ESR (5) V ´ ESL VRIPPLE(ESL ) = IN L (6) When ceramic output capacitors are used, the ESL component is usually negligible. In the case when multiple output capacitors are used, ESR and ESL should be the equivalent of ESR and ESL of all the output capacitor in parallel. When operating in DCM, the output ripple is dominated by the component determined by capacitance. It also varies with load current and can be expressed as shown in Equation 7. 2 VRIPPLE(DCM) = (a ´ I ( L ripple ) - IOUT ) 2 ´ COUT ´ fSW ´ IL(ripple ) where • a= 14 a is the DCM on-time coefficient and can be expressed in Equation 8 (typical value 1.25) (7) tON(DCM) tON(CCM) (8) Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TPS53321 TPS53321 www.ti.com SLUSAF3 – DECEMBER 2010 IL VOUT a x IL(ripple) VRIPPLE IOUT T1 axT UDG-10055 Figure 14. DCM VOUT Ripple Calculation 4. CHOOSE THE INPUT CAPACITOR The selection of input capacitor should be determined by the ripple current requirement. The ripple current generated by the converter needs to be absorbed by the input capacitors as well as the input source. The RMS ripple current from the converter can be expressed in Equation 9. IIN(ripple ) = IOUT ´ D ´ (1 - D ) where • D is the duty cycle and can be expressed as shown in Equation 10 (9) V D = OUT VIN (10) To minimize the ripple current drawn from the input source, sufficient input decoupling capacitors should be placed close to the device. The ceramic capacitor is recommended because it provides low ESR and low ESL. The input voltage ripple can be calculated as shown in Equation 11 when the total input capacitance is determined. ´D I VIN(ripple ) = OUT fSW ´ CIN (11) 5. COMPENSATION DESIGN The TPS53321 uses voltage mode control. To effectively compensate the power stage and ensure fast transient response, Type III compensation is typically used. The control to output transfer function can be described in Equation 12. 1 + s ´ COUT ´ ESR GCO = 4 ´ æ ö L + COUT ´ (ESR + DCR) ÷ + s2 ´ L ´ COUT 1+ s ´ ç è DCR + RLOAD ø (12) The output L-C filter introduces a double pole which can be calculated as shown in Equation 13. 1 fDP = 2 ´ p ´ L ´ COUT (13) The ESR zero can be calculated as shown in Equation 14. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TPS53321 15 TPS53321 SLUSAF3 – DECEMBER 2010 fESR = www.ti.com 1 2 ´ p ´ ESR ´ COUT (14) Figure 15 and Figure 16 show the configuration of Type III compensation and typical pole and zero locations. Equation 16 through Equation 20 describe the compensator transfer function and poles and zeros of the Type III network. C3 C1 C2 R4 R3 R2 COMP + VREF Gain (dB) R1 UGD-10058 fZ1 fZ2 fP2 fP3 Frequency UDG-10057 Figure 15. Type III Compensation Network Configuration Schematic GEA = Figure 16. Type III Compensation Gain Plot and Zero/Pole Placement (1 + s ´ C1 ´ (R1 + R3 ))(1 + s ´ R4 ´ C2 ) æ C ´C ö (s ´ R1 ´ (C2 + C3 ))´ (1 + s ´ C1 ´ R3 )´ ç 1 + s ´ R4 C 2 + C3 ÷ è 2 3 ø (15) 1 fZ1 = 2 ´ p ´ R 4 ´ C2 (16) 1 1 fZ2 = @ 2 ´ p ´ (R1 + R3 ) ´ C1 2 ´ p ´ R1 ´ C1 (17) fP1 = 0 (18) 1 fP2 = 2 ´ p ´ R3 ´ C1 (19) 1 1 fP3 = @ æ C2 ´ C3 ö 2 ´ p ´ R 4 ´ C3 2 ´ p ´ R4 ´ ç ÷ è C2 + C3 ø (20) The two zeros can be placed near the double pole frequency to cancel the response from the double pole. One pole can be used to cancel ESR zero, and the other non-zero pole can be placed at half switching frequency to attenuate the high frequency noise and switching ripple. Suitable values can be selected to achieve a compromise between high phase margin and fast response. A phase margin higher than 45 degrees is required for stable operation. For DCM operation, a C3 between 56 pF and 150 pF is recommended for output capacitance between 20 µF to 200 µF. 16 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TPS53321 TPS53321 www.ti.com SLUSAF3 – DECEMBER 2010 Figure 17 shows the master/slave configuration schematic for a design with a 3.3-V input. L1 1 mH Output all MLCCs VIN 3.3 V C5 22 mF C6 0.1 mF R6 2.2 W C8 1 mF 13 14 VIN VIN 5 6 7 12 VDD VBST 4 PGD 3 R7 20 kW PGD_Master R3 20 W 11 AGND TPS53321 EN_Master 2 SYNC 1 EN 8 PS FB 10 PGND PGND COMP 15 R1 9 4.02 kW R2 4.02 kW C3 100 pF 16 L11 1 mH Output all MLCCs C16 0.1 mF C18 1 mF R16 2.2 W 13 14 VIN VIN 5 6 7 VBST 4 PGD 3 R17 20 kW PGD_Master R13 20 W 11 AGND TPS53321 2 SYNC 1 EN 8 PS FB 10 PGND PGND COMP 15 R14 C12 2.2 nF 4.02 kW 9 16 VOUT = 1.5 V COUT 3 x 22 mF C14 VIN 0.1 mF SW SW SW 12 VDD EN_Slave C1 2.2 nF R4 C2 2.2 nF 4.02 kW VIN C15 22 mF COUT 3 x 22 mF C4 VIN 0.1 mF SW SW SW VOUT = 1.2 V C11 2.2 nF R11 4.02 kW R12 2.67 kW C13 100 pF UDG-10207 Figure 17. Master/Slave Configuration Schematic Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TPS53321 17 TPS53321 SLUSAF3 – DECEMBER 2010 www.ti.com Layout Considerations Good layout is essential for stable power supply operation. Follow these guidelines for a clean PCB layout: • Separate the power ground and analog ground planes. Connect them together at one location. • Use four vias to connect the thermal pad to power ground. • Place VIN and VDD decoupling capacitors as close to the device as possible. • Use wide traces for VIN, VOUT, PGND and SW. These nodes carry high current and also serve as heat sinks. • Place feedback and compensation components as close to the device as possible. • Keep analog signals (FB, COMP) away from noisy signals (SW, SYNC, VBST). • Refer to TPS53321 evaluation module for a layout example. Figure 18 shows and example layout for the TPS53321. GND Shape COMP FB AGND VDD VIN Shape VIN PS VIN SW PGND SW PGND SW SW VBST PGD SYNC EN VOUT GND Shape GND Via Etch under component Figure 18. TPS53321 Layout Example 18 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s) :TPS53321 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) TPS53321RGTR ACTIVE QFN RGT 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 3321 TPS53321RGTT ACTIVE QFN RGT 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 3321 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 Samples PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS53321RGTR QFN RGT 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS53321RGTT QFN RGT 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS53321RGTR QFN RGT 16 3000 367.0 367.0 35.0 TPS53321RGTT QFN RGT 16 250 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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