TI CSD86330Q3D

CSD86330Q3D
www.ti.com
SLPS264A – OCTOBER 2010 – REVISED DECEMBER 2010
Synchronous Buck NexFET™ Power Block
FEATURES
DESCRIPTION
•
•
•
•
•
The CSD86330Q3D NexFET™ power block is an
optimized design for synchronous buck applications
offering high current, high efficiency, and high
frequency capability in a small 3.3-mm × 3.3-mm
outline. Optimized for 5V gate drive applications, this
product offers a flexible solution capable of offering a
high density power supply when paired with any 5V
gate drive from an external controller/driver.
1
Half-Bridge Power Block
90% System Efficiency at 15A
Up To 20A Operation
High Frequency Operation (Up To 1.5MHz)
High Density – SON 3.3-mm × 3.3-mm
Footprint
Optimized for 5V Gate Drive
Low Switching Losses
Ultra Low Inductance Package
RoHS Compliant
Halogen Free
Pb-Free Terminal Plating
2
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•
•
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•
TEXT ADDED FOR SPACING
Top View
APPLICATIONS
•
Synchronous Buck Converters
– High Frequency Applications
– High Current, Low Duty Cycle Applications
Multiphase Synchronous Buck Converters
POL DC-DC Converters
IMVP, VRM, and VRD Applications
•
•
•
8
VSW
7
VSW
3
6
VSW
4
5
VIN
1
VIN
2
TG
TGR
PGND
(Pin 9)
BG
P0116-01
TEXT ADDED FOR SPACING
ORDERING INFORMATION
Device
Package
Media
Qty
Ship
CSD86330Q3D
SON
3.3-mm × 3.3-mm
Plastic Package
13-Inch
Reel
2500
Tape and
Reel
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
TYPICAL POWER BLOCK EFFICIENCY
and POWER LOSS
TYPICAL CIRCUIT
CSD86330Q3D
ENABLE
D1
BST
DRVH
G1
Control
FET
G1R
D2/S1
ENABLE
PWM
LL
PWM
GND
DRVL
G2
100
5
90
4
VI
VO
Sync
FET
S2
VGS = 5V
VIN = 12V
VOUT = 1.3V
fSW = 500kHz
LOUT = 1µH
T A = 25°C
80
70
3
2
Power Loss (W)
VDD
Efficiency (%)
Driver IC
VDD
S0474-04
60
1
Efficiency
Power Loss
50
0
5
10
Output Current (A)
15
0
20
G029
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NexFET is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
CSD86330Q3D
SLPS264A – OCTOBER 2010 – REVISED DECEMBER 2010
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS
TA = 25°C (unless otherwise noted) (1)
Parameter
Conditions
VALUE
UNIT
–0.8 to 25
V
TG to TGR
–8 to 10
V
BG to PGND
–8 to 10
V
60
A
6
W
VIN to PGND
Voltage range
Pulsed Current Rating, IDM
Power Dissipation, PD
Avalanche Energy EAS
Sync FET, ID = 65A, L = 0.1mH
211
Control FET, ID = 42A, L = 0.1mH
88
Operating Junction and Storage Temperature Range, TJ, TSTG
(1)
mJ
–55 to 150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
TA = 25° (unless otherwise noted)
Parameter
Conditions
Gate Drive Voltage, VGS
MIN
MAX
4.5
8
V
22
V
Input Supply Voltage, VIN
Switching Frequency, fSW
CBST = 0.1µF (min)
200
UNIT
1500
Operating Current
Operating Temperature, TJ
kHz
20
A
125
°C
MAX
UNIT
POWER BLOCK PERFORMANCE
TA = 25° (unless otherwise noted)
Parameter
Conditions
MIN
TYP
Power Loss, PLOSS (1)
VIN = 12V, VGS = 5V,
VOUT = 1.3V, IOUT = 15A ,
fSW = 500kHz,
LOUT = 1µH, TJ = 25ºC
1.9
W
VIN Quiescent Current, IQVIN
TG to TGR = 0V
BG to PGND = 0V
10
µA
(1)
Measurement made with six 10-µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins and
using a high current 5V driver IC.
THERMAL INFORMATION
TA = 25°C (unless otherwise stated)
THERMAL METRIC
RqJA
RqJC
(1)
(2)
2
MIN
Junction to ambient thermal resistance (Min Cu) (1)
MAX
UNIT
135
Junction to ambient thermal resistance (Max Cu) (1) (2)
Junction to case thermal resistance (Top of package)
TYP
73
(1)
29
Junction to case thermal resistance (PGND Pin) (1)
°C/W
2.5
2
2
RqJC is determined with the device mounted on a 1-inch (6.45-cm ), 2 oz. (0.071-mm thick) Cu pad on a 1.5-inch × 1.5-inch
(3.81-cm × 3.81-cm), 0.06-inch (1.52-mm) thick FR4 board. RqJC is specified by design while RqJA is determined by the user’s board
design.
Device mounted on FR4 material with 1-inch2 (6.45-cm2) Cu.
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Copyright © 2010, Texas Instruments Incorporated
CSD86330Q3D
www.ti.com
SLPS264A – OCTOBER 2010 – REVISED DECEMBER 2010
ELECTRICAL CHARACTERISTICS
TA = 25°C (unless otherwise stated)
PARAMETER
Q1 Control FET
TEST CONDITIONS
MIN
TYP
Q2 Sync FET
MAX
MIN
TYP
MAX
UNIT
Static Characteristics
BVDSS
Drain to Source Voltage
VGS = 0V, IDS = 250µA
IDSS
Drain to Source Leakage
Current
VGS = 0V, VDS = 20V
IGSS
Gate to Source Leakage
Current
VDS = 0V, VGS = +10 / –8
VGS(th)
Gate to Source Threshold
Voltage
VDS = VGS, IDS = 250µA
RDS(on)
Drain to Source On
Resistance
gfs
Transconductance
25
25
0.9
V
1
1
µA
100
100
nA
1.1
1.6
V
1.4
2.1
0.9
VGS = 4.5V, IDS = 14A
8.8
11.5
4.6
6.0
mΩ
VGS = 8V, IDS = 14A
7.3
9.6
4.0
5.2
mΩ
VDS = 15V, IDS = 14A
52
82
S
Dynamic Characteristics
CISS
Input Capacitance (1)
COSS
Output Capacitance (1)
CRSS
Reverse Transfer
Capacitance (1)
VGS = 0V, VDS = 12.5V,
f = 1MHz
(1)
RG
Series Gate Resistance
Qg
Gate Charge Total (4.5V) (1)
Qgd
Gate Charge - Gate to Drain
Qgs
Gate Charge - Gate to
Source
Qg(th)
Gate Charge at Vth
QOSS
Output Charge
td(on)
710
920
1280
1660
pF
350
455
680
880
pF
18
23
38
49
pF
1.5
3.0
1.2
2.4
Ω
4.8
6.2
9.2
12
nC
0.9
1.6
nC
1.6
2.1
nC
0.9
1.2
nC
7.2
13.6
nC
Turn On Delay Time
4.9
5.3
ns
tr
Rise Time
7.5
6.3
ns
td(off)
Turn Off Delay Time
8.5
15.8
ns
tf
Fall Time
1.9
4.2
ns
VDS = 12.5V,
IDS = 14A
VDS = 15.5V, VGS = 0V
VDS = 12.5V, VGS = 4.5V,
IDS = 14A, RG = 2Ω
Diode Characteristics
VSD
Diode Forward Voltage
IDS = 14A, VGS = 0V
Qrr
Reverse Recovery Charge
trr
Reverse Recovery Time
Vdd = 15.5V, IF = 14A,
di/dt = 300A/µs
(1)
0.85
1
0.8
1
V
3.9
7.3
nC
13.9
19
ns
Specified by design
LD
HD
HS
LS
Max RqJA = 140°C/W
when mounted on
minimum pad area of
2-oz. (0.071-mm thick)
Cu.
MIN Rev0
MIN Rev0
LG
86330Q3D 3.3x3.3
86330Q3D 3.3x3.3
Max RqJA = 76°C/W
when mounted on
1 inch2 (6.45 cm2) of
2-oz. (0.071-mm thick)
Cu.
HG
LD
HD
LG
HG
M0205-01
Copyright © 2010, Texas Instruments Incorporated
HS
LS
M0206-01
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CSD86330Q3D
SLPS264A – OCTOBER 2010 – REVISED DECEMBER 2010
www.ti.com
TYPICAL POWER BLOCK DEVICE CHARACTERISTICS
Test Conditions: VIN = 12V, VDD = 5V, fSW = 500kHz, VOUT = 1.2V, LOUT = 1.0µH, IOUT = 20A, TJ = 125°C, unless stated
otherwise.
1.2
3.5
1.1
Power Loss, Normalized
4
Power Loss (W)
3
2.5
2
1.5
1
1
0.9
0.8
0.7
0.6
0.5
0
0
2
4
6
8
10
12
14
Output Current (A)
16
18
0.5
-50
20
-25
25
50
75
100
Junction Temperature ( °C)
125
150
G002
Figure 2. Power Loss vs Temperature
25
25
20
20
Output Current (A)
Output Current (A)
Figure 1. Power Loss vs Output Current
15
10
400LFM
200LFM
100LFM
Nat Conv
5
0
G001
15
10
400LFM
200LFM
100LFM
Nat Conv
5
0
0
0
10
20
30
40
50
60
Ambient Temperature (°C)
70
80
90
0
10
20
G003
Figure 3. Safe Operating Area – PCB Vertical Mount(1)
30
40
50
60
Ambient Temperature (°C)
70
80
90
G004
Figure 4. Safe Operating Area – PCB Horizontal Mount(1)
25
Output Current (A)
20
15
10
5
0
0
20
40
60
80
100
Board Temperature (°C)
120
140
G005
Figure 5. Typical Safe Operating Area(1)
(1)
4
The Typical Power Block System Characteristic curves are based on measurements made on a PCB design with
dimensions of 4.0” (W) × 3.5” (L) × 0.062” (H) and 6 copper layers of 1 oz. copper thickness. See Application Section
for detailed explanation.
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Copyright © 2010, Texas Instruments Incorporated
CSD86330Q3D
www.ti.com
SLPS264A – OCTOBER 2010 – REVISED DECEMBER 2010
TYPICAL POWER BLOCK DEVICE CHARACTERISTICS (continued)
Test Conditions: VIN = 12V, VDD = 5V, fSW = 500kHz, VOUT = 1.2V, LOUT = 1.0µH, IOUT = 20A, TJ = 125°C, unless stated
otherwise.
15.7
1.5
13.1
1.5
13.1
1.4
10.5
1.4
10.5
1.3
7.9
1.3
7.8
1.2
5.2
1.2
5.2
1.1
2.6
1.1
2.6
0
0.9
-2.6
0.8
-5.2
0.7
-7.9
0.6
200
400
600
800
1000
1200
Switching Frequency (kHz)
1400
1
0
0.9
-2.6
0.8
-5.2
0.7
-7.8
0.6
-10.5
1600
3
6
9
G006
Figure 6. Normalized Power Loss vs Switching Frequency
18
-10.5
24
21
G007
Figure 7. Normalized Power Loss vs Input Voltage
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
15.7
1.6
15.7
1.5
13.1
1.5
13.1
1.4
10.5
1.4
10.5
1.3
7.9
1.3
7.9
1.2
5.2
1.2
5.2
1.1
2.6
1.1
2.6
1
0
0.9
-2.6
0.8
-5.2
0.7
0.6
0.6
1.2
1.8
2.4
3
3.6
Output Voltage (V)
4.2
4.8
1
0
0.9
-2.6
0.8
-5.2
-7.9
0.7
-7.9
-10.5
5.4
0.6
G008
Figure 8. Normalized Power Loss vs. Output Voltage
Copyright © 2010, Texas Instruments Incorporated
Power Loss, Normalized
1.6
SOA Temperature Adj (°C)
Power Loss, Normalized
12
15
Input Voltage (V)
SOA Temperature Adj (°C)
1
Power Loss, Normalized
1.6
SOA Temperature Adj (°C)
TEXT ADDED FOR SPACING
15.7
SOA Temperature Adj (°C)
Power Loss, Normalized
TEXT ADDED FOR SPACING
1.6
0
0.1
0.2
0.3
0.4 0.5 0.6 0.7 0.8
Output Inductance (µH)
0.9
1
-10.5
1.1
G009
Figure 9. Normalized Power Loss vs. Output Inductance
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SLPS264A – OCTOBER 2010 – REVISED DECEMBER 2010
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TYPICAL POWER BLOCK MOSFET CHARACTERISTICS
TA = 25°C, unless stated otherwise.
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
60
60
IDS - Drain-to-Source Current - A
IDS - Drain-to-Source Current - A
VGS = 8V
50
40
VGS = 8V
30
VGS = 6V
20
VGS = 4.5V
10
0
50
40
VGS = 6V
30
20
VGS = 4.5V
10
0
0
0.2
0.4
0.6
0.8
VDS - Drain-to-Source Voltage - V
1
0
0.05
G010
Figure 10. Control MOSFET Saturation
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
VDS = 5V
IDS - Drain-to-Source Current - A
IDS - Drain-to-Source Current - A
G011
100
VDS = 5V
10
1
T C = 125°C
0.1
T C = 25°C
0.01
T C = -55°C
0.001
1
1.5
2
2.5
3
VGS - Gate-to-Source Voltage - V
3.5
10
1
T C = 125°C
0.1
T C = 25°C
0.01
T C = -55°C
0.001
0.5
0.75
G012
Figure 12. Control MOSFET Transfer
1
1.25
1.5
1.75
2
VGS - Gate-to-Source Voltage - V
2.25
2.5
G013
Figure 13. Sync MOSFET Transfer
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
8
8
ID = 14A
VDS = 12.5V
7
VGS - Gate-to-Source Voltage - V
VGS - Gate-to-Source Voltage - V
0.3
Figure 11. Sync MOSFET Saturation
100
6
5
4
3
2
1
0
ID = 14A
VDS = 12.5V
7
6
5
4
3
2
1
0
0
2
4
Qg - Gate Charge - nC
6
Figure 14. Control MOSFET Gate Charge
6
0.1
0.15
0.2
0.25
VDS - Drain-to-Source Voltage - V
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8
G014
0
3
6
9
Qg - Gate Charge - nC
12
15
G015
Figure 15. Sync MOSFET Gate Charge
Copyright © 2010, Texas Instruments Incorporated
CSD86330Q3D
www.ti.com
SLPS264A – OCTOBER 2010 – REVISED DECEMBER 2010
TYPICAL POWER BLOCK MOSFET CHARACTERISTICS (continued)
TA = 25°C, unless stated otherwise.
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
10
10
f = 1MHz
VGS = 0V
Ciss = Cgd + Cgs
Ciss = Cgd + Cgs
0.1
C - Capacitance - nF
C - Capacitance - nF
1
Coss = Cds + Cgd
0.01
1
Coss = Cds + Cgd
0.1
Crss = Cgd
Crss = Cgd
f = 1MHz
VGS = 0V
0.001
0.01
0
5
10
15
20
VDS - Drain-to-Source Voltage - V
25
0
5
G016
Figure 16. Control MOSFET Capacitance
TEXT ADDED FOR SPACING
G017
TEXT ADDED FOR SPACING
1.8
ID = 250µA
ID = 250µA
1.6
VGS(th) - Threshold Voltage - V
1.6
VGS(th) - Threshold Voltage - V
25
Figure 17. Sync MOSFET Capacitance
1.8
1.4
1.2
1
0.8
0.6
0.4
0.2
1.4
1.2
1
0.8
0.6
0.4
0.2
0
-75
-25
25
75
T C - Case Temperature - °C
125
0
-75
175
-25
25
75
T C - Case Temperature - °C
G018
Figure 18. Control MOSFET VGS(th)
125
175
G019
Figure 19. Sync MOSFET VGS(th)
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
25
16
ID = 14A
RDS(on) - On-State Resistance - mΩ
RDS(on) - On-State Resistance - mΩ
10
15
20
VDS - Drain-to-Source Voltage - V
20
15
T C = 125°C
10
T C = 25°C
5
0
ID = 14A
14
12
10
T C = 125°C
8
6
4
T C = 25°C
2
0
0
1
2
3
4
5
6
7
8
VGS - Gate-to-Source Voltage - V
9
Figure 20. Control MOSFET RDS(on) vs VGS
Copyright © 2010, Texas Instruments Incorporated
10
G020
0
1
2
3
4
5
6
7
8
VGS - Gate-to-Source Voltage - V
9
10
G021
Figure 21. Sync MOSFET RDS(on) vs VGS
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CSD86330Q3D
SLPS264A – OCTOBER 2010 – REVISED DECEMBER 2010
www.ti.com
TYPICAL POWER BLOCK MOSFET CHARACTERISTICS (continued)
TA = 25°C, unless stated otherwise.
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
1.6
ID = 14A
VGS = 8V
1.4
Normalized On-State Resistance
Normalized On-State Resistance
1.6
1.2
1
0.8
0.6
0.4
0.2
0
-75
-25
25
75
T C - Case Temperature - °C
125
ID = 14A
VGS = 8V
1.4
1.2
1
0.8
0.6
0.4
0.2
0
-75
175
-25
G022
Figure 22. Control MOSFET Normalized RDS(on)
TEXT ADDED FOR SPACING
G023
TEXT ADDED FOR SPACING
ISD - Source-to-Drain Current - A
ISD - Source-to-Drain Current - A
175
100
10
T C = 125°C
1
0.1
T C = 25°C
0.01
0.001
0.0001
10
T C = 125°C
1
0.1
T C = 25°C
0.01
0.001
0.0001
0
0.2
0.4
0.6
0.8
VSD - Source-to-Drain Voltage - V
1
1.2
0
0.2
G024
Figure 24. Control MOSFET Body Diode
0.4
0.6
0.8
VSD - Source-to-Drain Voltage - V
1
1.2
G025
Figure 25. Sync MOSFET Body Diode
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
100
I(AV) - Peak Avalanche Current - A
100
I(AV) - Peak Avalanche Current - A
125
Figure 23. Sync MOSFET Normalized RDS(on)
100
T C = 25°C
10
T C = 125°C
I(AV) = t(AV) ÷ (0.021 × L)
1
0.01
0.1
1
t(AV) - Time in Avalanche - ms
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T C = 25°C
T C = 125°C
10
I(AV) = t(AV) ÷ (0.021 × L)
10
G026
Figure 26. Control MOSFET Unclamped Inductive
Switching
8
25
75
T C - Case Temperature - °C
1
0.01
0.1
1
t(AV) - Time in Avalanche - ms
10
G027
Figure 27. Sync MOSFET Unclamped Inductive Switching
Copyright © 2010, Texas Instruments Incorporated
CSD86330Q3D
www.ti.com
SLPS264A – OCTOBER 2010 – REVISED DECEMBER 2010
APPLICATION INFORMATION
The CSD86330Q3D NexFET™ power block is an optimized design for synchronous buck applications using 5V
gate drive. The Control FET and Sync FET silicon are parametrically tuned to yield the lowest power loss and
highest system efficiency. As a result, a new rating method is needed which is tailored towards a more systems
centric environment. System level performance curves such as Power Loss, Safe Operating Area, and
normalized graphs allow engineers to predict the product performance in the actual application.
Power Loss Curves
MOSFET centric parameters such as RDS(ON) and Qgd are needed to estimate the loss generated by the devices.
In an effort to simplify the design process for engineers, Texas Instruments has provided measured power loss
performance curves. Figure 1 plots the power loss of the CSD86330Q3D as a function of load current. This curve
is measured by configuring and running the CSD86330Q3D as it would be in the final application (see
Figure 28).The measured power loss is the CSD86330Q3D loss and consists of both input conversion loss and
gate drive loss. Equation 1 is used to generate the power loss curve.
(VIN × IIN) + (VDD × IDD) – (VSW_AVG × IOUT) = Power Loss
(1)
The power loss curve in Figure 1 is measured at the maximum recommended junction temperatures of 125°C
under isothermal test conditions.
Safe Operating Curves (SOA)
The SOA curves in the CSD86330Q3D data sheet provides guidance on the temperature boundaries within an
operating system by incorporating the thermal resistance and system power loss. Figure 3 to Figure 5 outline the
temperature and airflow conditions required for a given load current. The area under the curve dictates the safe
operating area. All the curves are based on measurements made on a PCB design with dimensions of 4” (W) ×
3.5” (L) × 0.062” (T) and 6 copper layers of 1 oz. copper thickness.
Normalized Curves
The normalized curves in the CSD86330Q3D data sheet provides guidance on the Power Loss and SOA
adjustments based on their application specific needs. These curves show how the power loss and SOA
boundaries will adjust for a given set of systems conditions. The primary Y-axis is the normalized change in
power loss and the secondary Y-axis is the change is system temperature required in order to comply with the
SOA curve. The change in power loss is a multiplier for the Power Loss curve and the change in temperature is
subtracted from the SOA curve.
Input Current (IIN)
Gate Drive
Current (IDD)
VDD
A
Gate Drive
Voltage (VDD) V
VDD
ENABLE
VI
CSD86330Q3D
Driver IC
BST
DRVH
PWM
LL
GND
DRVL
PWM
A
VIN
TG
TGR
BG
Control
FET
V
Input Voltage (VIN)
Output Current (IOUT)
VO
VSW
A
Sync
FET
PGND
Averaging
Circuit
V
Averaged Switched
Node Voltage
(VSW_AVG)
S0475-04
Figure 28. Typical Application
Copyright © 2010, Texas Instruments Incorporated
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Calculating Power Loss and SOA
The user can estimate product loss and SOA boundaries by arithmetic means (see Design Example). Though
the Power Loss and SOA curves in this data sheet are taken for a specific set of test conditions, the following
procedure will outline the steps the user should take to predict product performance for any set of system
conditions.
Design Example
Operating Conditions:
• Output Current = 15A
• Input Voltage = 12V
• Output Voltage = 1.2V
• Switching Frequency = 1000kHz
• Inductor = 0.4µH
Calculating Power Loss
•
•
•
•
•
•
Power Loss at 15A = 2.2W (Figure 1)
Normalized Power Loss for input voltage ≈ 1.0 (Figure 7)
Normalized Power Loss for output voltage ≈ 0.98 (Figure 8)
Normalized Power Loss for switching frequency ≈ 1.17 (Figure 6)
Normalized Power Loss for output inductor ≈ 1.06 (Figure 9)
Final calculated Power Loss = 2.2W × 1.0 × 0.98 × 1.17 × 1.06 ≈ 2.67W
Calculating SOA Adjustments
•
•
•
•
•
SOA adjustment for input voltage ≈ 0ºC (Figure 7)
SOA adjustment for output voltage ≈ –0.29ºC (Figure 8)
SOA adjustment for switching frequency ≈ 4.1ºC (Figure 6)
SOA adjustment for output inductor ≈ 1.5ºC (Figure 9)
Final calculated SOA adjustment = 0 + (–0.29) + 4.1 + 1.5 ≈ 5.3ºC
In the design example above, the estimated power loss of the CSD86330Q3D would increase to 2.67W. In
addition, the maximum allowable board and/or ambient temperature would have to decrease by 5.3ºC. Figure 29
graphically shows how the SOA curve would be adjusted accordingly.
1. Start by drawing a horizontal line from the application current to the SOA curve.
2. Draw a vertical line from the SOA curve intercept down to the board/ambient temperature.
3. Adjust the SOA board/ambient temperature by subtracting the temperature adjustment value.
In the design example, the SOA temperature adjustment yields a reduction in allowable board/ambient
temperature of 5.3ºC. In the event the adjustment value is a negative number, subtracting the negative number
would yield an increase in allowable board/ambient temperature.
25
Output Current (A)
20
1
15
10
VGS = 5V
VIN = 12V
VOUT = 1.3V
fSW = 500kHz
LOUT = 1mH
5
2
3
0
0
20
40
60
80
100
Board Temperature (°C)
120
140
G028
Figure 29. Power Block SOA
10
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CSD86330Q3D
www.ti.com
SLPS264A – OCTOBER 2010 – REVISED DECEMBER 2010
RECOMMENDED PCB DESIGN OVERVIEW
There are two key system-level parameters that can be addressed with a proper PCB design: Electrical and
Thermal performance. Properly optimizing the PCB layout will yield maximum performance in both areas. A brief
description on how to address each parameter is provided.
Electrical Performance
The Power Block has the ability to switch voltages at rates greater than 10kV/µs. Special care must be then
taken with the PCB layout design and placement of the input capacitors, Driver IC, and output inductor.
• The placement of the input capacitors relative to the Power Block’s VIN and PGND pins should have the
highest priority during the component placement routine. It is critical to minimize these node lengths. As such,
ceramic input capacitors need to be placed as close as possible to the VIN and PGND pins (see Figure 30).
The example in Figure 30 uses 6 × 10-µF ceramic capacitors (TDK Part # C3216X5R1C106KT or equivalent).
Notice there are ceramic capacitors on both sides of the board with an appropriate amount of vias
interconnecting both layers. In terms of priority of placement next to the Power Block, C5, C7, C19, and C8
should follow in order.
• The Driver IC should be placed relatively close to the Power Block Gate pins. TG and BG should connect to
the outputs of the Driver IC. The TGR pin serves as the return path of the high-side gate drive circuitry and
should be connected to the Phase pin of the IC (sometimes called LX, LL, SW, PH, etc.). The bootstrap
capacitor for the Driver IC will also connect to this pin.
• The switching node of the output inductor should be placed relatively close to the Power Block VSW pins.
Minimizing the node length between these two components will reduce the PCB conduction losses and
actually reduce the switching noise level. (1)
Thermal Performance
The Power Block has the ability to utilize the GND planes as the primary thermal path. As such, the use of
thermal vias is an effective way to pull away heat from the device and into the system board. Concerns of solder
voids and manufacturability problems can be addressed by the use of three basic tactics to minimize the amount
of solder attach that will wick down the via barrel:
• Intentionally space out the vias from each other to avoid a cluster of holes in a given area.
• Use the smallest drill size allowed in your design. The example in Figure 30 uses vias with a 10 mil drill hole
and a 16 mil capture pad.
• Tent the opposite side of the via with solder-mask.
In the end, the number and drill size of the thermal vias should align with the end user’s PCB design rules and
manufacturing capabilities.
Figure 30. Recommended PCB Layout (Top Down)
(1)
Keong W. Kam, David Pommerenke, “EMI Analysis Methods for Synchronous Buck Converter EMI Root Cause Analysis”, University of
Missouri – Rolla
Copyright © 2010, Texas Instruments Incorporated
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CSD86330Q3D
SLPS264A – OCTOBER 2010 – REVISED DECEMBER 2010
www.ti.com
MECHANICAL DATA
Q3D Package Dimensions
A
E2
5
4
3
6
4
5
3
q
L
d1
L
c1
9
2
7
2
D2
7
D1
E
d
e
8
1
1
8
Top View
Side View
d2
Pin 1
Designation
VIN
Pin 2
VIN
Pin 3
TG
Pin 4
TGR
Pin 5
BG
Pin 6
VSW
Pin 7
VSW
Pin 8
VSW
Pin 9
PGND
DIM
c
Exposed tie clips may vary
q
M0192-01
MILLIMETERS
INCHES
MIN
MAX
MIN
MAX
a
1.40
1.55
0.055
0.061
b
0.280
0.400
0.011
0.016
c
0.150
0.250
0.006
0.010
c1
0.150
0.250
0.006
0.010
d
0.940
1.040
0.037
0.041
d1
0.160
0.260
0.006
0.010
d2
0.150
0.250
0.006
0.010
d3
0.250
0.350
0.010
0.014
D1
3.200
3.400
0.126
0.134
D2
2.650
2.750
0.104
0.108
E
3.200
3.400
0.126
0.134
E1
3.200
3.400
0.126
0.134
E2
1.750
1.850
0.069
e
0.650 TYP
L
0.400
q
0.00
K
12
d3
K
Bottom View
Pinout
Position
b
6
E1
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0.300 TYP
0.073
0.026 TYP
0.500
0.016
–
–
0.020
–
0.012 TYP
Copyright © 2010, Texas Instruments Incorporated
CSD86330Q3D
www.ti.com
SLPS264A – OCTOBER 2010 – REVISED DECEMBER 2010
Land Pattern Recommendation
1.900 (0.075)
0.200
(0.008)
0.210
(0.008)
4
0.350 (0.014)
5
0.440
(0.017)
0.650
(0.026)
2.800
(0.110)
2.390
(0.094)
8
0.210
(0.008)
1
1.090
(0.043)
0.300 (0.012)
0.650 (0.026)
0.650 (0.026)
3.600 (0.142)
M0193-01
NOTE: Dimensions are in mm (inches).
Stencil Recommendation
0.160 (0.005)
0.550 (0.022)
0.200 (0.008)
5
4
0.300 (0.012)
0.300
(0.012)
0.340
(0.013)
2.290
(0.090)
0.333
(0.013)
8
1
0.990
(0.039)
0.100
(0.004)
0.300 (0.012)
0.350 (0.014)
0.850 (0.033)
3.500 (0.138)
M0207-01
NOTE: Dimensions are in mm (inches).
For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through
PCB Layout Techniques.
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CSD86330Q3D
SLPS264A – OCTOBER 2010 – REVISED DECEMBER 2010
www.ti.com
1.75 ±0.10
Q3D Tape and Reel Information
4.00 ±0.10 (See Note 1)
Ø 1.50
+0.10
–0.00
1.30
3.60
5.50 ±0.05
12.00
+0.30
–0.10
8.00 ±0.10
2.00 ±0.05
3.60
M0144-01
NOTES: 1. 10-sprocket hole-pitch cumulative tolerance ±0.2
2. Camber not to exceed 1mm in 100mm, noncumulative over 250mm
3. Material: black static-dissipative polystyrene
4. All dimensions are in mm, unless otherwise specified.
5. Thickness: 0.30 ±0.05mm
6. MSL1 260°C (IR and convection) PbF reflow compatible
Spacer
REVISION HISTORY
Changes from Original (October 2010) to Revision A
•
14
Page
Changed IOUT Conditions From: 20A To: 15A, and the TYP value From: 2.9W To: 1.9W ................................................... 2
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PACKAGE OPTION ADDENDUM
www.ti.com
12-Feb-2011
PACKAGING INFORMATION
Orderable Device
CSD86330Q3D
Status
(1)
ACTIVE
Package Type Package
Drawing
SON
DQZ
Pins
Package Qty
8
2500
Eco Plan
(2)
Pb-Free (RoHS
Exempt)
Lead/
Ball Finish
CU SN
MSL Peak Temp
(3)
Samples
(Requires Login)
Level-1-260C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
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