CSD87384M www.ti.com SLPS415B – SEPTEMBER 2013 – REVISED JANUARY 2014 CSD87384M Synchronous Buck NexFET™ Power Block II FEATURES DESCRIPTION • • • • • • • • • • • • The CSD87384M NexFET™ Power Block II is a highly optimized design for synchronous buck applications offering high current and high efficiency capability in a small 5.0-mm × 3.5-mm outline. Optimized for 5 V gate drive applications, this product offers an efficient and flexible solution capable of providing a high density power supply when paired with any 5 V gate drive from an external controller or driver. 1 2 Half-Bridge Power Block 90.5% System Efficiency at 25 A Up to 30 A Operation High Density – 5-mm x 3.5-mm LGA Footprint Double Side Cooling Capability Ultra-Low Profile – 0.48-mm MAX Optimized for 5 V Gate Drive Low Switching Losses Ultra-Low Inductance Package RoHS Compliant Halogen Free Pb-Free Terminal Plating TEXT ADDED FOR SPACING Ordering Information Device Media Qty CSD87384M 13-Inch Reel 2500 CSD87384MT 7-Inch Reel 250 • • Ship 5 × 2.5 LGA Tape and Reel TEXT ADDED FOR SPACING APPLICATIONS • Package Synchronous Buck Converters – High Frequency Applications – High Current, Low Duty Cycle Applications Multiphase Synchronous Buck Converters POL DC-DC Converters 1 VIN TG PGND BG VSW TEXT ADDED FOR SPACING Typical Circuit Typical Power Block Efficiency and Power Loss VIN VDD VDD 100 7 90 6 BOOT VIN DRVH VSW ENABLE PWM ENABLE PWM VOUT LL BG DRVL PGND Driver IC VGS = 5V VIN = 12V VOUT = 1.3V LOUT = 0.29µH fSW = 500kHz TA = 25ºC 80 Efficiency (%) GND 70 60 5 4 3 50 2 40 1 Power Loss (W) TG CSD87384M 30 0 3 6 9 12 15 18 21 Output Current (A) 24 27 30 0 G001 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NexFET is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2013–2014, Texas Instruments Incorporated CSD87384M SLPS415B – SEPTEMBER 2013 – REVISED JANUARY 2014 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings TA = 25°C (unless otherwise noted) (1) PARAMETER CONDITIONS VIN to PGND Voltage range MIN MAX –0.8 30 VSW to PGND 30 VSW to PGND (10 ns) 32 TG to VSW –8 10 BG to PGND –8 10 Pulsed Current Rating, IDM (2) Power Dissipation, PD Avalanche Energy EAS (2) (3) 8 W 48 Operating Junction and Storage Temperature Range, TJ, TSTG (1) A 231 Control FET, ID = 31 L = 0.1 mH –55 V 95 (3) Sync FET, ID = 68, L = 0.1 mH UNIT 150 mJ °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability. Pulse Duration ≤ 50 µs. Duty cycle ≤ 0.01. Device mounted on FR4 material with 1-inch2 (6.45-cm2) Cu. Recommended Operating Conditions TA = 25°C (unless otherwise noted) PARAMETER CONDITIONS MIN Gate Drive Voltage, VGS MAX 4.5 8 Input Supply Voltage, VIN Switching Frequency, fSW Operating Current 24 CBST = 0.1 μF (min) 200 1500 UNIT V V kHz No Airflow 30 A With Airflow (200 LFM) 35 A With Airflow + Heat Sink 40 A 125 °C MAX UNIT Operating Temperature, TJ Power Block Performance TA = 25°C (unless otherwise noted) PARAMETER Power Loss, PLOSS (1) VIN Quiescent Current, IQVIN (1) 2 CONDITIONS MIN TYP VIN = 12 V, VGS = 5 V VOUT = 1.3 V, IOUT = 25 A fSW = 500 kHz LOUT = 0.3 µH, TJ = 25ºC 3.7 W TG to TGR = 0 V BG to PGND = 0 V 10 µA Measurement made with six 10 µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins and using a high current 5 V driver IC. Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated CSD87384M www.ti.com SLPS415B – SEPTEMBER 2013 – REVISED JANUARY 2014 Thermal Information TA = 25°C (unless otherwise stated) THERMAL METRIC RθJA RθJC (1) (2) Junction to ambient thermal resistance (Min Cu) Junction to ambient thermal resistance (Max Cu) (1) TYP MAX UNIT 153 (2) (1) Junction to case thermal resistance (Top of package) Junction to case thermal resistance (PGND Pin) MIN (1) 67 (1) 3.0 °C/W 1.25 RθJC is determined with the device mounted on a 1-inch2 (6.45-cm2), 2 oz. (0.071-mm thick) Cu pad on a 1.5-inch × 1.5-inch (3.81-cm × 3.81-cm), 0.06-inch (1.52-mm) thick FR4 board. RθJC is specified by design while RθJA is determined by the user’s board design. Device mounted on FR4 material with 1-inch2 (6.45-cm2) Cu. Copyright © 2013–2014, Texas Instruments Incorporated Submit Documentation Feedback 3 CSD87384M SLPS415B – SEPTEMBER 2013 – REVISED JANUARY 2014 www.ti.com Electrical Characteristics TA = 25°C (unless otherwise stated) PARAMETER TEST CONDITIONS Q1 Control FET MIN TYP Q2 Sync FET MAX MIN TYP MAX UNIT Static Characteristics BVDSS Drain-to-Source Voltage VGS = 0 V, IDS = 250 μA IDSS Drain-to-Source Leakage Current VGS = 0 V, VDS = 24 V 1 1 μA IGSS Gate-to-Source Leakage Current VDS = 0 V, VGS = 10 V 100 100 nA VGS(th) Gate-to-Source Threshold Voltage VDS = VGS, IDS = 250 μA 1.7 V RDS(on) Drain-to-Source On Impedance gfs Transconductance 30 30 1.1 1.9 V 1.1 VGS = 4.5 V, IDS = 25 A 7.5 8.9 2.15 2.6 VGS = 8 V, IDS = 25 A 6.4 7.7 1.95 2.4 VDS = 10 V, IDS = 25 A 67 240 mΩ S Dynamic Characteristics CISS COSS CRSS RG Input Capacitance (1) Output Capacitance (1) Reverse Transfer Capacitance VGS = 0 V, VDS = 15 V, f = 1MHz (1) Series Gate Resistance (1) 884 1150 3760 4890 pF 452 588 1110 1440 pF 19.4 25.2 87 114 pF 0.7 1.4 Ω 31 40 nC 1.0 2.0 Qg Gate Charge Total (4.5 V) (1) 7.1 9.2 Qgd Gate Charge – Gate to Drain 1.5 8.6 nC Qgs Gate Charge – Gate to Source 2.7 8.6 nC Qg(th) Gate Charge at Vth QOSS Output Charge td(on) Turn On Delay Time tr Rise Time td(off) Turn Off Delay Time tf Fall Time VDS = 15 V, IDS = 25 A 1.3 5.4 nC 11.3 37 nC 8.7 17.5 ns 56 49 ns 14 29 ns 7.6 8.2 ns IDS = 25 A, VGS = 0 V 0.85 0.80 Vdd = 15 V, IF = 25 A, di/dt = 300 A/μs 21 51 nC 21 32 ns VDD = 12 V, VGS = 0 V VDS = 15 V, VGS = 4.5 V, IDS = 25 A, RG = 2 Ω Diode Characteristics VSD Diode Forward Voltage Qrr Reverse Recovery Charge trr Reverse Recovery Time (1) Specified by design Max RθJA = 67°C/W when mounted on 1 inch2 (6.45 cm2) of 2-oz. (0.071-mm thick) Cu. 4 V Submit Documentation Feedback Max RθJA = 153°C/W when mounted on minimum pad area of 2-oz. (0.071-mm thick) Cu. Copyright © 2013–2014, Texas Instruments Incorporated CSD87384M www.ti.com SLPS415B – SEPTEMBER 2013 – REVISED JANUARY 2014 Typical Power Block Device Characteristics TJ = 125°C, unless stated otherwise. 8 1.1 VIN = 12V VGS = 5V VOUT = 1.3V fSW = 500kHz LOUT = 0.29µH Power Loss (W) 6 5 4 3 2 1 4 7 10 13 16 19 Output Current (A) 22 25 0.7 35 30 30 25 25 20 15 400LFM 200LFM 100LFM Nat Conv 5 0 0 10 20 30 40 50 60 70 Ambient Temperature (ºC) 0 25 50 75 100 Junction Temperature (ºC) 150 G001 20 15 VIN = 12V VGS = 5V VOUT = 1.3V fSW = 500kHz LOUT = 0.29µH 10 5 80 125 Figure 2. Normalized Power Loss vs Temperature 35 10 −25 G001 Output Current (A) Output Current (A) 0.8 0.5 −50 28 30 Figure 1. Power Loss vs Output Current 90 G001 Figure 3. Safe Operating Area – PCB Horizontal Mount (1) (1) 0.9 0.6 1 0 VIN = 12V VGS = 5V VOUT = 1.3V fSW = 500kHz LOUT = 0.29µH 1 Power Loss, Normalized 7 0 0 20 40 60 80 100 Board Temperature (ºC) 120 140 G001 Figure 4. Typical Safe Operating Area(1) The Typical Power Block System Characteristic curves are based on measurements made on a PCB design with dimensions of 4.0 inches (W) × 3.5 inches (L) x 0.062 inch (H) and 6 copper layers of 1-oz. copper thickness. See Application Section for detailed explanation. Copyright © 2013–2014, Texas Instruments Incorporated Submit Documentation Feedback 5 CSD87384M SLPS415B – SEPTEMBER 2013 – REVISED JANUARY 2014 www.ti.com Typical Power Block Device Characteristics (continued) TJ = 125°C, unless stated otherwise. TEXT ADDED FOR SPACING 1.5 4.2 1.3 1.4 3.4 1.3 2.5 1.2 1.7 0.8 1.05 0.4 −1.7 1 0.0 −2.5 400 600 800 1000 1200 1400 1600 1800 Switching Frequency (kHz) 0.95 0.8 0.0 −0.8 0 G001 Figure 5. Normalized Power Loss vs Switching Frequency 1.6 5 3.3 1.4 1.7 1.2 VIN = 12V VGS = 5V fSW = 500kHz LOUT = 0.29µH IOUT = 30A 1.8 2.3 2.8 3.3 3.8 Output Voltage (V) 4.3 4.8 0 −1.7 −3.3 5.3 Figure 7. Normalized Power Loss vs. Output Voltage 6 Submit Documentation Feedback Power Loss, Normalized 6.7 SOA Temperature Adj (ºC) Power Loss, Normalized 1.8 1.3 8 10 12 14 16 Input Voltage (V) 18 20 22 24 −0.4 G001 TEXT ADDED FOR SPACING 0.59 VIN = 12V VGS = 5V VOUT = 1.3V fSW = 500kHz IOUT = 30A 1.06 0.8 6 1.07 8.3 0.8 4 Figure 6. Normalized Power Loss vs Input Voltage TEXT ADDED FOR SPACING 2 1 2 1.05 1.04 1.03 0.42 0.34 0.25 1.02 0.17 1.01 0.08 0 1 0.99 −0.08 0.98 −0.17 0.97 −0.25 0.96 G001 0.51 0 −0.34 100 200 300 400 500 600 700 800 900 1000 1100 Output Inductance (nH) SOA Temperature Adj (ºC) 0.9 0.6 0.3 1.7 1.1 VIN = 12V VGS = 5V VOUT = 1.3V LOUT = 0.29µH IOUT = 30A 1 200 1.2 2.1 1.3 0.8 0 1.25 2.5 1.15 1.1 0.7 3.0 VGS = 5V VOUT = 1.3V LOUT = 0.29µH fSW = 500kHz IOUT = 30A SOA Temperature Adj (ºC) 1.35 Power Loss, Normalized 5.1 SOA Temperature Adj (ºC) Power Loss, Normalized TEXT ADDED FOR SPACING 1.6 G001 Figure 8. Normalized Power Loss vs. Output Inductance Copyright © 2013–2014, Texas Instruments Incorporated CSD87384M www.ti.com SLPS415B – SEPTEMBER 2013 – REVISED JANUARY 2014 Typical Power Block MOSFET Characteristics TA = 25°C, unless stated otherwise. TEXT ADDED FOR SPACING 200 90 180 IDS - Drain-to-Source Current (A) IDS - Drain-to-Source Current (A) TEXT ADDED FOR SPACING 100 80 70 60 50 40 30 VGS = 8.0V VGS = 4.5V VGS = 4.0V 20 10 0 0 0.3 0.6 0.9 1.2 VDS - Drain-to-Source Voltage (V) 160 140 120 100 80 60 20 0 1.5 VGS = 8.0V VGS = 4.5V VGS = 4.0V 40 0 0.1 G001 Figure 9. Control MOSFET Saturation TEXT ADDED FOR SPACING IDS - Drain-to-Source Current (A) IDS - Drain-to-Source Current (A) VDS = 5V 1 0.1 0.01 TC = 125°C TC = 25°C TC = −55°C 0 0.5 1 1.5 2 2.5 3 VGS - Gate-to-Source Voltage (V) 3.5 4 VDS = 5V 10 1 0.1 0.01 TC = 125°C TC = 25°C TC = −55°C 0.001 0.0001 0 0.5 G001 Figure 11. Control MOSFET Transfer TEXT ADDED FOR SPACING 3 G001 TEXT ADDED FOR SPACING 10 ID = 25A VDS = 15V 9 VGS - Gate-to-Source Voltage (V) VGS - Gate-to-Source Voltage (V) 1 1.5 2 2.5 VGS - Gate-to-Source Voltage (V) Figure 12. Sync MOSFET Transfer 10 8 7 6 5 4 3 2 1 0 G001 TEXT ADDED FOR SPACING 200 100 10 0.0001 0.6 Figure 10. Sync MOSFET Saturation 100 0.001 0.2 0.3 0.4 0.5 VDS - Drain-to-Source Voltage (V) 0 2 4 6 8 10 12 Qg - Gate Charge (nC) 14 Figure 13. Control MOSFET Gate Charge Copyright © 2013–2014, Texas Instruments Incorporated 16 G001 ID = 25A VDS =15V 9 8 7 6 5 4 3 2 1 0 0 5 10 15 20 25 30 35 40 45 50 55 60 65 Qg - Gate Charge (nC) G001 Figure 14. Sync MOSFET Gate Charge Submit Documentation Feedback 7 CSD87384M SLPS415B – SEPTEMBER 2013 – REVISED JANUARY 2014 www.ti.com Typical Power Block MOSFET Characteristics (continued) TA = 25°C, unless stated otherwise. TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 1000 1000 C − Capacitance (nF) 10000 C − Capacitance (nF) 10000 100 10 1 Ciss = Cgd + Cgs Coss = Cds + Cgd Crss = Cgd 0 5 10 15 20 25 VDS - Drain-to-Source Voltage (V) 100 10 1 30 Ciss = Cgd + Cgs Coss = Cds + Cgd Crss = Cgd 0 5 Figure 15. Control MOSFET Capacitance TEXT ADDED FOR SPACING VGS(th) - Threshold Voltage (V) VGS(th) - Threshold Voltage (V) 1.6 1.5 1.4 1.3 1.2 1.1 1 0.9 0.8 −25 25 75 125 TC - Case Temperature (ºC) 175 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 −75 ID = 250µA −25 G001 Figure 17. Control MOSFET VGS(th) TEXT ADDED FOR SPACING G001 TEXT ADDED FOR SPACING ID = 25A 18 RDS(on) - On-State Resistance (mΩ) RDS(on) - On-State Resistance (mΩ) 175 8 16 14 12 10 8 6 4 TC = 25°C TC = 125ºC 2 0 1 2 3 4 5 6 7 8 VGS - Gate-to- Source Voltage (V) 9 Figure 19. Control MOSFET RDS(on) vs VGS 8 25 75 125 TC - Case Temperature (ºC) Figure 18. Sync MOSFET VGS(th) 20 0 G001 TEXT ADDED FOR SPACING ID = 250µA 0.7 −75 30 Figure 16. Sync MOSFET Capacitance 1.8 1.7 10 15 20 25 VDS - Drain-to-Source Voltage (V) G001 Submit Documentation Feedback 10 G001 ID = 25A 7 6 5 4 3 2 TC = 25°C TC = 125ºC 1 0 0 1 2 3 4 5 6 7 8 VGS - Gate-to- Source Voltage (V) 9 10 G001 Figure 20. Sync MOSFET RDS(on) vs VGS Copyright © 2013–2014, Texas Instruments Incorporated CSD87384M www.ti.com SLPS415B – SEPTEMBER 2013 – REVISED JANUARY 2014 Typical Power Block MOSFET Characteristics (continued) TA = 25°C, unless stated otherwise. TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 1.6 Normalized On-State Resistance Normalized On-State Resistance ID =25A VGS = 8V 1.5 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 −75 1.8 ID = 25A 1.7 VGS = 8V 1.6 1.5 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 −75 −25 −25 25 75 125 TC - Case Temperature (ºC) 175 G001 Figure 21. Control MOSFET Normalized RDS(on) TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING ISD − Source-to-Drain Current (A) ISD − Source-to-Drain Current (A) G001 100 10 1 0.1 0.01 0.001 TC = 25°C TC = 125°C 0 0.2 0.4 0.6 0.8 VSD − Source-to-Drain Voltage (V) 1 10 1 0.1 0.01 0.001 0.0001 TC = 25°C TC = 125°C 0 G001 Figure 23. Control MOSFET Body Diode TEXT ADDED FOR SPACING 1 G001 TEXT ADDED FOR SPACING I(AV) - Peak Avalanche Current (A) 100 10 TC = 25°C TC = 125°C 1 0.01 0.2 0.4 0.6 0.8 VSD − Source-to-Drain Voltage (V) Figure 24. Sync MOSFET Body Diode 100 I(AV) - Peak Avalanche Current (A) 175 Figure 22. Sync MOSFET Normalized RDS(on) 100 0.0001 25 75 125 TC - Case Temperature (ºC) 0.1 t(AV) - Time in Avalanche (ms) 1 G001 Figure 25. Control MOSFET Unclamped Inductive Switching Copyright © 2013–2014, Texas Instruments Incorporated 10 TC = 25°C TC = 125°C 1 0.01 0.1 t(AV) - Time in Avalanche (ms) 1 G001 Figure 26. Sync MOSFET Unclamped Inductive Switching Submit Documentation Feedback 9 CSD87384M SLPS415B – SEPTEMBER 2013 – REVISED JANUARY 2014 www.ti.com The CSD87384M NexFET™ power block is an optimized design for synchronous buck applications using 5 V gate drive. The Control FET and Sync FET silicon are parametrically tuned to yield the lowest power loss and highest system efficiency. As a result, a new rating method is needed which is tailored toward a more systemscentric environment. System level performance curves such as Power Loss, Safe Operating Area, and normalized graphs allow engineers to predict the product performance in the actual application. Power Loss Curves MOSFET centric parameters such as RDS(ON) and Qgd are needed to estimate the loss generated by the devices. To simplify the design process for engineers, TI has provided measured power loss performance curves. Figure 1 plots the power loss of the CSD87381P as a function of load current. This curve is measured by configuring and running the CSD87381P as it would be in the final application (see Figure 27). The measured power loss is the CSD87381P loss and consists of both input conversion loss and gate drive loss. Equation 1 is used to generate the power loss curve. (VIN × IIN) + (VDD × IDD) – (VSW_AVG × IOUT) = Power Loss (1) The power loss curve in Figure 1 is measured at the maximum recommended junction temperatures of 125°C under isothermal test conditions. Safe Operating Curves (SOA) The SOA curves in the CSD87384M data sheet provide guidance on the temperature boundaries within an operating system by incorporating the thermal resistance and system power loss. Figure 3 to Figure 4 outline the temperature and airflow conditions required for a given load current. The area under the curve dictates the safe operating area. All the curves are based on measurements made on a PCB design with dimensions of 4 inches (W) x 3.5 inches (L) x 0.062 inch (T) and 6 copper layers of 1-oz. copper thickness. Normalized Curves The normalized curves in the CSD87384M data sheet provide guidance on the Power Loss and SOA adjustments based on their application-specific needs. These curves show how the power loss and SOA boundaries adjust for a given set of systems conditions. The primary y-axis is the normalized change in power loss and the secondary y-axis is the change in system temperature required in order to comply with the SOA curve. The change in power loss is a multiplier for the Power Loss curve and the change in temperature is subtracted from the SOA curve. Input Current (IIN) A VDD A VDD V VIN Gate Drive V Voltage (VDD) VIN BOOT DRVH ENABLE Input Voltage (VIN) TG Output Current (IOUT) VSW LL PWM PWM DRVL GND Driver IC A VOUT BG PGND CSD87384M Averaging Circuit Averaged Switch V Node Voltage (VSW_AVG) Figure 27. Typical Application 10 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated CSD87384M www.ti.com SLPS415B – SEPTEMBER 2013 – REVISED JANUARY 2014 Calculating Power Loss and SOA The user can estimate product loss and SOA boundaries by arithmetic means (see Design Example). Though the Power Loss and SOA curves in this data sheet are taken for a specific set of test conditions, the following procedure outlines the steps the user should take to predict product performance for any set of system conditions. Design Example Operating Conditions: • Output Current = 20 A • Input Voltage = 4 V • Output Voltage = 1 V • Switching Frequency = 800 kHz • Inductor = 0.2 µH Calculating Power Loss • • • • • • Power Loss at 20 A = 3.5 W (Figure 1) Normalized Power Loss for input voltage ≈ 1.18 (Figure 6) Normalized Power Loss for output voltage ≈ 0.94 (Figure 7) Normalized Power Loss for switching frequency ≈ 1.15 (Figure 5) Normalized Power Loss for output inductor ≈ 1.02 (Figure 8) Final calculated Power Loss = 3.5W x 1.18 x 0.94 x 1.15 x 1.02 ≈ 4.6 W Calculating SOA Adjustments • • • • • SOA adjustment for input voltage ≈ 1.5ºC (Figure 6) SOA adjustment for output voltage ≈ –0.5ºC (Figure 7) SOA adjustment for switching frequency ≈ 1.2ºC (Figure 5) SOA adjustment for output inductor ≈ 0.2ºC (Figure 8) Final calculated SOA adjustment = 1.5 + (-0.5) + 1.2 + 0.2 ≈ 2.4ºC In the previous design example, the estimated power loss of the CSD87384M would increase to 4.6 W. In addition, the maximum allowable board and/or ambient temperature would have to decrease by 2.4ºC. Figure 28 graphically shows how the SOA curve would be adjusted accordingly. 1. Start by drawing a horizontal line from the application current to the SOA curve. 2. Draw a vertical line from the SOA curve intercept down to the board/ambient temperature. 3. Adjust the SOA board/ambient temperature by subtracting the temperature adjustment value. In the design example, the SOA temperature adjustment yields a reduction in allowable board/ambient temperature of 2.4ºC. In the event the adjustment value is a negative number, subtracting the negative number would yield an increase in allowable board/ambient temperature. Figure 28. Power Block SOA Copyright © 2013–2014, Texas Instruments Incorporated Submit Documentation Feedback 11 CSD87384M SLPS415B – SEPTEMBER 2013 – REVISED JANUARY 2014 www.ti.com RECOMMENDED PCB DESIGN OVERVIEW There are two key system-level parameters that can be addressed with a proper PCB design: Electrical and Thermal performance. Properly optimizing the PCB layout yields maximum performance in both areas. A brief description on how to address each parameter is provided. Electrical Performance The CSD87384M has the ability to switch voltages at rates greater than 10 kV/µs. Special care must be then taken with the PCB layout design and placement of the input capacitors, inductor, and output capacitors. • The placement of the input capacitors relative to VIN and PGND pins of CSD87384M device should have the highest priority during the component placement routine. It is critical to minimize these node lengths. As such, ceramic input capacitors need to be placed as close as possible to the VIN and PGND pins (see Figure 29). The example in Figure 29 uses 1 x 10-nF 0402 25-V and 4 x 10-μF 1206 25-V ceramic capacitors (TDK part number C3216X5R1C106KT or equivalent). Notice there are ceramic capacitors on both sides of the board with an appropriate amount of vias interconnecting both layers. In terms of priority of placement next to the Power Stage C21, C5, C8, C19, and C18 should follow in order. • The switching node of the output inductor should be placed relatively close to the Power Block II CSD87384M VSW pins. Minimizing the VSW node length between these two components will reduce the PCB conduction losses and actually reduce the switching noise level. See Figure 29. (1) (1) Keong W. Kam, David Pommerenke, “EMI Analysis Methods for Synchronous Buck Converter EMI Root Cause Analysis”, University of Missouri – Rolla Thermal Performance The CSD87384M has the ability to utilize the PGND planes as the primary thermal path. As such, the use of thermal vias is an effective way to pull away heat from the device and into the system board. Concerns of solder voids and manufacturability problems can be addressed by the use of three basic tactics to minimize the amount of solder attach that wicks down the via barrel: • Intentionally space out the vias from each other to avoid a cluster of holes in a given area. • Use the smallest drill size allowed in your design. The example in Figure 29 uses vias with a 10 mil drill hole and a 16 mil capture pad. • Tent the opposite side of the via with solder-mask. The number and drill size of the thermal vias should align with the end user’s PCB design rules and manufacturing capabilities. Figure 29. Recommended PCB Layout (Top Down View) 12 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated CSD87384M www.ti.com SLPS415B – SEPTEMBER 2013 – REVISED JANUARY 2014 Mechanical Data CSD87384M Package Dimensions Table 1. Pin Configuration Position Copyright © 2013–2014, Texas Instruments Incorporated Designation Pin 1 TG Pin 2 VIN Pin 3 PGND Pin 4 BG Pin 5 VSW Submit Documentation Feedback 13 CSD87384M SLPS415B – SEPTEMBER 2013 – REVISED JANUARY 2014 www.ti.com 2.500 REF PKG 1.504 2.005 2.500 REF PKG Land Pattern Recommendation 1.750 REF PKG 1.750 1.208 1.208 2 3 5 0.000 0.588 0.888 1.208 1 0.588 0.888 1.208 4 0.822 1.122 1.442 1.560 2.000 0.696 1.915 1.595 PACKAGE OUTLINE 0.000 1.750 REF PKG 2.500 REF PKG Solder Mask Opening 1.331 1.932 1.578 2.500 REF PKG Text For Spacing Stencil Recommendation (100 µm) 1.750 REF PKG 1.356 0.955 0.947 0.000 0.327 0.317 0.517 0.937 1.163 1.356 0.935 0.955 1.161 2.450 2.056 1.169 1.395 0.000 0.332 0.532 0.693 0.467 PACKAGE OUTLINE 1.868 1.642 1.750 REF PKG Text For Spacing . Text For Spacing 14 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated CSD87384M www.ti.com SLPS415B – SEPTEMBER 2013 – REVISED JANUARY 2014 2.500 REF PKG Solder Mask Opening 1.436 1.560 1.950 2.500 REF PKG Stencil Recommendation (125 µm) 1.750 REF PKG 1.452 1.070 1.012 0.000 0.337 0.587 0.913 1.070 1.183 1.452 0.392 0.913 1.183 2.457 2.043 1.147 1.417 0.000 0.307 0.557 0.707 0.572 PACKAGE OUTLINE 1.890 1.620 1.750 REF PKG Text For Spacing For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through PCB Layout Techniques. Text For Spacing Pin Drawing 87384M TI YMS LLLL E Text For Spacing Copyright © 2013–2014, Texas Instruments Incorporated Submit Documentation Feedback 15 CSD87384M SLPS415B – SEPTEMBER 2013 – REVISED JANUARY 2014 www.ti.com CSD87384M Embossed Carrier Tape Dimensions (1) Pin 1 is oriented in the top-left quadrant of the tape enclosure (closest to the carrier tape sprocket holes). spacer REVISION HISTORY Changes from Original (September 2013) to Revision A • Page Changed VGS(th) from 1.0 V to 1.1 V in the Electrical Characteristics table .......................................................................... 4 Changes from Revision A (September 2013) to Revision B Page • Added small reel order number ............................................................................................................................................ 1 • Changed Figure 16 ............................................................................................................................................................... 8 16 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 29-Jan-2014 PACKAGING INFORMATION Orderable Device Status (1) CSD87384M ACTIVE Package Type Package Pins Package Drawing Qty PTAB MPB 5 2500 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Op Temp (°C) Device Marking (4/5) -55 to 150 87384M (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 29-Jan-2014 Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 17-Dec-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device CSD87384M Package Package Pins Type Drawing PTAB MPB 5 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 3.8 B0 (mm) K0 (mm) P1 (mm) 5.3 0.55 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 17-Dec-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CSD87384M PTAB MPB 5 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications. In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms. No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of non-designated products, TI will not be responsible for any failure to meet ISO/TS16949. Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2014, Texas Instruments Incorporated