OKI Semiconductor ML9361 PEDL9361-01 Issue Date:Dec. 12, 2002 Preliminary 128-Channel Organic EL Anode Driver GENERAL DESCRIPTION The ML9361 is an organic EL anode driver LSI with 128 drivers. The anode driver is constant current output type and allows adjustment of current and pulse width for each output. Since this LSI has the output condition setting function, which allows setting of all outputs High, all outputs Low, and all outputs High Impedance, the user can set driving methods suited to the characteristics of individual organic EL panel. When combined with ML9371 the organic EL cathode driver, the ML9361 can drive a 64 × 128 full-dot panel. FEATURES • • • • • • • • • • Logic power supply voltage EL drive voltage Anode outputs Anode high output current : : : : 3.0 to 5.5 V 8.0 to 30 V (max.) 128 outputs –1.0 mA (constant current output, current adjustment range = at 100%) Anode low output current : 40 mA (max.) Anode low ON-resistance : 500Ω (max.) Anode output current adjustment range : 0%, 33%, 66%, and 100% (for each output) Output pulse width adjustment : Adjustable in 16 different degrees (adjusted by external clock input, for each output) All outputs High, all outputs Low, and all outputs High Impedance can be set as output conditions Package : Gold bump chip (TCP is tailored for each customer requirement) 1/19 PEDL9361-01 OKI Semiconductor ML9361 BLOCK DIAGRAM OUT1 OUT128 VDISP Constant current source circuit VEL VELSEL R-ADJ Anode driver D-GND VDD HZ ALL H ALL L OFF HZ A0 HZ PL A-CLK RESET Driver control circuit PAO0-1 PAO2-1 PAO1-1 PAO3-1 STB PADJ0-I/O PADJ1-I/O PADJ2-I/O PADJ3-I/O Pulse width adjustment data latch RESET PAI0-1 PAI2-1 PAI1-1 PAI3-1 PAI0-128 PAI2-128 PAI1-128 PAI3-128 SI0 SI1 SI2 SI3 CLK RESET F/R PO0-1 PO2-1 PO1-1 PO3-1 PO0-128 PO2-128 SO0 PO1-128 PO3-128 SO1 SO2 data shift register SO3 Pulse width adjustment IAO0-1 STBIAO1-1 STB RESET IAI0-1 IAI1-1 PO4-1 SI4 PO5-1 SI5 CLK RESET F/R IADJ0-I/O IADJ1-I/O D-CLK F/R L-GND PAO0-128 PAO2-128 PAO1-128 PAO3-128 PADJ0-O/I PADJ1-O/I PADJ2-O/I PADJ3-O/I IAO0-128 IAO1-128 Current adjustment data latch IAI0-128 IAI1-128 PO4-128 PO5-128 Current adjustment data shift register IADJ0-O/I IADJ1-O/I SO4 SO5 PIN CONFIGURATION (Gold bump chip) OUT2 OUT1 OUT4 OUT3 OUT124 OUT5 OUT126 OUT125 OUT128 OUT127 VDISP VDISP VDISP D-GND VDISP VDISP ML9361 D-GND D-GND VDISP D-GND D-GND D-GND R-ADJ D-CLK PADJ0-I/O PADJ2-I/O IADJ0-I/O VDD ALL H OFF HZ PL VELSEL RESET IIADJ1-O/I PADJ3-O/I PADJ1-O/I VEL STB PADJ1-I/O PADJ3-I/O IADJ1-I/O HZ ALL L A0 HZ A-CLK L-GND IADJ0-O/I PADJ2-O/I PADJ0-O/I F/R 2/19 PEDL9361-01 OKI Semiconductor ML9361 PIN DESCRIPTION Symbol I/O VDISP VDD D-GND L-GND — VEL I VELSEL I R-ADJ I F/R I IADJ0-I/O IADJ1-I/O I/O IADJ0-O/I IADJ1-O/I O/I PADJ0-I/O PADJ1-I/O PADJ2-I/O PADJ3-I/O PADJ0-O/I PADJ1-O/I PADJ2-O/I PADJ3-O/I I/O O/I D-CLK I STB I RESET I HZ I ALL H I ALL L I OFF HZ I A0 HZ I PL I A-CLK OUT 1 to 128 I O Description VDISP is a power supply pin for anode driver circuit and constant current source circuit. VDD is the logic circuit power supply pin. Power supply D-GND is a ground pin for anode driver circuit and constant current source circuit. L-GND is a ground pin for logic circuit. D-GND and L-GND should be connected outside the LSI. OUT1 to OUT128 output current setting voltage input pin. Power supply Input voltage to this pin is enabled when VELSEL is high, and disabled when it is low. Leave this pin open or input a voltage within the guaranteed operating range. Pin for selecting the output current adjusting voltage for anode driver circuit. Microcontroller • When this pin is low, LSI’s internal voltage (5 V) is selected. • When this pin is high, the input voltage at the VEL pin is selected. OUT1 to OUT128 output current setting resistor connection pin. Resistor Data transfer direction select signal input pin for current adjusting data shift register and pulse width adjusting data shift register. Microcontroller • When this pin is low, data is transferred starting at POn-1 toward POn-128. (n = 1 to 5) • When this pin is high, data is transferred starting at POn-128 toward POn-1. (n = 1 to 5) Anode output current adjusting data input-output pins. When the F/R pin is low, these pins are input pins and data is read into at the rising edge of D-CLK. When the F/R pin is high, these pins are output pins and the output status Microcontroller, changes at the falling edge of D-CLK. or ML9361 on Anode output current adjusting data input-output pins. next stage When the F/R pin is high, these pins are input pins and data is read into at the rising edge of D-CLK. When the F/R pin is low, these pins are output pins and the output status changes at the falling edge of D-CLK. Connected to Anode output pulse width adjusting data input-output pins. When the F/R pin is low, these pins are input pins and data is read into at the rising edge of D-CLK. When the F/R pin is high, these pins are output pins and the output status Microcontroller, changes at the falling edge of D-CLK. or ML9361 on next stage Anode output pulse width adjusting data input-output pins. When the F/R pin is high, these pins are input pins and data is read into at the rising edge of D-CLK. When the F/R pin is low, these pins are output pins and the output status changes at the falling edge of D-CLK. Anode output current adjusting data and anode output pulse width adjusting data transfer Microcontroller clock input pin (Schmitt input) Anode output current adjusting data and anode output pulse width adjusting data latch Microcontroller strobe signal input pin (Schmitt input) Initialization signal input pin. When this pin is set low, the LSI enters the following initial setting states: Microcontroller • Shift register outputs and latch outputs: all “low” • All anode drive signal outputs: “high impedance” Input pin for anode drive signal output control signal. Microcontroller When this pin is low, all anode drive signal outputs are high impedance. Input pin for anode drive signal output control signal (Schmitt input). Microcontroller When this pin is high, all anode drive signal outputs are constant current output. Input pin for anode drive signal output control signal (Schmitt input). Microcontroller When this pin is high, anode drive signal outputs are all low. Input pin for anode drive signal output control signal. Microcontroller Used to set the anode drive signal output condition at the time that is OFF to either low or high impedance with the combination of A0 HZ, P L, and anode output pulse width adjusting data. Input pin for anode drive signal output control signal. Microcontroller Used to set the anode drive signal output condition at the time that dot is OFF to either low or high impedance with the combination of OFF HZ, P L, and anode output pulse width adjusting data. Input pin for anode drive signal output control signal (Schmitt input). Microcontroller Used to set the anode drive signal output condition at the time that dot is OFF to either low or high impedance with the combination of OFF HZ, A0 HZ, and anode output pulse width adjusting data. Microcontroller Anode output pulse width adjusting clock input pin (Schmitt input). Organic EL Anode drive signal output pins for organic EL. anode 3/19 PEDL9361-01 OKI Semiconductor ML9361 FUNCTION TABLE 1. Operation during Transfer of Anode Output Current Adjusting Data and Anode Output Pulse Width Adjusting Data • When F/R is low Input Shift Register Latch PADJ RESET m-I/O, D-CLK IADJ STB X X H L m = 0 to 3 PAO PAO PAO PADJ m-O/I, PO PO PO PO m-1, m-2, m-127, m-128, k-1 k-2 k-127 k-128 IAO IAO IAO IAO IADJ n-1 n-2 n-127 n-128 n-O/I L L L L L n-I/O L Output PAO X L L L L PO PO PO k-1 k-126 k-127 L L L H L H L L Invariable Invariable H L Invariable Invariable L Invariable Invariable H Invariable X n = 0, 1 PO PO PO k-1 k-126 k-127 Invariable Invariable Invariable Invariable PO k-128 PO k-128 Invariable PO PO PO PO k-1 k-2 k-127 k-128 Invariable k = 0 to 5 2. Operation during Transfer of Anode Output Current Adjusting Data and Anode Output Pulse Width Adjusting Data • When F/R is high Input Shift Register Latch PADJ RESET D-CLK m-O/I, IADJ PAO STB PO PO PO PO k-128 k-127 k-2 k-1 n-O/I L X H L X X L L L L PO PO PO k-128 k-3 k-2 PO PO PO k-128 k-3 k-2 PAO m-128, m-127, Output PAO PAO PADJ m-2, m-1, m-I/O, IAO IAO IAO IAO IADJ n-128 n-127 n-2 n-1 n-I/O L L L L L L L L H L H L L Invariable Invariable H L Invariable Invariable L Invariable X H Invariable Invariable Invariable Invariable Invariable PO k-1 PO k-1 Invariable Invariable PO PO PO PO k-128 k-127 k-2 k-1 Invariable 4/19 PEDL9361-01 OKI Semiconductor ML9361 3. Operation of Output Section HZ L ALL H ALL L OFF HZ A0 HZ PL X X X X X X X High impedance H X X X X X X Constant current output H X X X L L L L X Low X Constant current output L X Low H One of PWM data n is “H” Low L All “L” High impedance H X Constant current output L One of PWM data n is “H” High impedance All “L” Low L H L H is “H” Low All “L” High impedance H X Constant current output One of PWM data n L is “H” All “L” H L Note: One of PWM data n L H H OUTn X L H PWM Data n H X H H COMP OUTn One of PWM data n is “H” All “L” High impedance High impedance Low High impedance When setting the STB pin to a high level, do so only when both the HZ pin and the ALL L pin are high or both are low. 5/19 PEDL9361-01 OKI Semiconductor ML9361 OUTPUT WAVEFORMS 1. When OFF HZ, A0 HZ, and P L are all low RESET HZ ALL H ALL L OFF HZ L A0 HZ PL L L PWM DATAm Data: 4 Data: 4 Data: 4 PWM DATAn Data: 15 Data: 0 Data: 0 D-CLK STB A-CLK OUTm HZ OUTn HZ L L L L L L H H 2. When OFF HZ is high and A0 HZ and P L are low RESET HZ ALL H ALL L OFF HZ A0 HZ H PL L L PWM DATAm Data: 4 Data: 4 Data: 4 PWM DATAn Data: 15 Data: 0 Data: 0 D-CLK STB A-CLK OUTm HZ OUTn HZ HZ HZ L HZ L L H H 6/19 PEDL9361-01 OKI Semiconductor ML9361 3. When OFF HZ and A0 HZ are high and P L is low RESET HZ ALL H ALL L OFF HZ H A0 HZ H PL PWM DATAm L PWM DATAn Data: 4 Data: 4 Data: 4 Data: 15 Data: 0 Data: 0 D-CLK STB A-CLK OUTm HZ OUTn HZ HZ L HZ L HZ H HZ H 4. When OFF HZ and A0 HZ are low and P L is controlled by pulse RESET HZ ALL H ALL L OFF HZ L A0 HZ PL L L PWM DATAm Data: 4 Data: 4 Data: 4 PWM DATAn Data: 15 Data: 0 Data: 0 D-CLK STB A-CLK OUTm HZ OUTn HZ L L L L L HZ L L H H 7/19 PEDL9361-01 OKI Semiconductor ML9361 5. When OFF HZ is high, A0 HZ is low, and P L is controlled by pulse RESET HZ ALL H ALL L OFF HZ H A0 HZ L PL PWM DATAm L PWM DATAn Data: 4 Data: 4 Data: 4 Data: 15 Data: 0 Data: 0 D-CLK STB A-CLK OUTm HZ OUTn HZ HZ HZ HZ HZ L HZ HZ L H H 6. When OFF HZ and A0 HZ are high and P L is controlled by pulse RESET HZ ALL H ALL L OFF HZ H A0 HZ H PL L PWM DATAm Data: 4 Data: 4 Data: 4 PWM DATAn Data: 15 Data: 0 Data: 0 D-CLK STB A-CLK OUTm HZ OUTn HZ HZ HZ HZ HZ L HZ HZ HZ H H 8/19 PEDL9361-01 OKI Semiconductor ML9361 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Condition Rating Unit VDD Ta = 25°C –0.3 to +6.5 V VDISP Ta = 25°C –0.3 to +35 V VIN Ta = 25°C –0.3 to VDD + 0.3 V Logic output voltage VOUT Ta = 25°C –0.3 to VDD + 0.3 V EL output current adjustment voltage VEL Ta = 25°C –0.3 to VDISP + 0.3 V EL driver output voltage VOUT-EL Applied to OUT1 to OUT128 –0.3 to VDISP + 0.3 V EL driver output voltage (pulse)*1 VOUT-ELP Applied to OUT1 to OUT128 –VDISP to 2 × VDISP V Applied to OUT1 to OUT128 –1.5 mA IELL (sink) 50 mA Tstg — –40 to +125 °C Logic power supply voltage EL drive power supply voltage (anode) Logic input voltage EL driver output current Storage temperature IELH (source) *1 Consult Oki for customization of pulse width. RECOMMENDED OPERATING CONDITIONS Parameter Symbol Condition Range Unit VDD — 3.0 to 5.5 V VDISP — 8 to 30 V Logic input voltage VIN — 0.0 to VDD V EL output current adjustment voltage VEL — 4 to VDISP – 3 V –0.1 to –1.0 mA Logic power supply voltage EL drive power supply voltage (anode) IELH (source) EL driver output current Junction operating temperature Applied to OUT1 to OUT128 Current adjustment range = 100% IELL (sink) Applied to OUT1 to OUT128 0 to 40 mA Tjop — –40 to +125 °C 9/19 PEDL9361-01 OKI Semiconductor ML9361 ELECTRICAL CHARACTERISTICS DC Characteristics 1 VDD = 3.0 to 5.5 V, VDISP = 8 to 30 V, Tjop = –40 to +125°C Parameter “H” input voltage “L” input voltage Schmitt voltage width Symbol VIH VIL VSH IIH1 “H” input current Anode driver ON current 6 Unit V V VDD = 5.0 V 0.4 1.0 1.6 V VDD = 5.5 V VI = 5.5 V –10 — 10 µA 100 200 µA IIL1 Inputs other than RESET, HZ, ALL H, ALL L, VELSEL, and F/R VDD = 5.5 V VI = 0.0 V –10 — 10 µA IIL2 RESET, HZ, ALL H, ALL L, VELSEL, F/R VDD = 5.5 V VI = 0.0 V –10 — 10 µA VDD = 3.0 V IO = –200 µA 0.8VDD — — V VDD = 3.0 V IO = 200 µA — — 0.2VDD V OUT1 to OUT128 VDISP = 24 V VEL = VO = 15 V VELSEL = high R-ADJ = 30 kΩ Current adjustment range = 100% –465 (–7%) –500 –535 (+7%) µA OUT1 to OUT128 VDISP = 24 V VEL = VO = 15 V VELSEL = high R-ADJ = 30 kΩ Current adjustment range = 66% –306 (–7%) –330 –353 (+7%) µA OUT1 to OUT128 VDISP = 24 V VEL = VO = 15 V VELSEL = high R-ADJ = 30 kΩ Current adjustment range = 33% –153 (–7%) –165 –177 (+7%) µA OUT1 to OUT128 VDISP = 24 V VEL=VO = 7.5 V VELSEL = high R-ADJ = 60 kΩ Current adjustment range = 100% –112 (–10%) –125 –138 (+10%) µA OUT1 to OUT128 VDISP = 24 V VEL = VO = 7.5 V VELSEL= high R-ADJ = 60 kΩ Current adjustment range = 66% –74 (–10%) –82.5 –91 (+10%) µA OUT1 to OUT128 VDISP = 24 V VEL = VO =7.5 V VELSEL = high R-ADJ = 60 kΩ Current adjustment range = 33% –37.5 (–12%) –41.25 –46 (+12%) µA VOL Anode driver ON current 5 Max. VDD 0.2VDD 40 “L” output voltage Anode driver ON current 4 Typ. — — VDD = 5.5 V VI = 5.5 V VOH Anode driver ON current 3 Min. 0.8VDD 0 RESET, HZ, ALL H, ALL L, VELSEL, F/R “H” output voltage Anode driver ON current 2 Condition — — IIH2 “L” input current Anode driver ON current 1 Applicable Pins All input pins All input pins D-CLK, A-CLK, STB, A-CLK, ALL H, ALL L Inputs other than RESET, HZ, ALL H, ALL L, VELSEL, and F/R IELON1 IELON2 IELON3 IELON4 IELON5 IELON6 PADJm-I/O, PADJm-O/I, IADJn-I/O, IADJn-O/I PADJm-I/O, PADJm-O/I, IADJn-I/O, IADJn-O/I 10/19 PEDL9361-01 OKI Semiconductor ML9361 DC Characteristics 2 VDD = 3.0 to 5.5 V, VDISP = 8 to 30 V, Tjop = –40 to +125°C Parameter Symbol Applicable Pins Anode driver ON current 7 IELON7 OUT1 to OUT128 Anode driver ON current 8 IELON8 OUT1 to OUT128 Anode driver ON current 9 IELON9 OUT1 to OUT128 IELL1 OUT1 to OUT128 IELL2 OUT1 to OUT128 IELL3 OUT1 to OUT128 VDISP dependence coefficient for anode driver ON current *1 ∆IELON1 OUT1 to OUT128 VO dependence coefficient for anode driver ON current *2 ∆IELON2 OUT1 to OUT128 Temperature coefficient for anode driver ON current ∆IELON3 OUT1 to OUT128 Relative error between dots (excluding adjoining dots) for anode driver ON current ∆IELON4 OUT1 to OUT128 ∆IELON5 OUT1 to OUT4 OUT63 to OUT66 OUT125 to OUT128 ∆IELON6 OUT1 to OUT128 Anode driver low output current 1 Anode driver low output current 2 Anode driver low output current 3 Tilt inside chip for anode driver ON current *3 Relative error between adjoining dots for anode driver ON current *4 Condition VDISP = 24 V VO = 15 V VELSEL = low R-ADJ = 10 kΩ Current adjustment range = 100% VDISP = 24 V VO = 15 V VELSEL = low R-ADJ = 10 kΩ Current adjustment range = 66% VDISP = 24 V VO = 15 V VELSEL = low R-ADJ = 10 kΩ Current adjustment range = 33% VDISP = 8 V VO = 8 V VDISP = 30 V VO = 30 V VDISP = 8 V VO = 1 V VDISP = 17 to 30 V VEL = VO = 15 V R-ADJ = 30 kΩ Current adjustment range = 100% VDISP = 24 V VEL = 15 V VO = 8 to 21 V R-ADJ = 30 kΩ Current adjustment range = 100% VDISP = 24 V VEL = VO = 15 V R-ADJ = 30 kΩ Current adjustment range = 100% VDISP = 24 V VEL = VO = 15 V R-ADJ = 30 kΩ Current adjustment range = 100% OUT1 to OUT128 = “ON” Inside one chip. VDISP = 24 V VEL = VO = 15 V R-ADJ = 30 kΩ Current adjustment range = 100% OUT1 to OUT128 = “ON” Inside one chip. VDISP = 24 V VEL = VO = 15 V R-ADJ = 30 kΩ Current adjustment range = 100% OUT1 to OUT128 = “ON” Inside one chip. Min. Typ. Max. Unit –415 (–17%) –500 –585 (+17%) µA –274 (–17%) –330 –386 (+17%) µA –137 (–17%) –165 –193 (+17%) µA 16 — — mA 60 — — mA 500 — — µA –2.5 0 2.5 %/V –2.5 0 2.5 %/V –0.1 0 0.1 %/°C –5 0 5 % –3 0 3 % –2 0 2 % 11/19 PEDL9361-01 OKI Semiconductor *1 VDISP dependence coefficient depends on the following conditions: I(VDISP = nV): Anode driver ON current at VDISP = nV. ∆IELON1 = [ I(VDISP = nV) − I(VDISP = (n+1)V) ]/{ [ I(VDISP = nV) + I(VDISP = (n+1)V) ]/2 } × 100 *2 VO dependence coefficient depends on the following conditions: I(VO = nV): Anode driver ON current at VO = nV. ∆IELON2 = [ I(VO = nV) − I(VO = (n−1)V) ]/{ [ I(VO = nV) + I(VO = (n−1)V) ]/2 } × 100 *3 Tilt inside chip depends on the following conditions: Cave: Average output current of OUT1 to 4, OUT63 to 66, and OUT125 to 128. Lave: Average output current of OUT1 to 4. Rave: Average output current of OUT125 to 128. ∆IELON5 = (Lave – Cave)/Cave ∆IELON5 = (Rave – Cave)/Cave *4 A relative error between adjoining dots depends on the following condition: (IELON(N+1) – IELON(N))IELON(N) ML9361 12/19 PEDL9361-01 OKI Semiconductor ML9361 Supply Current VDD = 3.0 to 5.5 V, VDISP = 8 to 30 V, Tjop = –40 to +125°C Parameter Symbol Applicable Pins IDISP1 VDISP IDISP2 VDISP Supply current VDD IDD1 VDD VDD IDD2 VDD Condition VDISP = 30 V VEL = 15 V A-CLK = 5 MHz R-ADJ = 30 kΩ Current adjustment range = 100% Output = open PWM data = other than “0” VDD = 0 V VDISP = 30 V VEL = 15 V R-ADJ = 30 kΩ Output = open VDD = 5.5 V D-CLK = 5 MHz DATA = “1010.....10” VDD = 5.5 V D-CLK, A-CLK = 5 MHz DATA = “1010.....10” VDD = 5.5 V A-CLK = 5 MHz DATA = “1010.....10” VDD = 5.5 V, D-CLK = halted RESET = 0 V All the other inputs are also 0 V. Min. Typ. Max. Unit — — 5.0 mA — — 300 µA — — 18 mA — — 20 mA — — 5 mA — — 100 µA 13/19 PEDL9361-01 OKI Semiconductor ML9361 AC Characteristics VDD = 3.0 to 5.5 V, VDISP = 8 to 30 V, Tjop = –40 to +125°C Parameter D-CLK frequency D-CLK pulse width A-CLK frequency A-CLK pulse width Symbol fDCLK tDCW fACLK tACW Condition — — — — Min. 0 50 0 50 Typ. — Max. 5.0 — 5.0 — Unit MHz ns MHz ns — 50 — — ns — — 50 — — ns tSTBW D-CLK IADJn-I PADJm-I D-CLK IADJn-I PADJm-I STB — 50 — — ns tALSS ALL L, STB — 100 — — ns tSALH ALL L, STB — 100 — — ns tHZSS HZ, STB — 100 — — ns tSHZH HZ, STB — 100 — — ns tALDCS ALL L, D-CLK — 100 — — ns tDCALH ALL L, D-CLK — 100 — — ns tALACS ALL L, A-CLK — 100 — — ns tACALH ALL L, A-CLK — 100 — — ns tPLW PL — 100 — — ns tPLALS ALL L, P L — 100 — — ns tSTPLS P L, STB — 100 — — ns tDCSH D-CLK STB — 50 — — ns DATA→D-CLK setup time tDS D-CLK→DATA hold time tDH STB pulse width ALL L→STB setup time STB→ALL L hold time HZ→STB setup time STB→HZ hold time ALL L→D-CLK setup time D-CLK→ALL L hold time ALL L→A-CLK setup time A-CLK→ALL L hold time P L pulse width P L→ALL L setup time STB→P L setup time D-CLK→STB hold time RESET pulse width Applicable pins D-CLK D-CLK A-CLK A-CLK tRW RESET — 100 — — ns RESET execution time tRSON RESET — 250 — — ns A-CLK → output delay time tDr tDf HZ, ALL H ALL L, P L A-CLK OUT1 to 128 — — — 2.0 µs Input signal rise/fall time tr tf All inputs — — — 500 ns 14/19 PEDL9361-01 OKI Semiconductor ML9361 TIMING DIAGRAM Data Input 0.9VDD VDD tRSON RESET tRW VIH VIL VIH ALL L VIL tALDCS 1/fDCLK tDCW tDCALH VIH VIL D-CLK tDS IADJn-I/O IADJn-O/I PADJm-I/O PADJm-O/I tDH VIH VIL tDCSH tSTBW STB VIH ALL L VIL VIL tALACS 1/fACLK tACW tACALH VIH VIL A-CLK tALSS tSALH STB tSHZH HZ VIH VIL tPLW VIH PL VIL tHZSS tSTPLS STB tr All inputs tf 0.9VDD 0.1VDD 15/19 PEDL9361-01 OKI Semiconductor ML9361 DESCRIPTION OF OPERATION Initial Settings Following initial settings can be made by setting the RESET pin to low. • The shift register outputs and latch circuit outputs become all low. • Anode drive signal output pins (OUT1 to 128) become high impedance. Anode Output Current Adjustment 1. Output current adjustment for entire output Output current of anode drive signal output pins (OUT1 to OUT128) can be adjusted, as a batch adjustment for all the output pins. Output current is adjusted by varying the value of the resistor connected between the R-ADJ pin and GND. Output current (typ.) at the time that the VELSEL pin is “high” and “low” is given by the following expressions: [When the VELSEL pin is “high”] Output current (typ.) = VEL pin voltage ÷ R-ADJ resistance value [When the VELSEL pin is “low”] Output current (typ.) = 5 V ÷ R-ADJ resistance value 2. Output current adjustment for each output Output current of anode drive signal output pins (OUT1 to OUT128) can be adjusted for each output pin. Adjustment of each output current is made by bit data IADJ0-n and IADJ1-n. This 2-bit data is written in the shift register at the rising edge of the D-CLK signal and latched at the rising edge of the STB signal. Relation between IADJ0-n, IADJ1-n, and output current is shown below. IADJ1-n IADJ0-n Current adjustment range 0 0 0% 0 1 33% 1 0 66% 1 1 100% 16/19 PEDL9361-01 OKI Semiconductor ML9361 3. Output pulse width adjustment Output pulse width of anode drive signal output pins (OUT1 to OUT128) can be adjusted for each output pin. Adjustment of each output pulse width is made by 4-bit data PADJ0-n, PADJ1-n, PADJ2-n, and PADJ3-n. This 4-bit data is written in the shift register at the rising edge of the D-CLK signal and latched at the rising edge of the STB signal. An anode drive signal output pin is configured as constant current output until the number of A-CLK pulses becomes equal to the output data of 4 bits of PADJ0-n, PADJ1-n, PADJ2-n, and PADJ3-n. When they have matched, the output becomes low or high impedance at the rising edge of the A-CLK pulse that has matched the output data of PADJ0-n, PADJ1-n, PADJ2-n, and PADJ3-n. Relation between PADJ0-n, PADJ1-n, PADJ2-n, and PADJ3-n and output pulse width is shown below. PADJ3-n PADJ2-n PADJ1-n PADJ0-n Output pulse width 0 0 0 0 0 0 0 0 1 1 0 0 1 0 2 0 0 1 1 3 0 1 0 0 4 0 1 0 1 5 0 1 1 0 6 0 1 1 1 7 1 0 0 0 8 1 0 0 1 9 1 0 1 0 10 1 0 1 1 11 1 1 0 0 12 1 1 0 1 13 1 1 1 0 14 1 1 1 1 15 Setting of Output Condition When Dot is OFF The output condition when dot is OFF is set with the combination of HZ, ALL L, OFF HZ, A0 HZ, and P L signals. See “3. Operation of Output Section” in “FUNCTION TABLE” and the section of “OUTPUT WAVEFORMS”. Power Applying Sequence It is possible to apply power first to VDD or VDISP. When power is applied to VDISP, and VDD is 2.5 V or less, following operating states occur. • Constant current source circuit does not operate. • Anode drive signal output pins (OUT1 to 128) become high impedance. Make the RESET pin high at least 250 ns after applying power to VDD. (Refer to RESET execution time in AC Characteristics.) 17/19 PEDL9361-01 OKI Semiconductor ML9361 REVISION HISTORY Document No. PEDL9361-01 Date Dec. 12, 2002 Page Previous Current Edition Edition – – Description Preliminary edition 1 18/19 PEDL9361-01 OKI Semiconductor ML9361 NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party’s right which may result from the use thereof. 6. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2002 Oki Electric Industry Co., Ltd. 19/19