IRF IRF7799L2TR1PBF

PD - 96266
IRF7799L2TRPbF
IRF7799L2TR1PbF
DirectFET™ Power MOSFET ‚
RoHS Compliant, Halogen Free 
l Lead-Free (Qualified up to 260°C Reflow)
l Ideal for High Performance Isolated Converter
Primary Switch Socket
l Optimized for Synchronous Rectification
l Low Conduction Losses
l High Cdv/dt Immunity
l Low Profile (<0.7mm)
l Dual Sided Cooling Compatible 
l Compatible with existing Surface Mount Techniques 
l Industrial Qualified
l
Typical values (unless otherwise specified)
VDSS
SC
M2
RDS(on)
250V min ± 30V max
Qg
D
32mΩ@ 10V
tot
Qgd
Vgs(th)
110nC
39nC
4.0V
G
S
S
S
S
S
S
S
S
D
DirectFET™ ISOMETRIC
L8
Applicable DirectFET Outline and Substrate Outline 
SB
VGS
M4
L4
L6
L8
Description
The IRF7799L2TR/TR1PbF combines the latest HEXFET® Power MOSFET Silicon technology with the advanced DirectFETTM packaging to
achieve the lowest on-state resistance in a package that has a footprint smaller than a D2PAK and only 0.7 mm profile. The DirectFET package
is compatible with existing layout geometries used in power applications, PCB assembly equipment and vapor phase, infra-red or convection
soldering techniques, when application note AN-1035 is followed regarding the manufacturing methods and processes. The DirectFET package
allows dual sided cooling to maximize thermal transfer in power systems.
The IRF7799L2TR/TR1PbF is optimized for high frequency switching and synchronous rectification applications. The reduced total losses
in the device coupled with the high level of thermal performance enables high efficiency and low temperatures, which are key for system
reliability improvements, and makes this device ideal for high performance power converters.
Absolute Maximum Ratings
Max.
Parameter
VDS
g
Pulsed Drain Current
Single Pulse Avalanche Energy
Avalanche Current
g
h
200
A
mJ
A
140
120
100
80
TJ = 125°C
60
T J = 25°C
Vgs = 7.0V
Vgs = 8.0V
Vgs = 10V
Vgs = 15V
55
160
50
45
40
35
30
40
T J = 25°C
25
20
4
8
12
16
20
VGS, Gate -to -Source Voltage (V)
Fig 1. Typical On-Resistance vs. Gate Voltage
Notes:
 Click on this section to link to the appropriate technical paper.
‚ Click on this section to link to the DirectFET Website.
ƒ Surface mounted on 1 in. square Cu board, steady state.
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V
60
ID = 21A
180
Typical RDS(on) (mW)
RDS(on), Drain-to -Source On Resistance (m Ω)
VGS
ID @ TC = 25°C
ID @ TC = 100°C
ID @ TA = 25°C
ID @ TC = 25°C
IDM
EAS
IAR
Units
250
±30
35
25
6.6
375
140
325
21
Drain-to-Source Voltage
Gate-to-Source Voltage
Continuous Drain Current, VGS @ 10V (Silicon Limited)f
Continuous Drain Current, VGS @ 10V (Silicon Limited)f
Continuous Drain Current, VGS @ 10V (Silicon Limited)e
Continuous Drain Current, VGS @ 10V (Package Limited) f
0
20
40
60
80
100
ID, Drain Current (A)
Fig 2. Typical On-Resistance vs. Drain Current
„ TC measured with thermocouple mounted to top (Drain) of part.
… Repetitive rating; pulse width limited by max. junction temperature.
† Starting TJ = 25°C, L = 1.42mH, RG = 25Ω, IAS = 21A.
‡ Pulse width ≤ 400µs; duty cycle ≤ 2%.
1
08/31/09
IRF7799L2TR/TR1PbF
Static @ TJ = 25°C (unless otherwise specified)
Min.
Typ. Max. Units
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Parameter
250
–––
–––
0.12
–––
–––
VGS(th)
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
–––
3.0
32
4.0
38
5.0
∆VGS(th)/∆TJ
IDSS
Gate Threshold Voltage Coefficient
Drain-to-Source Leakage Current
–––
–––
-13
–––
–––
20
Gate-to-Source Forward Leakage
–––
–––
–––
–––
1
100
Gate-to-Source Reverse Leakage
Forward Transconductance
–––
54
–––
–––
-100
–––
Total Gate Charge
Pre-Vth Gate-to-Source Charge
–––
–––
110
26
165
–––
Post-Vth Gate-to-Source Charge
Gate-to-Drain Charge
–––
–––
5.7
39
–––
Gate Charge Overdrive
Switch Charge (Qgs2 + Qgd)
–––
–––
39
45
–––
–––
Output Charge
Gate Resistance
–––
–––
33
0.73
–––
–––
Turn-On Delay Time
Rise Time
–––
–––
36.3
33.5
–––
–––
Turn-Off Delay Time
Fall Time
–––
–––
73.9
26.6
–––
–––
Input Capacitance
Output Capacitance
–––
–––
6714
606
–––
–––
BVDSS
∆ΒVDSS/∆TJ
RDS(on)
IGSS
gfs
Qg
Qgs1
Qgs2
Qgd
Qgodr
Qsw
Qoss
RG
td(on)
tr
td(off)
tf
Ciss
Coss
Crss
Coss
Coss
Conditions
VGS = 0V, ID = 250µA
V
Reference
to 25°C, ID = 2mA
V/°C
mΩ VGS = 10V, ID = 21A
V
i
VDS = VGS, ID = 250µA
mV/°C
µA VDS = 250V, VGS = 0V
1mA VDS = 250V, VGS = 0V, TJ = 125°C
nA
VGS = 20V
VGS = -20V
S
VDS = 50V, ID = 21A
nC
VDS = 125V
VGS = 10V
ID = 21A
See Fig. 9
nC
VDS = 16V, VGS = 0V
Ω
i
VDD = 125V, VGS = 10V
ns
ID = 21A
RG=6.2Ω
VGS = 0V
VDS = 25V
pF
Reverse Transfer Capacitance
Output Capacitance
–––
–––
157
5063
–––
–––
Output Capacitance
–––
217
–––
Min.
Typ. Max. Units
ƒ = 1.0MHz
VGS = 0V, VDS = 1.0V, f=1.0MHz
VGS = 0V, VDS = 80V, f=1.0MHz
Diode Characteristics
Parameter
IS
Continuous Source Current
ISM
(Body Diode)
Pulsed Source Current
VSD
trr
Qrr
2
g
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
–––
–––
–––
–––
Conditions
MOSFET symbol
35
A
showing the
integral reverse
p-n junction diode.
TJ = 25°C, IS = 21A, VGS = 0V
TJ = 25°C, IF = 21A, VDD = 50V
140
–––
–––
1.3
V
–––
–––
132
1412
198
2118
ns
nC
i
di/dt = 100A/µs
i
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IRF7799L2TR/TR1PbF
Absolute Maximum Ratings
f
f
c
Max.
Parameter
Units
125
63
4.3
270
-55 to + 175
Power Dissipation
Power Dissipation
Power Dissipation
Peak Soldering Temperature
Operating Junction and
Storage Temperature Range
PD @TC = 25°C
PD @TC = 100°C
PD @TA = 25°C
TP
TJ
TSTG
W
°C
Thermal Resistance
RθJA
RθJA
RθJA
RθJ-can
RθJ-PCB
e
j
k
Parameter
Junction-to-Ambient
Junction-to-Ambient
Junction-to-Ambient
Junction-to-Can
Junction-to-PCB Mounted
fl
Typ.
Max.
Units
–––
12.5
20
–––
–––
35
–––
–––
1.2
0.5
°C/W
Thermal Response ( Z thJC )
10
1
D = 0.50
0.20
0.10
0.1
0.05
τJ
0.02
0.01
0.01
R1
R1
τJ
τ1
R2
R2
τC
τ1
τ2
τ2
Ci= τi/Ri
Ci i/Ri
1E-005
0.0001
0.001
0.8117
τi (sec)
0.000787
0.006586
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
SINGLE PULSE
( THERMAL RESPONSE )
0.001
1E-006
Ri (°C/W)
0.38829
τ
0.01
0.1
1
t1 , Rectangular Pulse Duration (sec)
Fig 3. Maximum Effective Transient Thermal Impedance, Junction-to-Case „
Notes:
‰ Mounted on minimum footprint full size board with metalized
ƒ Surface mounted on 1 in. square Cu board, steady state.
„ TC measured with thermocouple incontact with top (Drain) of part. back and with small clip heatsink.
Š Rθ is measured at TJ of approximately 90°C.
ˆ Used double sided cooling, mounting pad with large heatsink.
ƒ Surface mounted on 1 in. square Cu
board (still air).
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‰ Mounted on minimum footprint full size board with metalized
back and with small clip heatsink. (still air)
3
IRF7799L2TR/TR1PbF
1000
1000
100
BOTTOM
VGS
15V
10V
8.0V
7.0V
6.5V
6.0V
5.5V
5.0V
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
VGS
15V
10V
8.0V
7.0V
6.5V
6.0V
5.5V
5.0V
10
1
5.0V
100
BOTTOM
10
1
Tj = 175°C
≤60µs PULSE WIDTH
Tj = 25°C
≤60µs PULSE WIDTH
0.1
0.1
0.1
1
10
100
0.1
V DS, Drain-to-Source Voltage (V)
100
3.0
RDS(on) , Drain-to-Source On Resistance
(Normalized)
VDS = 50V
≤60µs PULSE WIDTH
100
T J = 175°C
TJ = 25°C
TJ = -40°C
10
1
ID = 21A
VGS = 10V
2.5
2.0
1.5
1.0
0.5
0.0
0.1
3
4
5
6
-60 -40 -20 0 20 40 60 80 100120140160180
7
T J , Junction Temperature (°C)
VGS, Gate-to-Source Voltage (V)
Fig 6. Typical Transfer Characteristics
100000
Fig 7. Normalized On-Resistance vs. Temperature
14.0
VGS, Gate-to-Source Voltage (V)
VGS = 0V,
f = 1 MHZ
C iss = C gs + C gd, C ds SHORTED
C rss = C gd
C oss = C ds + C gd
C, Capacitance (pF)
10
Fig 5. Typical Output Characteristics
1000
ID, Drain-to-Source Current (A)
1
V DS, Drain-to-Source Voltage (V)
Fig 4. Typical Output Characteristics
10000
Ciss
Coss
1000
Crss
ID= 21A
12.0
VDS= 200V
VDS= 125V
VDS= 50V
10.0
8.0
6.0
4.0
2.0
0.0
100
1
10
100
1000
VDS, Drain-to-Source Voltage (V)
Fig 8. Typical Capacitance vs.Drain-to-Source Voltage
4
5.0V
0
20
40
60
80
100 120 140 160
QG, Total Gate Charge (nC)
Fig 9. Typical Total Gate Charge vs
Gate-to-Source Voltage
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IRF7799L2TR/TR1PbF
1000
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
1000
100
OPERATION IN THIS AREA
LIMITED BY R DS(on)
100
TJ = 175°C
TJ = 25°C
TJ = -40°C
10
1
10
100µsec
DC
1msec
1
10msec
Tc = 25°C
Tj = 175°C
Single Pulse
VGS = 0V
0.1
0.1
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
1
10
VSD, Source-to-Drain Voltage (V)
Fig 10. Typical Source-Drain Diode Forward Voltage
1000
Fig11. Maximum Safe Operating Area
6.0
VGS(th) , Gate Threshold Voltage (V)
40
ID, Drain Current (A)
100
VDS, Drain-to-Source Voltage (V)
30
20
10
5.0
4.0
3.0
ID = 250µA
ID = 1.0mA
ID = 1.0A
2.0
1.0
0
25
50
75
100
125
150
-75 -50 -25
175
0
25 50 75 100 125 150 175
T J , Temperature ( °C )
T C , Case Temperature (°C)
Fig 13. Typical Threshold Voltage vs.
Junction Temperature
Fig 12. Maximum Drain Current vs. Case Temperature
EAS , Single Pulse Avalanche Energy (mJ)
1400
ID
1.33A
2.53A
BOTTOM 21A
1200
TOP
1000
800
600
400
200
0
25
50
75
100
125
150
175
Starting T J , Junction Temperature (°C)
Fig 14. Maximum Avalanche Energy Vs. Drain Current
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5
IRF7799L2TR/TR1PbF
100
Avalanche Current (A)
Duty Cycle = Single Pulse
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ∆Tj = 150°C and
Tstart =25°C (Single Pulse)
0.01
10
0.05
0.10
1
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ∆Τ j = 25°C and
Tstart = 150°C.
0.1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 15. Typical Avalanche Current Vs.Pulsewidth
350
TOP
Single Pulse
BOTTOM 1.0% Duty Cycle
ID = 21A
300
EAR , Avalanche Energy (mJ)
Notes on Repetitive Avalanche Curves , Figures 13, 14:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of Tjmax. This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is
not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 16a, 16b.
4. PD (ave) = Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed
Tjmax (assumed as 25°C in Figure 15, 16).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see figure 11)
250
200
150
100
50
0
25
50
75
100
125
150
175
Starting T J , Junction Temperature (°C)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·ta
Fig 16. Maximum Avalanche Energy Vs. Temperature
D.U.T
Driver Gate Drive
+
ƒ
+
‚
-
„
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
+

RG
•
•
•
•
di/dt controlled by RG
Driver same type as D.U.T.
I SD controlled by Duty Factor "D"
D.U.T. - Device Under Test
VDD
P.W.
Period
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
D=
Period
P.W.
+
-
Re-Applied
Voltage
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Body Diode
VDD
Forward Drop
Inductor
Current
Inductor Curent
Ripple ≤ 5%
ISD
* VGS = 5V for Logic Level Devices
Fig 17. Diode Reverse Recovery Test Circuit for N-Channel HEXFET® Power MOSFETs
6
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IRF7799L2TR/TR1PbF
Id
Vds
Vgs
L
VCC
DUT
0
20K
1K
Vgs(th)
S
Qgodr
Fig 18a. Gate Charge Test Circuit
Qgd
Qgs2 Qgs1
Fig 18b. Gate Charge Waveform
V(BR)DSS
15V
DRIVER
L
VDS
tp
D.U.T
V
RGSG
+
- VDD
IAS
20V
tp
A
I AS
0.01Ω
Fig 19b. Unclamped Inductive Waveforms
Fig 19a. Unclamped Inductive Test Circuit
VDS
V GS
RG
RD
VDS
90%
D.U.T.
+
- VDD
V10V
GS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Fig 20a. Switching Time Test Circuit
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10%
VGS
td(on)
tr
t d(off)
tf
Fig 20b. Switching Time Waveforms
7
IRF7799L2TR/TR1PbF
DirectFET™ Board Footprint, L8 (Large Size Can).
Please see AN-1035 for DirectFET assembly details and stencil and substrate design recommendations
G = GATE
D = DRAIN
S = SOURCE
D
D
D
8
S
S
S
S
G
D
D
S
S
S
S
D
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IRF7799L2TR/TR1PbF
DirectFET™ Outline Dimension, L8 Outline (LargeSize Can).
Please see AN-1035 for DirectFET assembly details and stencil and substrate design recommendations
DIMENSIONS
IMPERIAL
METRIC
MAX MIN
CODE MIN
MAX
9.15 0.356
A
9.05
0.360
7.10 0.270
B
6.85
0.280
6.00 0.232
5.90
C
0.236
0.65 0.022
D
0.55
0.026
0.62 0.023
E
0.58
0.024
1.22 0.046
F
1.18
0.048
1.02 0.015
G
0.98
0.017
0.77 0.029
H
0.73
0.030
0.42 0.015
J
0.38
0.017
1.47 0.053
K
1.34
0.058
2.69 0.099
L
2.52
0.106
M
0.616 0.676 0.0235 0.0274
N
0.020 0.080 0.0008 0.0031
0.18 0.003
P
0.09
0.007
DirectFET™ Part Marking
GATE MARKING
LOGO
PART NUMBER
BATCH NUMBER
DATE CODE
Line above the last character of
the date code indicates "Lead-Free"
Note: For the most current drawing please refer to IR website at http://www.irf.com/package
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9
IRF7799L2TR/TR1PbF
DirectFET™ Tape & Reel Dimension (Showing component orientation).
NOTE: Controlling dimensions in mm Std reel
quantity is 4000 parts. (ordered as IRF7799L2PBF).
REEL DIMENSIONS
STANDARD OPTION (QTY 4000)
METRIC
IMPERIAL
CODE
MIN
MIN
MAX
MAX
A
12.992
330.0
N.C
N.C
B
0.795
20.2
N.C
N.C
0.504
C
12.8
0.520
13.2
D
0.059
1.5
N.C
N.C
E
3.937
100.0
N.C
N.C
F
N.C
N.C
0.889
22.4
G
0.646
16.4
0.724
18.4
H
0.626
15.9
0.724
18.4
LOADED TAPE FEED DIRECTION
NOTE: CONTROLLING
DIMENSIONS IN MM
CODE
A
B
C
D
E
F
G
H
10
DIMENSIONS
IMPERIAL
METRIC
MIN
MAX
MIN
MAX
0.469
0.476
11.90
12.10
0.154
0.161
3.90
4.10
0.626
0.642
15.90
16.30
0.291
0.299
7.40
7.60
0.284
0.291
7.20
7.40
0.390
0.398
10.10
9.90
0.059
NC
NC
1.50
0.059
0.063
1.60
1.50
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IRF7799L2TR/TR1PbF
Part number
Package Type
IRF7799L2TRPbF
IRF7799L2TR1PbF
DirectFET2 Large Can
DirectFET2 Large Can
Standard Pack
Form
Quantity
Tape and Reel
4000
Tape and Reel
1000
Note
"TR" suffix
"TR1" suffix
†
Qualification Information
Industrial
Qualification level
††
†††
(per JEDEC JESD47F
guidelines)
Comments: This family of products has passed JEDEC’s Industrial
qualification. IR’s Consumer qualification level is granted by extension of the
higher Industrial level.
Moisture Sensitivity Level
MSL1
DFET2
(per JEDEC J-STD-020D†††)
RoHS Compliant
†
††
†††
Yes
Qualification standards can be found at International Rectifier’s web site
http://www.irf.com/product-info/reliability
Higher qualification ratings may be available should the user have such requirements.
Please contact your International Rectifier sales representative for further information:
http://www.irf.com/whoto-call/salesrep/
Applicable version of JEDEC standard at the time of product release.
Data and specifications subject to change without notice.
This product has been designed and qualified to MSL1 rating for the Industrial market.
Additional storage requirement details for DirectFET products can be found in application note AN1035 on IR’s Web site.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.08/2009
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11