TI CSD17559Q5

CSD17559Q5
www.ti.com
SLPS374 – NOVEMBER 2012
30V N-Channel NexFET™ Power MOSFETs
Check for Samples: CSD17559Q5
PRODUCT SUMMARY
FEATURES
1
•
•
•
•
•
•
•
•
2
TA = 25°C unless otherwise stated
Extremely Low Resistance
Ultralow Qg and Qgd
Low Thermal Resistance
Avalanche Rated
Pb Free Terminal Plating
RoHS Compliant
Halogen Free
SON 5-mm × 6-mm Plastic Package
•
•
Point-of-Load Synchronous Buck in
Networking, Telecom, and Computing Systems
Synchronous Rectification
Active ORing and Hotswap Applications
30
V
Qg
Gate Charge Total (4.5V)
39
nC
Qgd
Gate Charge Gate to Drain
RDS(on)
Drain to Source On Resistance
VGS(th)
Threshold Voltage
The NexFET™ power MOSFET has been designed
to minimize losses in synchronous rectification and
other power conversion applications.
Top View
1
8
D
S
2
7
D
S
3
6
D
G
4
5
D
9.3
nC
VGS = 4.5V
1.15
mΩ
VGS = 10V
0.95
mΩ
1.4
V
Device
Package
Media
Qty
Ship
CSD17559Q5
SON 5-mm × 6-mm
Plastic Package
13-Inch
Reel
2500
Tape and
Reel
ABSOLUTE MAXIMUM RATINGS
TA = 25°C unless otherwise stated
VALUE
UNIT
VDS
Drain to Source Voltage
30
V
VGS
Gate to Source Voltage
±20
V
Continuous Drain Current (Package limited),
TC = 25°C
100
Continuous Drain Current (Silicon limited),
TC = 25°C
257
DESCRIPTION
S
UNIT
Drain to Source Voltage
ORDERING INFORMATION
APPLICATIONS
•
TYPICAL VALUE
VDS
ID
A
Continuous Drain Current(1)
40
IDM
Pulsed Drain Current, TA = 25°C(1)(2)
250
A
PD
Power Dissipation(1)
3.2
W
TJ,
TSTG
Operating Junction and Storage
Temperature Range
–55 to 150
°C
EAS
Avalanche Energy, single pulse
ID = 104A, L = 0.1mH, RG = 25Ω
541
mJ
A
(1) Typical RθJA = 40°C/W on 1-inch2 (6.45-cm2), 2-oz. (0.071mm thick) Cu pad on a 0.06-inch (1.52-mm) thick FR4 PCB.
(2) Pulse duration ≤300μs, duty cycle ≤2%
D
P0093-01
SPACE
RDS(on) vs VGS
SPACE
GATE CHARGE
10
TC = 25°C Id = 40A
TC = 125ºC Id = 40A
5
VGS - Gate-to-Source Voltage (V)
RDS(on) - On-State Resistance (mΩ)
6
4
3
2
1
0
0
2
4
6
8
10
VGS - Gate-to- Source Voltage (V)
12
G001
ID = 40A
VDS =15V
8
6
4
2
0
0
10
20
30
40
50
60
Qg - Gate Charge (nC)
70
80
90
G001
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NexFET is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012, Texas Instruments Incorporated
CSD17559Q5
SLPS374 – NOVEMBER 2012
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ELECTRICAL CHARACTERISTICS
(TA = 25°C unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Static Characteristics
BVDSS
Drain to Source Voltage
VGS = 0V, IDS = 250μA
IDSS
Drain to Source Leakage Current
VGS = 0V, VDS = 24V
IGSS
Gate to Source Leakage Current
VDS = 0V, VGS = 20V
VGS(th)
Gate to Source Threshold Voltage
VDS = VGS, IDS = 250μA
RDS(on)
Drain to Source On Resistance
gfs
Transconductance
30
1.2
V
1
μA
100
nA
1.4
1.7
V
VGS = 4.5V, IDS = 40A
1.15
1.5
mΩ
VGS = 10V, IDS = 40A
0.95
1.15
mΩ
VDS = 15V, IDS = 40A
235
S
Dynamic Characteristics
Ciss
Input Capacitance
VGS = 0V, VDS = 15V,
f = 1MHz
7070
9200
pF
Coss
Output Capacitance
1780
2314
pF
Crss
Reverse Transfer Capacitance
87
113
pF
RG
Series Gate Resistance
1.2
2.4
Ω
Qg
Gate Charge Total (4.5V)
39
51
nC
Qgd
Gate Charge Gate to Drain
9.3
nC
Qgs
Gate Charge Gate to Source
14.4
nC
Qg(th)
Gate Charge at Vth
8.3
nC
Qoss
Output Charge
50
nC
td(on)
Turn On Delay Time
20
ns
tr
Rise Time
41
ns
td(off)
Turn Off Delay Time
32
ns
tf
Fall Time
14
ns
VDS = 15V, IDS = 40A
VDS = 15V, VGS = 0V
VDS = 15V, VGS = 4.5V,
IDS = 40A,RG = 2Ω
Diode Characteristics
VSD
Diode Forward Voltage
Qrr
Reverse Recovery Charge
trr
Reverse Recovery Time
ISD = 40A, VGS = 0V
0.8
VDD= 15V, IF = 40A, di/dt = 300A/μs
1
V
80
nC
37
ns
THERMAL CHARACTERISTICS
(TA = 25°C unless otherwise stated)
MAX
UNIT
RθJC
Thermal Resistance Junction to Case (1)
PARAMETER
1.2
°C/W
RθJA
Thermal Resistance Junction to Ambient (1) (2)
50
°C/W
(1)
(2)
2
MIN
TYP
RθJC is determined with the device mounted on a 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu pad on a 1.5-inch × 1.5-inch (3.81-cm ×
3.81-cm), 0.06-inch (1.52-mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board design.
Device mounted on FR4 material with 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu.
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Product Folder Links: CSD17559Q5
CSD17559Q5
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GATE
SLPS374 – NOVEMBER 2012
GATE
Source
N-Chan 5x6 QFN TTA MIN Rev3
N-Chan 5x6 QFN TTA MAX Rev3
Max RθJA = 50°C/W
when mounted on
1 inch2 (6.45 cm2) of 2oz. (0.071-mm thick)
Cu.
Source
Max RθJA = 125°C/W
when mounted on a
minimum pad area of
2-oz. (0.071-mm thick)
Cu.
DRAIN
DRAIN
M0137-02
M0137-01
TYPICAL MOSFET CHARACTERISTICS
(TA = 25°C unless otherwise stated)
Figure 1. Transient Thermal Impedance
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3
CSD17559Q5
SLPS374 – NOVEMBER 2012
www.ti.com
TYPICAL MOSFET CHARACTERISTICS (continued)
(TA = 25°C unless otherwise stated)
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
200
160
IDS - Drain-to-Source Current (A)
IDS - Drain-to-Source Current (A)
180
140
120
100
80
60
40
VGS =10V
VGS =6V
VGS =4.5V
20
0
0
0.1
0.2
0.3
VDS - Drain-to-Source Voltage (V)
180
160
140
120
100
80
60
TC = 125°C
TC = 25°C
TC = −55°C
40
20
0
0.4
VDS = 5V
0
Figure 2. Saturation Characteristics
TEXT ADDED FOR SPACING
G001
TEXT ADDED FOR SPACING
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
C − Capacitance (pF)
8
6
4
10000
1000
100
2
0
10
20
30
40
50
60
Qg - Gate Charge (nC)
70
80
10
90
0
10
20
VDS - Drain-to-Source Voltage (V)
G001
Figure 4. Gate Charge
30
G001
Figure 5. Capacitance
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
2
6
RDS(on) - On-State Resistance (mΩ)
ID = 250uA
VGS(th) - Threshold Voltage (V)
5
100000
ID = 40A
VDS =15V
0
1.8
1.6
1.4
1.2
1
0.8
0.6
−75
−25
25
75
125
TC - Case Temperature (ºC)
Figure 6. Threshold Voltage vs. Temperature
4
2
3
4
VGS - Gate-to-Source Voltage (V)
Figure 3. Transfer Characteristics
10
VGS - Gate-to-Source Voltage (V)
1
G001
175
TC = 25°C Id = 40A
TC = 125ºC Id = 40A
5
4
3
2
1
0
0
G001
2
4
6
8
10
VGS - Gate-to- Source Voltage (V)
12
G001
Figure 7. On-State Resistance vs. Gate-to-Source Voltage
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Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: CSD17559Q5
CSD17559Q5
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SLPS374 – NOVEMBER 2012
TYPICAL MOSFET CHARACTERISTICS (continued)
(TA = 25°C unless otherwise stated)
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
100
VGS = 4.5V
VGS = 10V
1.8
ID =40A
ISD − Source-to-Drain Current (A)
Normalized On-State Resistance
2
1.6
1.4
1.2
1
0.8
0.6
0.4
−75
−25
25
75
125
TC - Case Temperature (ºC)
175
TC = 25°C
TC = 125°C
10
1
0.1
0.01
0.001
0.0001
0
0.2
0.4
0.6
0.8
VSD − Source-to-Drain Voltage (V)
G001
Figure 8. Normalized On-State Resistance vs. Temperature
G001
Figure 9. Typical Diode Forward Voltage
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
300
10000
DC
10 ms
1 ms
100 us
IAV - Peak Avalanche Current (A)
IDS - Drain-to-Source Current (A)
1
1000
100
10
1
Single Pulse
Typical RthetaJA = 100ºC/W(min Cu)
0.1
0.01
0.1
1
10
VDS - Drain-to-Source Voltage (V)
50
TC = 25ºC
TC = 125ºC
100
10
0.01
0.1
1
TAV - Time in Avalanche (mS)
G001
Figure 10. Safety Operating Area Tc = 25°C
10
G001
Figure 11. Single Pulse Unclamped Inductive Switching
TEXT ADDED FOR SPACING
IDS - Drain- to- Source Current (A)
300.0
Silicon limited
Package limited
250.0
200.0
150.0
100.0
50.0
0.0
−50
−25
0
25
50
75
100 125
TC - Case Temperature (ºC)
150
175
G001
Figure 12. Maximum Drain Current vs. Temperature
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Product Folder Links: CSD17559Q5
5
CSD17559Q5
SLPS374 – NOVEMBER 2012
www.ti.com
MECHANICAL DATA
Q5 Package Dimensions
K
L
L
c1
E1
E2
b
D2
4
4
5
5
e
3
6
3
6
E
D1
7
7
2
2
8
8
1
1
q
Top View
Bottom View
Side View
c
E1
A
q
Front View
M0140-01
DIM
MILLIMETERS
MAX
MIN
MAX
A
0.950
1.050
0.037
0.039
b
0.360
0.460
0.014
0.018
c
0.150
0.250
0.006
0.010
c1
0.150
0.250
0.006
0.010
D1
4.900
5.100
0.193
0.201
D2
4.320
4.520
0.170
0.178
E
4.900
5.100
0.193
0.201
E1
5.900
6.100
0.232
0.240
E2
3.920
4.12
0.154
e
6
INCHES
MIN
1.27 TYP
K
0.760
L
0.510
θ
0.00
0.162
0.050
0.030
0.710
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0.020
0.028
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: CSD17559Q5
CSD17559Q5
www.ti.com
SLPS374 – NOVEMBER 2012
Figure 13. Recommended PCB Pattern
DIM
F1
F7
F3
8
1
F2
F11
F5
F9
5
4
F6
MILLIMETERS
INCHES
MIN
MAX
MIN
MAX
F1
6.205
6.305
0.244
0.248
F2
4.460
4.560
0.176
0.180
F3
4.460
4.560
0.176
0.180
F4
0.650
0.700
0.026
0.028
F5
0.620
0.670
0.024
0.026
F6
0.630
0.680
0.025
0.027
F7
0.700
0.800
0.028
0.031
F8
0.650
0.700
0.026
0.028
F9
0.620
0.670
0.024
0.026
F10
4.900
5.000
0.193
0.197
F11
4.460
4.560
0.176
0.180
F8
F4
F10
M0139-01
K0
4.00 ±0.10 (See Note 1)
0.30 ±0.05
2.00 ±0.05
+0.10
–0.00
12.00 ±0.30
Ø 1.50
1.75 ±0.10
Q5 Tape and Reel Information
5.50 ±0.05
B0
R 0.30 MAX
A0
8.00 ±0.10
Ø 1.50 MIN
A0 = 6.50 ±0.10
B0 = 5.30 ±0.10
K0 = 1.40 ±0.10
R 0.30 TYP
M0138-01
Notes:
1. 10-sprocket hole-pitch cumulative tolerance ±0.2
2. Camber not to exceed 1mm in 100mm, noncumulative over 250mm
3. Material: black static-dissipative polystyrene
4. All dimensions are in mm, unless otherwise specified.
5. Thickness: 0.30 ±0.05mm
6. MSL1 260°C (IR and convection) PbF reflow compatible
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PACKAGE MATERIALS INFORMATION
www.ti.com
19-Dec-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
CSD17559Q5
Package Package Pins
Type Drawing
SON
DQH
8
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
12.8
Pack Materials-Page 1
6.5
B0
(mm)
K0
(mm)
P1
(mm)
5.3
1.4
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Dec-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CSD17559Q5
SON
DQH
8
2500
335.0
335.0
32.0
Pack Materials-Page 2
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