IDT 83021AMI

ICS83021I
1-TO-1 DIFFERENTIAL- TO-LVCMOS/LVTTL TRANSLATOR
General Description
Features
The ICS83021I is a 1-to-1 Differential-to-LVCMOS/
LVTTL Translator and a member of the
HiPerClockS™
HiPerClockS™ family of High Performance Clock
Solutions from IDT. The differential input is highly
flexible and can accept the following input types:
LVPECL, LVDS, LVHSTL, SSTL, and HCSL. The small 8-lead
SOIC footprint makes this device ideal for use in applications with
limited board space.
•
•
•
One LVCMOS/LVTTL output
•
•
•
•
•
•
Output frequency: 350MHz (typical)
ICS
CLK/nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
Part-to-part skew: 500ps (maximum)
Additive phase jitter, RMS: 0.21ps (typical), 3.3V output
Full 3.3V and 2.5V operating supply
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Pin Assignment
Block Diagram
CLK Pulldown
nCLK Pullup
Differential CLK/nCLK input pair
nc
CLK
nCLK
nc
Q0
1
2
3
4
8
7
6
5
VDD
Q0
nc
GND
ICS83021I
8-Lead SOIC, 150Mil
3.9mm x 4.9mm x 1.375mm package body
M Package
Top View
IDT™ / ICS™ LVCMOS/LVTTL TRANSLATOR
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Table 1. Pin Descriptions
Number
Name
1, 4, 6
nc
Type
Unused
Description
No connect.
2
CLK
Input
Pulldown
3
nCLK
Input
Pullup
Non-inverting differential clock input.
5
GND
Power
Power supply ground.
7
Q0
Output
Single-ended clock output. LVCMOS/LVTTL interface levels.
8
VDD
Power
Positive supply pin.
Inverting differential clock input.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
CIN
Input Capacitance
4
pF
RPULLUP
Input Pullup Resistor
51
kΩ
RPULLDOWN
Input Pulldown Resistor
51
kΩ
CPD
Power Dissipation Capacitance
23
pF
ROUT
Output Impedance
IDT™ / ICS™ LVCMOS/LVTTL TRANSLATOR
Test Conditions
Minimum
VDD = 3.6V
5
2
Typical
7
Maximum
12
Units
Ω
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Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
4.6V
Inputs, VI
-0.5V to VDD + 0.5V
Outputs, VO
-0.5V to VDD + 0.5V
Package Thermal Impedance, θJA
103°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
DC Electrical Characteristics
Table 3A. Power Supply DC Characteristics, VDD = 3.3V ± 0.3V or 2.5V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
VDD
Positive Supply Voltage
IDD
Power Supply Current
Minimum
Typical
Maximum
Units
3.0
3.3
3.6
V
2.375
2.5
2.625
V
20
mA
Maximum
Units
Table 3B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 0.3V or 2.5V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
VOH
Output High Voltage; NOTE 1
VOL
Output Low Voltage; NOTE 1
Test Conditions
Minimum
Typical
VDD = 3.6V
2.6
V
VDD = 2.625V
1.8
V
VDD = 3.6V or 2.625V
0.5
V
NOTE 1: Outputs terminated with 50Ω to VDD/2. See Parameter Measurement Information, Output Load Test Circuit Diagrams.
Table 3C. Differential DC Characteristics, VDD = 3.3V ± 0.3V or 2.5V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
IIH
Input High Current
IIL
Input Low Cureent
VPP
Peak-to-Peak Input Voltage
VCMR
Common Mode Input Voltage;
NOTE 1, 2
Minimum
Typical
Maximum
Units
nCLK
VIN = VDD = 3.6V or 2.625V
5
µA
CLK
VIN = VDD = 3.6V or 2.625V
150
µA
nCLK
VIN = 0V, VDD = 3.6V or 2.625V
-150
µA
CLK
VIN = 0V, VDD = 3.6V or 2.625V
-5
µA
0.15
1.3
V
GND + 0.5
VDD – 0.85
V
NOTE 1: For single ended applications, the maximum input voltage for CLK, nCLK is VDD + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
IDT™ / ICS™ LVCMOS/LVTTL TRANSLATOR
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AC Electrical Characteristics
Table 4A. AC Characteristics, VDD = 3.3V ± 0.3V, TA = -40°C to 85°C
Parameter
Symbol
fMAX
Output Frequency
tPD
Propagation Delay, NOTE 1
tsk(pp)
Part-to-Part Skew; NOTE 2, 3
tjit
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
tR / tF
Output Rise/Fall Time
odc
Output Duty Cycle
Test Conditions
Minimum
Typical
Maximum
350
ƒ ≤ 350MHz
1.7
100MHz, Integration Range
(637kHz – 10MHz)
0.8V to 2V
2.0
MHz
2.3
ns
500
ps
0.21
100
Units
ps
250
400
ps
ƒ ≤ 166MHz
45
50
55
%
166MHz < ƒ ≤ 350MHz
40
50
60
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after
thermal equilibrium has been reached under these conditions.
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output at VDD/2.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions.
Using the same type of inputs on each device, the outputs are measured at VDD/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
Table 4B. AC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C
Parameter
Symbol
fMAX
Output Frequency
tPD
Propagation Delay, NOTE 1
tsk(pp)
Part-to-Part Skew; NOTE 2, 3
tjit
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
tR / tF
Output Rise/Fall Time
odc
Output Duty Cycle
Test Conditions
Minimum
ƒ ≤ 350MHz
1.9
Typical
Maximum
350
100MHz, Integration Range
(637kHz – 10MHz)
2.2
MHz
2.5
ns
500
ps
0.21
20% to 80%
250
ƒ ≤ 250MHz
45
250MHz < ƒ ≤ 350MHz
40
Units
ps
550
ps
50
55
%
50
60
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after
thermal equilibrium has been reached under these conditions.
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output at VDD/2.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions.
Using the same type of inputs on each device, the outputs are measured at VDD/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
IDT™ / ICS™ LVCMOS/LVTTL TRANSLATOR
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Additive Phase Jitter
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called
the dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz band
to the power in the fundamental. When the required offset is
specified, the phase noise is called a dBc value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
SSB Phase Noise dBc/Hz
Additive Phase Jitter @ 100MHz
12kHz to 20MHz = 0.21ps (typical)
Offset Frequency (Hz)
device. This is illustrated above. The device meets the noise floor
of what is shown, but can actually be lower. The phase noise is
dependent on the input source and measurement equipment.
As with most timing specifications, phase noise measurements
has issues relating to the limitations of the equipment. Often the
noise floor of the equipment is higher than the noise floor of the
IDT™ / ICS™ LVCMOS/LVTTL TRANSLATOR
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Parameter Measurement Information
1.25V±5%
1.65V±0.15V
SCOPE
VDD
SCOPE
VDD
Qx
Qx
LVCMOS
LVCMOS
GND
GND
-1.25V±5%
-1.65V±0.15V
3.3V Core/3.3V LVCMOS Output Load AC Test Circuit
2.5V Core/2.5V LVCMOS Output Load AC Test Circuit
Part 1
VDD
V
DDO
Qx
2
nCLK
V
Part 2
V
Cross Points
PP
CMR
V
CLK
DDO
Qy
2
tsk(pp)
GND
Differential Input Level
2V
Part-to-Part Skew
2V
0.8V
0.8V
Q0
tR
20%
20%
Q0
tF
3.3V Output Rise/Fall Time
IDT™ / ICS™ LVCMOS/LVTTL TRANSLATOR
80%
80%
tR
tF
2.5V Output Rise/Fall Time
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Parameter Measurement Information, continued
nCLK
V
DD
CLK
2
Q0
t PW
Q0
t
VDD
2
t
PD
odc =
PERIOD
t PW
x 100%
t PERIOD
Propagation Delay
Output Duty Cycle/Pulse Width/Period
Application Information
Wiring the Differential Input to Accept Single Ended Levels
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the
center of the input voltage swing. For example, if the input clock
swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and
R2/R1 = 0.609.
VDD
R1
1K
Single Ended Clock Input
CLK
V_REF
nCLK
C1
0.1u
R2
1K
Figure 1. Single-Ended Signal Driving Differential Input
IDT™ / ICS™ LVCMOS/LVTTL TRANSLATOR
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Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both signals must meet the VPP and
VCMR input requirements. Figures 2A to 2F show interface
examples for the HiPerClockS CLK/nCLK input driven by the most
common driver types. The input interfaces suggested here are
examples only. Please consult with the vendor of the driver
component to confirm the driver termination requirements. For
example, in Figure 2A, the input termination applies for IDT
HiPerClockS open emitter LVHSTL drivers. If you are using an
LVHSTL driver from another vendor, use their termination
recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50Ω
Zo = 50Ω
CLK
CLK
Zo = 50Ω
nCLK
Zo = 50Ω
nCLK
HiPerClockS
Input
LVHSTL
R1
50
IDT
HiPerClockS
LVHSTL Driver
HiPerClockS
Input
LVPECL
R2
50
R1
50
R2
50
R2
50
Figure 2A. HiPerClockS CLK/nCLK Input
Driven by an IDT Open Emitter
HiPerClockS LVHSTL Driver
Figure 2B. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
3.3V
3.3V
3.3V
R3
125
3.3V
R4
125
3.3V
Zo = 50Ω
Zo = 50Ω
CLK
CLK
R1
100
Zo = 50Ω
nCLK
HiPerClockS
Input
LVPECL
R1
84
R2
84
Figure 2C. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
2.5V
nCLK
Zo = 50Ω
Receiver
LVDS
Figure 2D. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVDS Driver
2.5V
3.3V
3.3V
2.5V
*R3
33
R3
120
Zo = 50Ω
R4
120
Zo = 60Ω
CLK
CLK
Zo = 50Ω
Zo = 60Ω
nCLK
nCLK
HCSL
*R4
33
R1
50
R2
50
HiPerClockS
Input
HiPerClockS
SSTL
R1
120
R2
120
*Optional – R3 and R4 can be 0Ω
Figure 2F. HiPerClockS CLK/nCLK Input
Driven by a 2.5V SSTL Driver
Figure 2E. HiPerClockS CLK/nCLK Input
Driven by a 3.3V HCSL Driver
IDT™ / ICS™ LVCMOS/LVTTL TRANSLATOR
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Reliability Information
Table 5. θJA vs. Air Flow Table for an 8 Lead SOIC
θJA by Velocity
Linear Feet per Minute
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
123°C/W
110°C/W
99°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
103°C/W
94°C/W
89°C/W
Transistor Count
The transistor count for ICS83021I is: 416
Pin-to-pin compatible with the MC100EPT21
Package Outline and Package Dimensions
Package Outline - M Suffix for 8 Lead SOIC
Table 6. Package Dimensions
All Dimensions in Millimeters
Symbol
Minimum
Maximum
N
8
A
1.35
1.75
A1
0.10
0.25
B
0.33
0.51
C
0.19
0.25
D
4.80
5.00
E
3.80
4.00
e
1.27 Basic
H
5.80
6.20
h
0.25
0.50
L
0.40
1.27
α
0°
8°
Reference Document: JEDEC Publication 95, MS-012
150
il (N
B d ) SOIC
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Ordering Information
Table 7. Ordering Information
Part/Order Number
83021AMI
83021AMIT
83021AMILF
83021AMILFT
Marking
83021AMI
83021AMI
83021AIL
83021AIL
Package
8 Lead SOIC
8 Lead SOIC
“Lead-Free” 8 Lead SOIC
“Lead-Free” 8 Lead SOIC
Shipping Packaging
Tube
2500 Tape & Reel
Tube
2500 Tape & Reel
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for
the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT
product for use in life support devices or critical medical instruments.
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Revision History Sheet
Rev
Table
Page
B
T2
T3B
T3C
T3D
T4B
2
3
3
3
4
5
B
B
C
T4A
T7
T4A, T4B
T7
C
C
T4A, T4B
Description of Change
Date
6/3/04
6
7
Pin Characteristics table - added 2.5V CPD.
Added 2.5V Power Supply table.
LVCMOS table - added 2.5V VOH.
Differential table - added 2.5V.
Added 2.5V AC Characteristics table.
Added 2.5V Output Load AC Test Circuit Diagram, and 2.5V Output Rise/Fall
Time Diagrams.
Updated Figure 1.
Added Differential Clock Input Interface section.
2
4
Pin Characteristics Table - changed CIN 4pF max. to 4pF typical.
3.3V AC Characteristics Table - changed odc Test Conditions.
6/30/04
1
10
Features Section - added Lead-Free bullet.
Ordering Information Table - Added Lead-Free part number.
3/21/05
1
4
5
11
Features Section - added Additive Phase Jitter bullet.
AC Characteristics Tables - added Additive Phase Jitter row.
Added Additive Phase Jitter Plot.
Added Lead-Free Note.
12/12/05
1
8
9
Pin Assignment - corrected package body measurements.
Updated Differential Clock Input Interface.
Updated Reliability Information.
Updated datasheet format .
6/18/08
1
4
Corrected typo in Header from 1-to-2... to 1-to-1....
AC Tables - added Temperature NOTE.
10/31/08
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Contact Information:
www.IDT.com
www.IDT.com
Sales
Technical Support
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
Fax: 408-284-2775
www.IDT.com/go/contactIDT
[email protected]
+480-763-2056
Corporate Headquarters
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
United States
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
© 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered
trademarks used to identify products or services of their respective owners.
Printed in USA