SiHH11N60E www.vishay.com Vishay Siliconix E Series Power MOSFET FEATURES PRODUCT SUMMARY VDS (V) at TJ max. • Fully lead (Pb)-free device 650 RDS(on) typ. (Ω) at 25 °C VGS = 10 V • Low figure-of-merit (FOM) Ron x Qg 0.295 Qg max. (nC) 62 • Low input capacitance (Ciss) Qgs (nC) 7 • Reduced switching and conduction losses 13 • Ultra low gate charge (Qg) Qgd (nC) Configuration Single • Avalanche energy rated (UIS) • Kelvin connection for reduced gate noise PowerPAK® 8 x 8 • Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 4 D APPLICATIONS 1 • Server and telecom power supplies 2 3 • Switch mode power supplies (SMPS) 3 Pin 4 • Power factor correction power supplies (PFC) G • Lighting Pin 1 - High-intensity discharge (HID) - Fluorescent ballast lighting • Industrial S N-Channel MOSFET - Welding - Induction heating - Motor drives - Battery chargers - Renewable energy - Solar (PV inverters) Pin 2 Pin 3 ORDERING INFORMATION Package PowerPAK 8 x 8 Lead (Pb)-free and Halogen-free SiHH11N60E-T1-GE3 ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted) PARAMETER SYMBOL LIMIT Drain-Source Voltage VDS 600 Gate-Source Voltage VGS ± 30 Continuous Drain Current (TJ = 150 °C) VGS at 10 V TC = 25 °C TC = 100 °C Pulsed Drain Current a ID UNIT V 11 7 A IDM 27 0.9 W/°C Single Pulse Avalanche Energy b EAS 127 mJ Maximum Power Dissipation PD 114 W TJ, Tstg -55 to +150 °C Linear Derating Factor Operating Junction and Storage Temperature Range Drain-Source Voltage Slope TJ = 125 °C Reverse Diode dV/dt c dV/dt 70 18 V/ns Notes a. Repetitive rating; pulse width limited by maximum junction temperature. b. VDD = 140 V, starting TJ = 25 °C, L = 28.2 mH, Rg = 25 Ω, IAS = 3 A. c. ISD ≤ ID, dI/dt = 100 A/μs, starting TJ = 25 °C. S15-2031-Rev. A, 24-Aug-15 Document Number: 91651 1 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHH11N60E www.vishay.com Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYP. MAX. Maximum Junction-to-Ambient RthJA 42 55 Maximum Junction-to-Case (Drain) RthJC 0.76 1.10 UNIT °C/W SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static Drain-Source Breakdown Voltage VDS Temperature Coefficient Gate-Source Threshold Voltage (N) VDS VGS = 0 V, ID = 250 μA 600 - - V ΔVDS/TJ Reference to 25 °C, ID = 1 mA - 0.66 - V/°C VGS(th) VDS = VGS, ID = 250 μA 2.0 - 4.0 V VGS = ± 20 V - - ± 100 nA VGS = ± 30 V - - ±1 μA VDS = 600 V, VGS = 0 V - - 1 VDS = 480 V, VGS = 0 V, TJ = 125 °C - - 50 Gate-Source Leakage IGSS Zero Gate Voltage Drain Current IDSS μA - 0.295 0.339 Ω gfs VDS = 30 V, ID = 5.5 A - 3.7 - S Input Capacitance Ciss 1076 - Coss - 56 - Reverse Transfer Capacitance Crss VGS = 0 V, VDS = 100 V, f = 1 MHz - Output Capacitance - 6 - Effective Output Capacitance, Energy Related a Co(er) - 52 - Effective Output Capacitance, Time Related b Co(tr) - 174 - - 31 62 - 7 - Drain-Source On-State Resistance Forward Transconductance RDS(on) VGS = 10 V ID = 5.5 A Dynamic pF VDS = 0 V to 480 V, VGS = 0 V Total Gate Charge Qg Gate-Source Charge Qgs VGS = 10 V ID = 5.5 A, VDS = 480 V Gate-Drain Charge Qgd - 13 - Turn-On Delay Time td(on) - 16 32 Rise Time Turn-Off Delay Time tr td(off) Fall Time tf Gate Input Resistance Rg VDD = 480 V, ID = 5.5 A, VGS = 10 V, Rg = 9.1 Ω - 21 42 - 39 68 - 21 42 f = 1 MHz, open drain 0.2 0.7 1.5 - - 11 - - 27 nC ns Ω Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current IS Pulsed Diode Forward Current ISM Diode Forward Voltage VSD Reverse Recovery Time trr Reverse Recovery Charge Qrr Reverse Recovery Current IRRM MOSFET symbol showing the integral reverse p - n junction diode D A G TJ = 25 °C, IS = 5.5 A, VGS = 0 V TJ = 25 °C, IF = IS = 5.5 A, dI/dt = 100 A/μs, VR = 25 V S - 0.9 1.2 V - 280 560 ns - 3.0 6.0 μC - 20 - A Notes a. Coss(er) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 % to 80 % VDS. b. Coss(tr) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 % to 80 % VDS. S15-2031-Rev. A, 24-Aug-15 Document Number: 91651 2 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHH11N60E www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 3.0 30 15 V 14 V 13 V 12 V 11 V 10 V 9V 8V 7V 6V BOTTOM 5 V 20 ID = 5.5 A TJ = 25 °C RDS(on), Drain-to-Source On-Resistance (Normalized) 10 2.0 1.5 1.0 VGS = 10 V 0.5 0 0 0 5 10 15 20 25 VDS, Drain-to-Source Voltage (V) -60 -40 -20 30 20 10 000 TOP 15 V 14 V 13 V 12 V 11 V 10 V 9V 8V 7V 6V BOTTOM 5 V TJ = 150 °C Ciss 1000 C, Capacitance (pF) 15 0 20 40 60 80 100 120 140 160 TJ, Junction Temperature (°C) Fig. 4 - Normalized On-Resistance vs. Temperature Fig. 1 - Typical Output Characteristics ID, Drain-to-Source Current (A) 2.5 10 100 Coss Crss 10 5 VGS = 0 V, f = 1 MHz Ciss = Cgs + Cgd, Cds shorted Crss = Cgd Coss = Cds + Cgd 1 0 0 5 10 15 20 25 VDS, Drain-to-Source Voltage (V) 0 30 100 200 300 400 500 VDS, Drain-to-Source Voltage (V) 600 Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 2 - Typical Output Characteristics 30 10 000 8 7 6 20 1000 5 Coss (pF) ID, Drain-to-Source Current (A) TJ = 25 °C TJ = 150 °C 10 Coss Eoss 4 Eoss (μJ) ID, Drain-to-Source Current (A) TOP 3 100 2 1 VDS = 30 V 0 10 0 5 10 15 20 VGS, Gate-to-Source Voltage (V) Fig. 3 - Typical Transfer Characteristics S15-2031-Rev. A, 24-Aug-15 25 0 0 100 200 300 VDS 400 500 600 Fig. 6 - COSS and EOSS vs. VDS Document Number: 91651 3 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHH11N60E www.vishay.com Vishay Siliconix 12 VDS = 480 V VDS = 300 V VDS = 120 V 20 9 ID, Drain Current (A) VGS, Gate-to-Source Voltage (V) 24 16 12 8 6 3 4 0 0 0 15 30 45 Qg, Total Gate Charge (nC) 60 Fig. 7 - Typical Gate Charge vs. Gate-to-Source Voltage 25 50 75 100 125 TC, Case Temperature (°C) 150 Fig. 10 - Maximum Drain Current vs. Case Temperature 10 VDS, Drain-to-Source Breakdown Voltage (V) ISD, Reverse Drain Current (A) 750 TJ = 150 °C TJ = 25 °C 1 VGS = 0 V 0.1 0.2 0.4 0.6 0.8 1.0 1.2 VSD, Source-Drain Voltage (V) 1.4 Fig. 8 - Typical Source-Drain Diode Forward Voltage ID, Drain Current (A) 100 Operation in this Area Limited by RDS(on) 725 700 675 650 625 600 ID = 250 μA 575 -60 -40 -20 0 20 40 60 80 100 120 140 160 TJ, Junction Temperature (°C) Fig. 11 - Temperature vs. Drain-to-Source Voltage IDM Limited 10 100 μs Limited by RDS(on)* 1 1 ms 0.1 10 ms TC = 25 °C TJ = 150 °C Single Pulse BVDSS Limited 0.01 1 10 100 1000 VDS, Drain-to-Source Voltage (V) * VGS > minimum VGS at which RDS(on) is specified Fig. 9 - Maximum Safe Operating Area S15-2031-Rev. A, 24-Aug-15 Document Number: 91651 4 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHH11N60E www.vishay.com Vishay Siliconix 1 Normalized Effective Transient Thermal Impedance Duty Cycle = 0.5 0.2 0.1 0.1 0.05 0.02 Single Pulse 0.01 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 Pulse Time (s) Fig. 12 - Normalized Thermal Transient Impedance, Junction-to-Case 1 Normalized Effective Transient Thermal Impedance Duty Cycle = 0.5 0.2 0.1 0.1 0.05 0.02 0.01 Single Pulse 0.001 0.0001 0.001 0.01 0.1 1 10 100 1000 Pulse Time (s) Fig. 13 - Normalized Thermal Transient Impedance, Junction-to-Ambient VDS VGS L RD Vary tp to obtain required IAS VDS D.U.T. RG D.U.T RG + - VDD + - IAS 10 V V DD 10 V Pulse width ≤ 1 µs Duty factor ≤ 0.1 % 0.01 Ω tp Fig. 14 - Switching Time Test Circuit Fig. 16 - Unclamped Inductive Test Circuit VDS VDS tp 90 % VDD VDS 10 % VGS td(on) tr td(off) tf Fig. 15 - Switching Time Waveforms S15-2031-Rev. A, 24-Aug-15 IAS Fig. 17 - Unclamped Inductive Waveforms Document Number: 91651 5 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHH11N60E www.vishay.com Vishay Siliconix Current regulator Same type as D.U.T. QG 10 V 50 kΩ QGS QGD 12 V 0.2 µF 0.3 µF + VG D.U.T. - VDS VGS Charge Fig. 18 - Basic Gate Charge Waveform 3 mA IG ID Current sampling resistors Fig. 19 - Gate Charge Test Circuit Peak Diode Recovery dV/dt Test Circuit + D.U.T. Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + - - Rg • • • • + dV/dt controlled by Rg Driver same type as D.U.T. ISD controlled by duty factor “D” D.U.T. - device under test + - VDD Driver gate drive Period P.W. D= P.W. Period VGS = 10 Va D.U.T. lSD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt Re-applied voltage Inductor current VDD Body diode forward drop Ripple ≤ 5 % ISD Note a. VGS = 5 V for logic level devices Fig. 20 - For N-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91651. S15-2031-Rev. A, 24-Aug-15 Document Number: 91651 6 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information www.vishay.com Vishay Siliconix PowerPAK® 8 x 8 Case Outline D2 D3 2x E3 0.1 C A D A 2x 0.1 C B K E E2 PPAK 8x8 (8 mm x 8 mm) L B e Pin 1 dot 5, 6 by marking TOP SIDE VIEW b 0.08 C A1 DIM. A2 A BACK SIDE VIEW MILLIMETERS INCHES MIN. NOM. MAX. MIN. NOM. 8 0.95 1.00 1.05 0.037 0.039 0.041 A1 0.00 - 0.05 0.000 - 0.002 1.05 0.037 A A2 b4 020 ref. 0.95 1.00 MAX. 0.008 ref. 0.039 0.041 D 7.90 8.00 8.10 0.311 0.315 0.319 D2 7.10 7.20 7.30 0.280 0.283 0.287 D3 0.40 BSC 0.016 BSC e 2.00 BSC 0.079 BSC E 7.90 8.00 8.10 0.311 0.315 0.319 E2 4.30 4.35 4.40 0.169 0.171 0.173 E3 0.40 BSC 0.016 BSC K 2.75 BSC 0.108 BSC L 0.45 N3 0.50 0.55 8 0.018 0.020 0.022 8 Notes 1. Use millimeters as the primary measurement. 2. Dimensioning and tolerances conform to ASME Y14.5 M - 1994. 3. N is the number of terminals. 4. Package warpage max. 0.08 mm. 5. The pin 1 identifier must be existed on the top surface of the package by using indentation mark or other feature of package body. 6. Exact shape and size of this feature is optional. ECN: T15-0225-Rev. A, 18-May-15 DWG: 6041 Revision: 18-May-15 1 Document Number: 67859 THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. 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We confirm that all the products identified as being compliant to IEC 61249-2-21 conform to JEDEC JS709A standards. Revision: 02-Oct-12 1 Document Number: 91000