Databook.fxp 1/13/99 2:09 PM Page B-52 B-52 01/99 J174, J175 P-Channel Silicon Junction Field-Effect Transistor Absolute maximum ratings at TA = 25¡C ¥ Choppers ¥ Commutators ¥ Analog Switches Reverse Gate Source & Reverse Gate Drain Voltage Continuous Forward Gate Current Continuous Device Power Dissipation Power Derating At 25°C free air temperature: J174 Static Electrical Characteristics Min Gate Source Breakdown Voltage V(BR)GSS Gate Reverse Current IGSS Gate Source Cutoff Voltage VGS(OFF) Drain Saturation Current (Pulsed) IDSS Drain Cutoff Current ID(OFF) Dynamic Electrical Characteristics Drain Source ON Resistance rds(on) Dynamic Electrical Characteristics J175 Max 30 Min – 30 V 50 mA 360 mW 3.27 mW/°C Process PJ99 Max 30 Unit Test Conditions V IG = 1 µA, VDS = ØV 1 nA VGS = 20V, VDS = ØV 6 V VDS = – 15V, ID = – 10 nA – 20 – 125 – 7 – 70 mA VDS = – 15V, VGS = ØV –1 –1 nA VDS = – 15V, VGS = 10V Ω VGS = Ø, VDS < = 0.1V f = 1 kHz 1 5 10 3 Max Max 85 85 Typ Typ Drain Gate Capacitance Cgd 5.5 5.5 pF VDS = ØV, VGS = 10V f = 1 MHz Source Gate Capacitance Cgs 5.5 5.5 pF VDS = ØV, VGS = 10V f = 1 MHz Drain Gate + Source Gate Capacitance Cgd + Cgs 32 32 pF VDS = VGS = ØV f = 1 MHz td(on) 2 5 ns Rise Time tr 5 10 ns Turn OFF Delay Time td(off) 5 10 ns Fall Time tf 10 20 ns Switching Characteristics Turn ON Delay Time VDD VGS(OFF) RL VGS(ON) J174 J175 – 10 12 560 Ø –6 8 1.2 k Ø TOÐ226AA Package Surface Mount Dimensions in Inches (mm) SMPJ174, SMPJ175 V V Ω V Pin Configuration 1 Drain, 2 Gate, 3 Source 1000 N. Shiloh Road, Garland, TX 75042 (972) 487-1287 FAX (972) 276-3375 www.interfet.com