IS62WV10248EALL/BLL IS65WV10248EALL/BLL 1Mx8 LOW

IS62WV10248EALL/BLL
IS65WV10248EALL/BLL
NOVEMBER 2014
1Mx8 LOW VOLTAGE,
ULTRA LOW POWER CMOS STATIC RAM
KEY FEATURES







High-speed access time: 45ns, 55ns
CMOS low power operation
– 36 mW (typical) operating
– 12 µW (typical) CMOS standby
TTL compatible interface levels
Single power supply
–1.65V-2.2V VDD (62/65WV10248EALL)
– 2.2V-3.6V VDD (62/65WV10248EBLL)
Data control for upper and lower bytes
o
o
Automotive temperature (-40 C to +125 C)
Lead-free available
DESCRIPTION
The ISSI IS62WV10248EALL/ IS62WV10248EBLL are
high-speed, 8M bit static RAMs organized as 1M words
by 8 bits. It is fabricated using ISSI's high-performance
CMOS technology. This highly reliable process
coupled with innovative circuit design techniques,
yields high-performance and low power consumption
devices.
When
is HIGH (deselected) or when CS2 is low
(deselected), the device assumes a standby mode at
which the power dissipation can be reduced down with
CMOS input levels.
Easy memory expansion is provided by using Chip
Enable and Output Enable inputs. The active LOW
Write Enable (
) controls both writing and reading of
the memory.
The IS62WV10248EALL and IS62WV10248EBLL are
packaged in the JEDEC standard 48-pin mini BGA
(6mm x 8mm) and 44-Pin TSOP (TYPE II).
BLOCK DIAGRAM
Copyright © 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such
applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc.- www.issi.com
Rev. B
10/21/2014
1
IS62WV10248EALL/BLL
IS65WV10248EALL/BLL
PIN CONFIGURATIONS (1Mx8)
48-pin mini BGA (B) (6mm x 8mm)
44-Pin TSOP (Type II)
PIN DESCRIPTIONS
A0-A19
Address Inputs
Chip Enable 1 Input
CS2
Chip Enable 2 Input
Output Enable Input
Write Enable Input
I/O0-I/O7
NC
VDD
Vss
Input/Output
No Connection
Power
Ground
Integrated Silicon Solution, Inc.- www.issi.com
Rev. B
10/21/2014
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IS62WV10248EALL/BLL
IS65WV10248EALL/BLL
FUNCTION DESCRIPTION
SRAM is one of random access memories. Each byte has an address and can be accessed randomly. SRAM has three
different modes supported. Each function is described below with Truth Table.
STANDBY MODE
Device enters standby mode when deselected (
HIGH or CS2 LOW). The input and output pins (I/O0-7) are placed
in a high impedance state. The current consumption in this mode will be either ISB1 or ISB2 depending on the input
level. CMOS input in this mode will maximize saving power.
WRITE MODE
Write operation issues with Chip selected (
LOW and CS2 HIGH) and Write Enable (
) input LOW. The input and
output pins(I/O0-7) are in data input mode. Output buffers are closed during this time even if
is LOW.
READ MODE
Read operation issues with Chip selected (
LOW and CS2 HIGH) and Write Enable (
) input HIGH. When
LOW, output buffer turns on to make data output. Any input to I/O pins during READ mode is not permitted.
is
In the READ mode, output buffers can be turned off by pulling
HIGH. In this mode, internal device operates as
READ but I/Os are in a high impedance state. Since device is in READ mode, active current is used.
TRUTH TABLE
Mode
I/O Operation
VDD Current
Not Selected
X
H
CS2
X
X
High-Z
ISB1, ISB2
(Power-down)
X
X
L
X
High-Z
ISB1, ISB2
Output Disabled
H
L
H
H
High-Z
Icc
Read
H
L
H
L
Dout
Icc
Write
L
L
H
X
Din
Icc
Integrated Silicon Solution, Inc.- www.issi.com
Rev. B
10/21/2014
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IS62WV10248EALL/BLL
IS65WV10248EALL/BLL
ABSOLUTE MAXIMUM RATINGS AND OPERATING RANGE
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Vt er m
tBIAS
Parameter
Terminal Voltage with Respect to GND
Temperature Under Bias
Value
–0.2 to +3.9(VDD+0.3V)
–55 to +125
VDD
V DD Related to GND
–0.2 to +3.9(VDD+0.3V)
tStg
Storage Temperature
–65 to +150
IOUT
DC Output Current (LOW)
20
Unit
V
C
V
C
mA
Notes:
Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
OPERATING RANGE(1)
Range
Device Marking
Ambient Temperature
VDD(min)
VDD(typ)
VDD(max)
Commercial
IS62WV10248EALL
Industrial
IS62WV10248EALL
0C to +70C
1.65V
1.8V
2.2V
-40C to +85C
1.65V
1.8V
2.2V
Automotive
IS65WV10248EALL
-40C to +125C
1.65V
1.8V
2.2V
Commercial
IS62WV10248EBLL
0C to +70C
2.2V
3.3V
3.6V
Industrial
IS62WV10248EBLL
-40C to +85C
2.2V
3.3V
3.6V
Automotive
IS65WV10248EBLL
-40C to +125C
2.2V
3.3V
3.6V
Note:
1.
Full device AC operation assumes a 100 µs ramp time from 0 to Vcc(min) and 200 µs wait time after Vcc stabilization.
PIN CAPACITANCE (1)
Parameter
Symbol
Input capacitance
DQ capacitance (IO0–IO7)
CIN
CI/O
Test Condition
TA = 25°C, f = 1 MHz, VDD = VDD(typ)
Max
Units
10
10
pF
pF
Note:
1. These parameters are guaranteed by design and tested by a sample basis only.
THERMAL CHARACTERISTICS (1)
Parameter
Thermal resistance from junction to ambient (airflow = 1m/s)
Thermal resistance from junction to case
Symbol
RθJA
RθJC
Rating
43.22
13.35
Units
°C/W
°C/W
Note:
1. These parameters are guaranteed by design and tested by a sample basis only.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. B
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IS62WV10248EALL/BLL
IS65WV10248EALL/BLL
ELECTRICAL CHARACTERISTICS
IS62(5)WV10248EALL DC ELECTRICAL CHARACTERISTICS-I (OVER THE OPERATING RANGE)
Symbol
VOH
VOL
(1)
VIH
(1)
VIL
ILI
ILO
Parameter
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage
Output Leakage
Test Conditions
I OH = -0.1 mA
IOL = 0.1 mA
GND < VIN < VDD
GND < VIN < VDD, Output Disabled
Min.
1.4
—
1.4
–0.2
–1
–1
Max.
—
0.2
VDD + 0.2
0.4
1
1
Unit
V
V
V
V
µA
µA
Notes:
1. VILL(min) = -1.0V AC (pulse width < 10ns). Not 100% tested.
VIHH (max) = VDD + 1.0V AC (pulse width < 10ns). Not 100% tested.
IS62(5)WV10248EBLL DC ELECTRICAL CHARACTERISTICS-I (OVER THE OPERATING RANGE)
Symbol
VOH
Parameter
Output HIGH Voltage
VOL
Output LOW Voltage
(1)
Input HIGH Voltage
(1)
Input LOW Voltage
VIH
VIL
ILI
ILO
Input Leakage
Output Leakage
Test Conditions
2.2 ≤ V DD < 2.7, I OH = -0.1 mA
2.7 ≤ V DD ≤ 3.6, I OH = -1.0 mA
2.2 ≤ V DD < 2.7, IOL = 0.1 mA
2.7 ≤ V DD ≤ 3.6, IOL = 2.1 mA
2.2 ≤ V DD < 2.7
2.7 ≤ V DD ≤ 3.6
2.2 ≤ V DD < 2.7
2.7 ≤ V DD ≤ 3.6
GND < VIN < VDD
GND < VIN < VDD, Output Disabled
Min.
2.0
2.4
—
—
1.8
2.2
–0.3
–0.3
–1
–1
Max.
—
—
0.4
0.4
VDD + 0.3
VDD + 0.3
0.6
0.8
1
1
Unit
V
V
V
V
V
V
V
V
µA
µA
Notes:
1. VILL(min) = -2.0V AC (pulse width < 10ns). Not 100% tested.
VIHH (max) = VDD + 2.0V AC (pulse width < 10ns). Not 100% tested.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. B
10/21/2014
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IS62WV10248EALL/BLL
IS65WV10248EALL/BLL
IS62(5)WV10248EALL DC ELECTRICAL CHARACTERISTICS-II FOR POWER
(OVER THE OPERATING RANGE)
Symbol
ICC
ICC1
ISB1
Parameter
VDD Dynamic
Operating
Supply Current
VDD Static
Operating
Supply Current
CMOS Standby
Current (CMOS
Inputs)
Test Conditions
VDD=VDD(max), IOUT=0mA, f=fMAX
VDD=VDD(max), IOUT = 0mA, f=0Hz
VDD=VDD(max),
(1) 0V ≤ CS2 ≤ 0.2V
or
(2)
≥ VDD - 0.2V, CS2 ≥ VDD - 0.2V
Grade
Com.
Ind.
Auto.
Com.
Ind.
Auto.
Com.
Typ.
-
Max.
12
15
15
6
6
6
20
Unit
mA
Ind.
-
25
µA
Auto.
-
50
µA
mA
µA
Note:
Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VDD = VDD(typ), TA = 25C
IS62(5)WV10248EBLL DC ELECTRICAL CHARACTERISTICS-II FOR POWER
(OVER THE OPERATING RANGE)
Symbol
ICC
ICC1
ISB1
Parameter
VDD Dynamic
Operating
Supply Current
VDD Static
Operating
Supply Current
CMOS Standby
Current (CMOS
Inputs)
Test Conditions
VDD=VDD(max), IOUT=0mA, f=fMAX
VDD=VDD(max), IOUT = 0mA, f=0Hz
VDD=VDD(max),
(1) 0V ≤ CS2 ≤ 0.2V
or
(2)
≥ VDD - 0.2V, CS2 ≥ VDD - 0.2V
Grade
Com.
Ind.
Auto.
Com.
Ind.
Auto.
Com.
Typ.
-
Max.
15
15
15
6
6
6
20
Unit
mA
Ind.
-
25
µA
Auto.
-
50
µA
mA
µA
Note:
Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VDD = VDD(typ), TA = 25℃
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Rev. B
10/21/2014
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IS62WV10248EALL/BLL
IS65WV10248EALL/BLL
AC TEST CONDITIONS (OVER THE OPERATING RANGE)
Parameter
Input Rise Time
Input Fall Time
Output Timing Reference Level
Output Load Conditions
Symbol
Conditions
Units
TR
TF
VREF
1.0
1.0
½ VTM
V/ns
V/ns
V
Refer to Figure 1 and 2
OUTPUT LOAD CONDITIONS FIGURES
Figure1
Figure2
R1
R1
VTM
VTM
OUTPUT
OUTPUT
30pF,
including
jig and
scope
Parameters
R1
R2
VTM
R2
VDD=1.65~1.98V
13500Ω
10800Ω
VDD
Integrated Silicon Solution, Inc.- www.issi.com
Rev. B
10/21/2014
5pF,
including
jig and
scope
VDD=2.2~2.7V
16667Ω
15385Ω
VDD
R2
VDD=2.7~3.6V
1103Ω
1554Ω
VDD
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IS62WV10248EALL/BLL
IS65WV10248EALL/BLL
AC CHARACTERISTICS(6) (OVER OPERATING RANGE)
READ CYCLE AC CHARACTERISTICS
Parameter
Symbol
Read Cycle Time
Address Access Time
Output Hold Time
45ns
55ns
unit
notes
-
ns
1,5
8
5
55
55
25
18
-
ns
ns
ns
ns
ns
ns
1
1
1
1
2
2
10
18
-
ns
ns
2
2
unit
notes
Min
Max
Min
Max
tRC
45
-
55
, CS2 Access Time
Access Time
to High-Z Output
to Low-Z Output
tAA
tOHA
tACS1/tACS2
tDOE
tHZOE
tLZOE
8
5
45
45
22
18
-
, CS2 to High-Z Output
, CS2 to Low-Z Output
tHZCS/tHZCS2
tLZCS/tLZCS2
10
18
-
WRITE CYCLE AC CHARACTERISTICS
Parameter
Symbol
Write Cycle Time
,CS2 to Write End
Address Setup Time to Write End
Address Hold from Write End
Address Setup Time
Pulse Width
Data Setup to Write End
Data Hold from Write End
LOW to High-Z Output
HIGH to Low-Z Output
45ns
55ns
Min
Max
Min
Max
tWC
tSCS1/tSCS2
tAW
45
35
35
-
55
40
40
-
ns
ns
ns
1,3,5
1,3
1,3
tHA
tSA
tPWE
tSD
tHD
tHZWE
0
0
35
28
0
-
18
0
0
40
28
0
-
18
ns
ns
ns
ns
ns
ns
1,3
1,3
1,3,4
1,3
1,3
2,3
tLZWE
10
-
10
-
ns
2,3
Notes:
1. Tested with the load in Figure 1.
2. Tested with the load in Figure 2. tHZOE, tHZCS and tHZWE transitions are measured when the output enters a high impedance state. Not
100% tested.
3. The internal write time is defined by the overlap of
=LOW, CS2=HIGH and
=LOW. All four conditions must be in valid states to initiate a
Write, but any condition can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge
of the signal that terminates the write.
4. tPWE > tHZWE + tSD when OE is LOW.
5. Address inputs must meet VIH and VIL SPEC during this period. Any glitch or unknown inputs are not permitted. Unknown input with standby
mode is acceptable.
6. Data retention characteristics are defined later in DATA RETENTION CHARACTERISTICS.
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Rev. B
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IS62WV10248EALL/BLL
IS65WV10248EALL/BLL
TIMING DIAGRAM
READ CYCLE NO. 1(1,2) (ADDRESS CONTROLLED) (
=
=VIL, CS2=
=VIH)
tRC
ADDRESS
tAA
tOHA
tOHA
I/O0-15
PREVIOUS DATA VALID
READ CYCLE NO. 2(1,3) (
, CS2, AND
Notes:
1.
is HIGH for a Read Cycle.
2. The device is continuously selected.
,
3. Address is valid prior to or coincident with
Low-Z
DATA VALID
Low-Z
CONTROLLED)
= Vil. CS2=
=VIH.
LOW and CS2 HIGH transition.
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Rev. B
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IS62WV10248EALL/BLL
IS65WV10248EALL/BLL
WRITE CYCLE NO. 1 (
CONTROLLED,
= HIGH OR LOW)
Notes:
1. tHZWE is based on the assumption when tSA=0nS after READ operation. Actual DOUT for tHZWE may not appear if
Write Cycle. tHZOE is the time DOUT goes to High-Z after
goes high.
2. During this period the I/Os are in output state. Do not apply input signals.
WRITE CYCLE NO. 2 (
Controlled:
is HIGH During Write Cycle)
Notes:
1. tHZWE is based on the assumption when tSA=0nS after READ operation. Actual DOUT for tHZWE may not appear if
Write Cycle. tHZOE is the time DOUT goes to High-Z after goes high.
2. During this period the I/Os are in output state. Do not apply input signals
Integrated Silicon Solution, Inc.- www.issi.com
Rev. B
10/21/2014
goes high before
goes high before
10
IS62WV10248EALL/BLL
IS65WV10248EALL/BLL
WRITE CYCLE NO. 3 (
CONTROLLED:
IS LOW DURING WRITE CYCLE)
Notes:
If
is low during write cycle, tHZWE must be met in the application. Do not apply input signal during this period. Data output from the previous
READ operation will drive IO BUS.
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Rev. B
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IS62WV10248EALL/BLL
IS65WV10248EALL/BLL
DATA RETENTION CHARACTERISTICS
Symbol
Parameter
Test Condition
OPTION
VDR
VDD for Data
Retention
See Data Retention Waveform
IS62(5)WV10248EALL
IS62(5)WV10248EBLL
Data Retention
Current
VDD= VDR(min),
(1) 0V ≤ CS2 ≤ 0.2V, or
(2)
≥ VDD – 0.2V,
CS2 ≥ VDD - 0.2V
See Data Retention Waveform
IDR
tSDR
Data Retention
Setup Time
tRDR
Recovery Time
Min.
Typ.
(1)
Max.
Unit
1.5
-
V
1.5
-
V
uA
Com.
-
-
20
Ind.
-
-
25
Auto
-
-
50
0
-
-
ns
tRC
-
-
ns
See Data Retention Waveform
Note:
1. Typical values are measured at VDD=VDR(min), TA = 25℃ and not 100% tested.
DATA RETENTION WAVEFORM (
CONTROLLED)
tSDR
DATA RETENTION MODE
tRDR
VDD
VDR
> VDD-0.2V
GND
DATA RETENTION WAVEFORM (CS2 CONTROLLED)
DATA RETENTION MODE
VDD
CS2
tSDR
tRDR
VDR
CS2 < 0.2V
GND
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IS62WV10248EALL/BLL
IS65WV10248EALL/BLL
ORDERING INFORMATION
IS62WV10248EALL (1.65V - 2.2V)
Industrial Range: –40°C to +85°C
Speed (ns)
55
Order Part No.
Package
IS62WV10248EALL-55TI
TSOP-II
IS62WV10248EALL-55TLI
TSOP-II, Lead-free
IS62WV10248EALL-55BI
mini BGA
IS62WV10248EALL-55BLI
mini BGA, Lead-free
IS62WV10248EBLL (2.2V - 3.6V)
Industrial Range: –40°C to +85°C
Speed (ns)
45
55
Order Part No.
Package
IS62WV10248EBLL-45TI
TSOP-II
IS62WV10248EBLL-45TLI
TSOP-II, Lead-free
IS62WV10248EBLL-45BI
mini BGA
IS62WV10248EBLL-45BLI
mini BGA, Lead-free
IS62WV10248EBLL-55TI
TSOP-II
IS62WV10248EBLL-55TLI
TSOP-II, Lead-free
IS62WV10248EBLL-55BI
mini BGA
IS62WV10248EBLL-55BLI
mini BGA, Lead-free
IS65WV10248EBLL (2.2V - 3.6V)
Automotive Range: –40°C to +125°C
Speed (ns)
45
Order Part No.
Package
IS65WV10248EBLL-45CTLA3
TSOP-II, Lead-free,
Copper Lead-frame
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IS62WV10248EALL/BLL
IS65WV10248EALL/BLL
PACKAGE INFORMATION
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Rev. B
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IS62WV10248EALL/BLL
IS65WV10248EALL/BLL
PACKAGE INFORMATION
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Rev. B
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