IS62WV25616EALL/EBLL/ECLL IS65WV25616EBLL/ECLL

IS62WV25616EALL/EBLL/ECLL
IS65WV25616EBLL/ECLL
256Kx16 LOW VOLTAGE,
ULTRA LOW POWER CMOS STATIC RAM
KEY FEATURES
 High-speed access time: 35ns, 45ns, 55ns

CMOS low power operation
– 30 mW (typical) operating
– 6 µW (typical) CMOS standby

TTL compatible interface levels

Single power supply
–1.65V-2.2V VDD (IS62/65WV25616EALL)
– 2.2V-3.6V VDD (IS62/65WV25616EBLL)
– 3.3V +/-5% VDD (IS62/65WV25616ECLL)

Package : 44-pin TSOP (Type II)
48-pin mini BGA

Commercial, Industrial and Automotive
temperature support

PRELIMINARY
AUGUST 2015
DESCRIPTION
The ISSI IS62/65WV25616EALL/EBLL/ECLL are highspeed, low power, 4M bit static RAMs organized as 256K
words by 16 bits. It is fabricated using ISSI's highperformance CMOS technology.
This highly reliable process coupled with innovative circuit
design techniques, yields high-performance and low power
consumption devices. When CS1# is HIGH (deselected) or
when CS2 is LOW (deselected) or when CS1# is LOW,
CS2 is HIGH and both LB# and UB# are HIGH, the device
assumes a standby mode at which the power dissipation
can be reduced down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs. The active LOW Write Enable
(WE#) controls both writing and reading of the memory. A
data byte allows Upper Byte (UB#) and Lower Byte (LB#)
access.
The IS62/65WV25616EALL/EBLL/ECLL are packaged in the
JEDEC standard 48-pin mini BGA (6mm x 8mm) and 44-Pin
TSOP (TYPE II).
Lead-free available
FUNCTIONAL BLOCK DIAGRAM
DECODER
A0 – A17
256K x 16
MEMORY
ARRAY
VDD
GND
I/O0 – I/O7
Lower Byte
I/O8 – I/O15
Upper Byte
CS2
CS1#
OE#
WE#
UB#
LB#
I/O
DATA
CIRCUIT
COLUMN I/O
CONTROL
CIRCUIT
Copyright © 2015 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such
applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc.- www.issi.com
Rev. 0B
08/04/2015
1
IS62WV25616EALL/EBLL/ECLL
IS65WV25616EBLL/ECLL
PIN CONFIGURATIONS
48-Pin mini BGA (6mm x 8mm)
48-Pin mini BGA (6mm x 8mm)
2 CS Option
1
2
3
4
5
6
LB#
OE#
A0
A1
A2
NC
B
I/O8
UB#
A3
A4
CS1#
I/O0
C
I/O9
I/O10
A5
A6
I/O1
D
GND
I/O11
A17
A7
D
VDD
I/O12
NC
F
I/O14
I/O13
G
I/O15
H
NC
A
1
2
3
4
5
6
LB#
OE#
A0
A1
A2
CS2
B
I/O8
UB#
A3
A4
CS1#
I/O0
I/O2
C
I/O9
I/O10
A5
A6
I/O1
I/O2
I/O3
VDD
D
GND
I/O11
A17
A7
I/O3
VDD
A16
I/O4
GND
D
VDD
I/O12
NC
A16
I/O4
GND
A14
A15
I/O5
I/O6
F
I/O14
I/O13
A14
A15
I/O5
I/O6
NC
A12
A13
WE#
I/O7
G
I/O15
NC
A12
A13
WE#
I/O7
A8
A9
A10
A11
NC
H
NC
A8
A9
A10
A11
NC
PIN DESCRIPTIONS
A0-A17
I/O0-I/O15
CS1#, CS2
OE#
WE#
LB#
NC
Address Inputs
Data Inputs/Outputs
Chip Enable Input
Output Enable Input
Write Enable Input
Lower-byte Control
(I/O0-I/O7)
Upper-byte Control
(I/O8-I/O15)
No Connection
VDD
GND
Power
Ground
UB#
A
44-Pin mini TSOP (Type II)
A4
1
44
A5
A3
2
43
A6
A2
3
42
A7
A1
4
41
40
OE#
5
CS#
6
39
LB#
I/O0
7
8
9
38
37
I/O15
I/O1
I/O2
36
I/O14
I/O13
I/O3
10
35
I/O12
VDD
11
34
GND
GND
12
I/O4
13
33
32
VDD
I/O11
I/O5
I/O6
14
31
30
I/O10
I/O9
I/O7
16
17
29
I/O8
28
NC
A16
18
27
A8
A15
A14
19
26
20
A9
A10
A13
21
25
24
22
23
WE#
A12
Integrated Silicon Solution, Inc.- www.issi.com
Rev. 0B
08/04/2015
UB#
A0
14
A11
A17
2
IS62WV25616EALL/EBLL/ECLL
IS65WV25616EBLL/ECLL
FUNCTION DESCRIPTION
SRAM is one of random access memories. Each byte or word has an address and can be accessed randomly. SRAM
has three different modes supported. Each function is described below with Truth Table.
STANDBY MODE
Device enters standby mode when deselected (CS1# HIGH or CS2 LOW or both UB# and LB# are HIGH). The input
and output pins (I/O0-15) are placed in a high impedance state. The current consumption in this mode will be ISB1 or
ISB2. CMOS input in this mode will maximize saving power.
WRITE MODE
Write operation issues with Chip selected (CS1# LOW and CS2 HIGH) and Write Enable (WE#) input LOW. The input
and output pins (I/O0-15) are in data input mode. Output buffers are closed during this time even if OE# is LOW. UB#
and LB# enables a byte write feature. By enabling LB# LOW, data from I/O pins (I/O0 through I/O7) are written into the
location specified on the address pins. And with UB# being LOW, data from I/O pins (I/O8 through I/O15) are written
into the location.
READ MODE
Read operation issues with Chip selected (CS1# LOW and CS2 HIGH) and Write Enable (WE#) input HIGH. When
OE# is LOW, output buffer turns on to make data output. Any input to I/O pins during READ mode is not permitted. UB#
and LB# enables a byte read feature. By enabling LB# LOW, data from memory appears on I/O0-7. And with UB#
being LOW, data from memory appears on I/O8-15.
In the READ mode, output buffers can be turned off by pulling OE# HIGH. In this mode, internal device operates as
READ but I/Os are in a high impedance state. Since device is in READ mode, active current is used.
TRUTH TABLE
Mode
Not Selected
Output Disabled
Read
Write
CS1#
CS2
WE#
OE#
LB#
UB#
I/O0-I/O7
I/O8-I/O15
H
X
X
L
L
L
L
L
L
L
L
X
L
X
H
H
H
H
H
H
H
H
X
X
X
H
H
H
H
H
L
L
L
X
X
X
H
H
L
L
L
X
X
X
X
X
H
L
X
L
H
L
L
H
L
X
X
H
X
L
H
L
L
H
L
L
High-Z
High-Z
High-Z
High-Z
High-Z
DOUT
High-Z
DOUT
DIN
High-Z
DIN
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
DOUT
DOUT
High-Z
DIN
DIN
Integrated Silicon Solution, Inc.- www.issi.com
Rev. 0B
08/04/2015
VDD Current
ISB2
ICC,ICC1
ICC,ICC1
ICC,ICC1
3
IS62WV25616EALL/EBLL/ECLL
IS65WV25616EBLL/ECLL
ABSOLUTE MAXIMUM RATINGS AND OPERATING RANGE
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Vt er m
Parameter
Terminal Voltage with Respect to GND
Value
–0.5 to VDD + 0.5V
Unit
V
VDD
V DD Related to GND
–0.3 to 4.0
V
tStg
Storage Temperature
–65 to +150
PT
Power Dissipation
1.0
C
W
Notes:
1.
Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
(1)
OPERATING RANGE
Range
Ambient Temperature
Commercial
PART
NUMBER
0C to +70C
SPEED (MAX)
VDD(MIN)
VDD(TYP)
VDD(MAX)
55 ns
1.65V
1.8V
2.2V
55 ns
1.65V
1.8V
2.2V
Industrial
-40C to +85C
Automotive
-40C to +125C
55 ns
1.65V
1.8V
2.2V
0C to +70C
45ns
2.2V
3.0V
3.6V
45ns
2.2V
3.0V
3.6V
Commercial
~EALL
Industrial
-40C to +85C
Automotive
-40C to +125C
55ns
2.2V
3.0V
3.6V
Commercial
~EBLL
0C to +70C
35ns
3.135V
3.3V
3.465V
Industrial
-40C to +85C
35ns
3.135V
3.3V
3.465V
Automotive
-40C to +125C
45ns
3.135V
3.3V
3.465V
Note:
1.
~ECLL
Full device AC operation assumes a 100 µs ramp time from 0 to Vcc(min) and 200 µs wait time after Vcc stabilization.
PIN CAPACITANCE
Parameter
(1)
Symbol
Input capacitance
DQ capacitance (IO0–IO15)
Test Condition
CIN
CI/O
TA = 25°C, f = 1 MHz, VDD = VDD(typ)
Max
Units
6
8
pF
pF
Note:
1. These parameters are guaranteed by design and tested by a sample basis only.
(1)
THERMAL CHARACTERISTICS
Parameter
Thermal resistance from junction to ambient (airflow = 1m/s)
Thermal resistance from junction to pins
Thermal resistance from junction to case
Symbol
RθJA
RθJB
RθJC
Rating
TBD
TBD
TBD
Units
°C/W
°C/W
°C/W
Note:
1. These parameters are guaranteed by design and tested by a sample basis only.
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Rev. 0B
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4
IS62WV25616EALL/EBLL/ECLL
IS65WV25616EBLL/ECLL
AC TEST CONDITIONS (OVER THE OPERATING RANGE)
Parameter
Unit
(1.65V~2.2V)
0.4V to VDD -0.3V
Input Pulse Level
Input Rise and Fall Time
Output Timing Reference Level
R1
R2
VTM
Output Load Conditions
1V/ns
0.9V
13500
10800
1.8V
Unit
(2.2V~3.6V)
0.4V to VDD -0.3V
Unit
(3.3V +/-5%)
0.4V to VDD -0.3V
1V/ns
1V/ns
½ VDD
½ VDD + 0.05V
1005
1213
820
1378
3.0V
3.3V
Refer to Figure 1 and 2
OUTPUT LOAD CONDITIONS FIGURES
FIGURE 1
FIGURE 2
R1
R1
VTM
VTM
OUTPUT
OUTPUT
30pF,
Including
jig
and scope
R2
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Rev. 0B
08/04/2015
5pF,
Including
jig
and scope
R2
5
IS62WV25616EALL/EBLL/ECLL
IS65WV25616EBLL/ECLL
DC ELECTRICAL CHARACTERISTICS
IS62(5)WV25616EALL DC ELECTRICAL CHARACTERISTICS-I (OVER THE OPERATING RANGE)
VDD = 1.65V ~ 2.2V
Symbol
VOH
VOL
(1)
VIH
(1)
VIL
ILI
ILO
Parameter
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage
Output Leakage
Test Conditions
I OH = -0.1 mA
IOL = 0.1 mA
GND < VIN < VDD
GND < VIN < VDD, Output Disabled
Min.
1.4
—
1.4
–0.2
–1
–1
Max.
—
0.2
VDD + 0.2
0.4
1
1
Unit
V
V
V
V
µA
µA
Notes:
1. VILL(min) = -1.0V AC (pulse width < 10ns). Not 100% tested.
VIHH (max) = VDD + 1.0V AC (pulse width < 10ns). Not 100% tested.
IS62(5)WV25616EBLL DC ELECTRICAL CHARACTERISTICS-I (OVER THE OPERATING RANGE)
VDD = 2.2V ~ 3.6V
Symbol
VOH
Parameter
Output HIGH Voltage
VOL
Output LOW Voltage
Max.
—
—
0.4
0.4
VDD + 0.3
VDD + 0.3
0.6
0.8
1
1
Unit
V
V
V
V
V
V
V
V
µA
µA
IS62(5)WV25616ECLL DC ELECTRICAL CHARACTERISTICS-I (OVER THE OPERATING RANGE)
(2)
VDD = 3.3V +/-5%
Symbol
Parameter
Test Conditions
Min.
Max.
VOH
Output HIGH Voltage
I OH = -1.0 mA
2.4
—
VOL
Output LOW Voltage
IOL = 2.1 mA
—
0.4
(1)
VIH
Input HIGH Voltage
2.0
VDD + 0.3
(1)
VIL
Input LOW Voltage
–0.3
0.8
ILI
Input Leakage
GND < VIN < VDD
–1
1
ILO
Output Leakage
GND < VIN < VDD, Output Disabled
–1
1
Unit
V
V
V
V
µA
µA
(1)
Input HIGH Voltage
(1)
Input LOW Voltage
VIH
VIL
ILI
ILO
Input Leakage
Output Leakage
Test Conditions
2.2 ≤ V DD < 2.7, I OH = -0.1 mA
2.7 ≤ V DD ≤ 3.6, I OH = -1.0 mA
2.2 ≤ V DD < 2.7, IOL = 0.1 mA
2.7 ≤ V DD ≤ 3.6, IOL = 2.1 mA
2.2 ≤ V DD < 2.7
2.7 ≤ V DD ≤ 3.6
2.2 ≤ V DD < 2.7
2.7 ≤ V DD ≤ 3.6
GND < VIN < VDD
GND < VIN < VDD, Output Disabled
Min.
2.0
2.4
—
—
1.8
2.0
–0.3
–0.3
–1
–1
Notes:
1. VILL(min) = -2.0V AC (pulse width < 10ns). Not 100% tested.
VIHH (max) = VDD + 2.0V AC (pulse width < 10ns). Not 100% tested.
Notes:
1. VILL(min) = -2.0V AC (pulse width < 10ns). Not 100% tested.
VIHH (max) = VDD + 2.0V AC (pulse width < 10ns). Not 100% tested.
2. VDD=3.3V +/-5% is for high speed of 35ns device (ECLL).
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Rev. 0B
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IS62WV25616EALL/EBLL/ECLL
IS65WV25616EBLL/ECLL
IS62(5)WV25616EALL DC ELECTRICAL CHARACTERISTICS-II FOR POWER
(OVER THE OPERATING RANGE)
Symbol
ICC
ICC1
Parameter
Test Conditions
VDD Dynamic
Operating
Supply Current
VDD Static
Operating
Supply Current
CMOS Standby
Current (CMOS
Inputs)
VDD = MAX, IOU T= 0 mA, f = fMAX
ISB2
Notes:
1.
Grade
-55
Max.
20
22
22
5
5
5
Com.
Ind./Auto A1
Auto. A3
Com.
Ind./Auto A1
Auto. A3
VDD = MAX,
IOUT = 0 mA, f = 0
VDD = MAX,
(1) 0V ≤ CS2 ≤ 0.2V
or
(2) CS1# ≥ VDD - 0.2V, CS2 ≥ VDD - 0.2V
or
(3) LB# and UB# ≥ VDD - 0.2V
CS1# ≤ 0.2V, CS2 ≥ VDD - 0.2V, f = 0
Com.
6
Ind./Auto A1
8
Auto. A3
20
(1)
3.5
typ.
Unit
mA
mA
µA
Typical values are measured at VDD = 1.8V, TA = 25C , and not 100% tested.
IS62(5)WV25616EBLL/ECLL DC ELECTRICAL CHARACTERISTICS-II FOR POWER
(OVER THE OPERATING RANGE)
Symbol
ICC
ICC1
ISB2
Parameter
Test Conditions
VDD Dynamic
Operating
Supply Current
VDD Static
Operating
Supply Current
CMOS
Standby
Current
(CMOS Inputs)
VDD = MAX, IOU T= 0 mA, f = fMAX
VDD = MAX,
IOUT = 0 mA, f = 0
VDD = MAX,
(1) 0V ≤ CS2 ≤ 0.2V
or
(2) CS1# ≥ VDD - 0.2V, CS2 ≥ VDD - 0.2V
or
(3) LB# and UB# ≥ VDD - 0.2V
CS1# ≤ 0.2V, CS2 ≥ VDD - 0.2V, f = 0
Grade
(1)
-35
Max.
22
25
5
5
-
-45
Max.
20
22
22
5
5
5
-55
Max.
20
22
22
5
5
5
Com.
6
6
6
Ind./Auto A1
8
8
8
Auto. A3
-
20
20
Com.
Ind./Auto A1
Auto. A3
Com.
Ind./Auto A1
Auto. A3
(2)
typ.
Unit
mA
mA
µA
3.5
Notes:
1. 35 ns speed bin is for ECLL (VDD=3.3V +/-5%) only.
2. Typical values are measured at VDD = 3.0V, TA = 25C , and not 100% tested.
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IS62WV25616EALL/EBLL/ECLL
IS65WV25616EBLL/ECLL
AC CHARACTERISTICS
(6)
(OVER OPERATING RANGE)
READ CYCLE AC CHARACTERISTICS
(7)
35ns
Min
Max
45ns
Min
Max
55ns
Min
Max
Parameter
Symbol
unit
notes
Read Cycle Time
Address Access Time
Output Hold Time
tRC
tAA
tOHA
35
8
35
-
45
10
45
-
55
10
55
-
ns
ns
ns
1,5
1
1
CS1#, CS2 Access Time
UB#, LB# Access Time
OE# Access Time
OE# to High-Z Output
OE# to Low-Z Output
CS1#, CS2 to High-Z Output
tACS1/ACS2
tBA
tDOE
tHZOE
tLZOE
tHZCS
4
-
35
35
18
12
12
5
-
45
45
20
15
15
5
-
55
55
25
20
20
ns
ns
ns
ns
ns
ns
1
1
1
2
2
2
CS1#, CS2 to Low-Z Output
UB#, LB# to High-Z Output
UB#, LB# to Low-Z Output
tLZCS
tHZB
tLZB
10
10
12
-
10
10
15
-
10
10
20
-
ns
ns
ns
2
2
2
unit
notes
WRITE CYCLE AC CHARACTERISTICS
(7)
35ns
Min
Max
45ns
Min
Max
55ns
Min
Min
Parameter
Symbol
Write Cycle Time
CS1#, CS2 to Write End
tWC
tSCS
35
30
-
45
35
-
55
40
-
ns
ns
1,3,5
1,3
Address Setup Time to Write End
UB#,LB# to Write End
Address Hold from Write End
Address Setup Time
WE# Pulse Width
Data Setup to Write End
tAW
tAW
tHA
tSA
tPWE
tSD
30
30
0
0
30
18
-
35
35
0
0
35
20
-
40
40
0
0
40
25
-
ns
ns
ns
ns
ns
ns
1,3
1,3
1,3
1,3
1,3,4
1,3
Data Hold from Write End
WE# LOW to High-Z Output
WE# HIGH to Low-Z Output
tHD
tHZWE
tLZWE
0
4
12
-
0
5
15
-
0
5
20
-
ns
ns
ns
1,3
2,3
2,3
Notes:
1. Tested with the load in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. tHZOE, tHZCS, tHZB, and tHZWE transitions are
measured when the output enters a high impedance state. Not 100% tested.
3. The internal write time is defined by the overlap of CS1# = LOW, CS2=HIGH, UB# or LB# = LOW, and WE# = LOW. All four conditions must be
in valid states to initiate a Write, but any condition can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced
to the rising or falling edge of the signal that terminates the write.
4. tPWE > tHZWE + tSD when OE# is LOW.
5. Address inputs must meet VIH and VIL SPEC during this period. Any glitch or unknown inputs are not permitted. Unknown input with standby
mode is acceptable.
6. Data retention characteristics are defined later in DATA RETENTION CHARACTERISTICS.
7. 35 ns speed bin is for ECLL (VDD=3.3V +/-5%) only .
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IS62WV25616EALL/EBLL/ECLL
IS65WV25616EBLL/ECLL
Timing Diagram
READ CYCLE NO. 1
(1)
(ADDRESS CONTROLLED, CS1# = OE# = UB# = LB# = LOW, CS2 = WE# = HIGH)
tRC
Address
tAA
tOHA
tOHA
PREVIOUS DATA VALID
DQ 0-15
LOW-Z
DATA VALID
Notes:
1. The device is continuously selected.
READ CYCLE NO. 2
(1)
(OE# CONTROLLED, WE# = HIGH)
tRC
ADDRESS
tAA
tOHA
tDOE
OE#
tHZOE
tLZOE
CS1#
tHZCS1/
tHZCS2
tACS1/tACS2
CS2
tLZCS1/
tLZCS2
UB#,LB#
tHZB
tBA
tLZB
DOUT
HIGH-Z
LOW-Z
DATA VALID
Notes:
1. Address is valid prior to or coincident with CS1# LOW or CS2 HIGH transition.
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Rev. 0B
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IS62WV25616EALL/EBLL/ECLL
IS65WV25616EBLL/ECLL
WRITE CYCLE NO. 1(1,2) (CS1# , CS2 CONTROLLED, OE# = HIGH OR LOW)
tWC
ADDRESS
tSCS1
tSA
CS1#
tHA
tSCS2
CS2
tAW
tPWE
WE#
tPWB
UB#, LB#
tHZWE
DATA UNDEFINED
DOUT
HIGH-Z
(1)
tSD
DATA UNDEFINED
DIN
(2)
tLZWE
tHD
DATA IN VALID
Notes:
1. tHZWE is based on the assumption when tSA=0nS after READ operation. Actual DOUT for tHZWE may not appear if OE# goes high before
Write Cycle. tHZOE is the time DOUT goes to High-Z after OE# goes high.
2. During this period the I/Os are in output state. Do not apply input signals.
(1,2)
WRITE CYCLE NO. 2
(WE# CONTROLLED: OE# IS HIGH DURING WRITE CYCLE)
tWC
ADDRESS
tSCS1
CS1#
tSCS2
CS2
WE#
tHA
tAW
tPWE
tSA
tPWB
UB#, LB#
OE#
DOUT
tHZOE
DATA UNDEFINED
HIGH-Z
(1)
tSD
DIN
DATA UNDEFINED
(2)
tHD
DATA IN VALID
Notes:
1.
tHZOE is the time DOUT goes to High-Z after OE# goes high.
2. During this period the I/Os are in output state. Do not apply input signals.
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10
IS62WV25616EALL/EBLL/ECLL
IS65WV25616EBLL/ECLL
WRITE CYCLE NO. 3 (WE# CONTROLLED: OE# IS LOW DURING WRITE CYCLE)
tWC
ADDRESS
tSCS1
CS1#
tHA
tSCS2
CS2
tAW
WE#
tPWE
tSA
tPWB
UB#, LB#
tHZWE
DOUT
DATA UNDEFINED
(1)
HIGH-Z
tSD
DIN
DATA UNDEFINED
(2)
tLZWE
tHD
DATA IN VALID
Notes:
1. If OE# is low during write cycle, tHZWE must be met in the application. Do not apply input signal during this period. Data output from the
previous READ operation will drive IO BUS.
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IS62WV25616EALL/EBLL/ECLL
IS65WV25616EBLL/ECLL
WRITE CYCLE NO. 4 (UB# & LB# Controlled, OE# = LOW)
tWC
tWC
ADDRESS
ADDRESS 1
ADDRESS 2
CS1#=LOW
CS2=HIGH
OE#=LOW
tSA
tHA
tSA
tHA
WE#
tPWB
UB#, LB#
tPWB
WORD 1
WORD 2
tHZWE
DOUT
tLZWE
HIGH-Z
DATA UNDEFINED
tHD
tSD
DIN
DATA IN
VALID
DATA IN
VALID
Notes:
1. If OE# is low during write cycle, tHZWE must be met in the application. Do not apply input signal during this period. Data output from the
previous READ operation will drive IO BUS.
2. Due to the restriction of note1, OE# is recommended to be HIGH during write period.
3. Note WE# stays LOW in this example. If WE# toggles, tPWE and tHZWE must be considered.
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IS62WV25616EALL/EBLL/ECLL
IS65WV25616EBLL/ECLL
DATA RETENTION CHARACTERISTICS
Symbol
VDR
Parameter
VDD for Data
Retention
IDR
Data Retention
Current
tSDR
Data Retention
Setup Time
Recovery Time
tRDR
Test Condition
OPTION
See Data Retention Waveform
VDD= VDR(min),
(1) 0V ≤ CS2 ≤ 0.2V, or
(2) CS1# ≥ VDD – 0.2V,
CS2 ≥ VDD - 0.2V
(3) LB# and UB# ≥ VDD -0.2V,
CS1# ≤ 0.2V, CS2 ≥ VDD - 0.2V
Min.
Typ.
(2)
1.5
Max.
Unit
3.6
V
Com.
-
-
6
Ind./Auto A1
-
Auto A3
-
8
-
(2)
typ.
20
uA
3.5
See Data Retention Waveform
0
-
See Data Retention Waveform
tRC
-
-
ns
ns
Note:
1. If CS1# >VDD–0.2V, all other inputs including CS2 and UB# and LB# must meet this condition.
2. Typical values are measured at VDD = 3.0V, TA = 25C , and not 100% tested.
3. VDD power down slope must be longer than 100 us/volt when enter into Data Retention Mode.
DATA RETENTION WAVEFORM (CS1# CONTROLLED)
Data Retention Mode
tSDR
tRDR
VDD
VDR
CS1# > VDD – 0.2V
CS1#
GND
DATA RETENTION WAVEFORM (CS2 CONTROLLED)
DATA RETENTION MODE
VDD
CS2
tSDR
tRDR
VDR
CS2 < 0.2V
GND
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IS62WV25616EALL/EBLL/ECLL
IS65WV25616EBLL/ECLL
DATA RETENTION WAVEFORM (UB# AND LB# CONTROLLED)
tSDR
Data Retention Mode
tRDR
VDD
VDR
UB#/LB#
UB# and LB# > VDD – 0.2V
GND
Note:
1. CS2 must satisfy either CS2 ≥ VDD - 0.2V or CS2 ≤ 0.2V
2. CS1# must satisfy either CS1# ≥ VDD - 0.2V or CS1# ≤ 0.2V
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IS62WV25616EALL/EBLL/ECLL
IS65WV25616EBLL/ECLL
ORDERING INFORMATION
IS62WV25616EALL (1.65V - 2.2V)
Commercial Range: 0°C to +85°C
Speed (ns)
Order Part No.
Package
55
IS62WV25616EALL-55TL
TSOP (Type II), Lead-free
55
IS62WV25616EALL-55BL
mini BGA (6mm x 8mm), Lead-free
Industrial Range: –40°C to +85°C
Speed (ns)
Order Part No.
Package
55
IS62WV25616EALL-55TI
TSOP (Type II)
55
IS62WV25616EALL-55TLI
TSOP (Type II), Lead-free
55
IS62WV25616EALL-55BI
mini BGA (6mm x 8mm)
55
IS62WV25616EALL-55B2I
mini BGA (6mm x 8mm), 2 CS Option
55
IS62WV25616EALL-55BLI
mini BGA (6mm x 8mm), Lead-free
AUTOMOTIVE RANGE (A3): –40°C TO +125°C
*PLEASE CONTACT ISSI MARKETING
IS62WV25616EBLL (2.2V - 3.6V)
Industrial Range: –40°C to +85°C
Speed (ns)
45
55
Order Part No.
Package
IS62WV25616EBLL-45TI
TSOP (Type II)
IS62WV25616EBLL-45TLI
TSOP (Type II), Lead-free
IS62WV25616EBLL-45BI
mini BGA (6mm x 8mm)
IS62WV25616EBLL-45BLI
mini BGA (6mm x 8mm), Lead-free
IS62WV25616EBLL-45B2I
mini BGA (6mm x 8mm), 2 CS Option
IS62WV25616EBLL-45B2LI
mini BGA (6mm x 8mm), 2 CS Option, Lead-free
IS62WV25616EBLL-55TI
TSOP (Type II)
IS62WV25616EBLL-55TLI
TSOP (Type II), Lead-free
IS62WV25616EBLL-55BI
mini BGA (6mm x 8mm)
IS62WV25616EBLL-55BLI
mini BGA (6mm x 8mm), Lead-free
IS62WV25616EBLL-55B2I
mini BGA (6mm x 8mm), 2 CS Option
IS62WV25616EBLL-55B2LI
mini BGA (6mm x 8mm), 2 CS Option, Lead-free
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Rev. 0B
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IS62WV25616EALL/EBLL/ECLL
IS65WV25616EBLL/ECLL
Automotive Range (A1): –40°C to +85°C
Speed (ns)
45
Order Part No.
Package
IS65WV25616EBLL-45CTLA1
TSOP (Type II), Lead-free, Copper Lead-frame
IS65WV25616EBLL-45BLA1
mini BGA (6mm x 8mm), Lead-free
Automotive Range (A3): –40°C to +125°C
Speed (ns)
Order Part No.
Package
55
IS65WV25616EBLL-55CTLA3
TSOP (Type II), Lead-free, Copper Lead-frame
55
IS65WV25616EBLL-55BA3
mini BGA (6mm x 8mm)
55
IS65WV25616EBLL-55BLA3
mini BGA (6mm x 8mm), Lead-free
IS62WV25616ECLL (3.3V +/-5%)
Industrial Range: –40°C to +85°C
Speed (ns)
Order Part No.
Package
35
IS62WV25616ECLL-35TI
TSOP (Type II)
35
IS62WV25616ECLL-35TLI
TSOP (Type II), Lead-free
35
IS62WV25616ECLL-35BI
mini BGA (6mm x 8mm)
35
IS62WV25616ECLL-35BLI
mini BGA (6mm x 8mm), Lead-free
35
IS62WV25616ECLL-35B2I
mini BGA (6mm x 8mm), 2 CS Option
35
IS62WV25616ECLL-35B2LI
mini BGA (6mm x 8mm), 2 CS Option, Lead-free
Automotive Range (A3): –40°C to +125°C
Speed (ns)
Order Part No.
Package
45
IS65WV25616ECLL-45CTLA3
TSOP (Type II), Lead-free, Copper Lead-frame
45
IS65WV25616ECLL-45BA3
mini BGA (6mm x 8mm)
45
IS65WV25616ECLL-45BLA3
mini BGA (6mm x 8mm), Lead-free
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Rev. 0B
08/04/2015
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IS62WV25616EALL/EBLL/ECLL
IS65WV25616EBLL/ECLL
PACKAGE INFORMATION
Integrated Silicon Solution, Inc.- www.issi.com
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IS62WV25616EALL/EBLL/ECLL
IS65WV25616EBLL/ECLL
Integrated Silicon Solution, Inc.- www.issi.com
Rev. 0B
08/04/2015
18