3SK295 Silicon N-Channel Dual Gate MOS FET REJ03G0814-0300 (Previous ADE-208-387A) Rev.3.00 Aug. 10, 2005 Application • UHF RF amplifier Features • Low noise figure. NF = 2.0 dB typ. at f = 900 MHz • Capable of low voltage operation Outline RENESAS Package code: PLSP0004ZA-A (Package name: MPAK-4) 2 3 1 1. Source 2. Gate1 3. Gate2 4. Drain 4 Note: Marking is “ZQ–” Attention: This device is very sensitive to electro static discharge. It is recommended to adopt appropriate cautions when handling this transistor. Rev.3.00, Aug 10.2005, page 1 of 6 3SK295 Absolute Maximum Ratings (Ta = 25°C) Item Drain to source voltage Gate 1 to source voltage Gate 2 to source voltage Drain current Channel power dissipation Channel temperature Storage temperature Symbol VDS VG1S VG2S ID Pch Tch Tstg Ratings 12 ±8 ±8 25 150 150 –55 to +150 Unit V V V mA mW °C °C Electrical Characteristics (Ta = 25°C) Item Drain to source breakdown voltage Symbol V(BR)DSX Min 12 Typ — Max — Unit V Gate 1 to source breakdown voltage Gate 2 to source breakdown voltage Gate 1 cutoff current Gate 2 cutoff current Drain current V(BR)G1SS V(BR) G2SS IG1SS IG2SS IDS(on) ±8 ±8 — — 0.5 — — — — — — — ±100 ±100 10 V V nA nA mA Gate 1 to source cutoff voltage VG1S(off) –0.5 — +0.5 V VDS = 10 V, VG2S = 3 V, ID = 100 µA Gate 2 to source cutoff voltage VG2S(off) 0 — +1.0 V VDS = 10 V, VG1S = 3 V, ID = 100 µA Forward transfer admittance |yfs| 16 20.8 — mS VDS = 6 V, VG2S = 3 V, ID = 10 mA, f = 1 kHz Input capacitance Output capacitance Reverse transfer capacitance Power gain Noise figure Ciss Coss Crss PG NF 1.2 0.6 — 16 — 1.5 0.9 0.01 19.5 2.0 2.2 1.2 0.03 — 3 pF pF pF dB dB VDS = 6 V, VG2S = 3 V, ID = 10 mA, f = 1 MHz Rev.3.00, Aug 10.2005, page 2 of 6 Test conditions ID = 200 µA , VG1S = –3 V, VG2S = –3 V IG1 = ±10 µA, VG2S = VDS = 0 IG2 = ±10 µA, VG1S = VDS = 0 VG1S = ±6 V, VG2S = VDS = 0 VG2S = ±6 V, VG1S = VDS = 0 VDS = 6 V, VG1S = 0.5 V, VG2S = 3 V VDS = 4 V, VG2S = 3 V, ID = 10 mA, f = 900 MHz 3SK295 Main Characteristics 20 200 Pulse test (mA) 150 16 ID VG2S = 3 V 12 1.2 V Drain Current 1.0 V 100 50 0 50 100 150 Ambient Temperature 0.8 V 8 0.6 V 4 VG1S = 0.4 V 0 200 2 4 10 Drain Current vs. Gate2 to Source Voltage 20 20 Pulse test (mA) 2.0 V 2.5 V 16 2.0 V VDS = 6 V 16 12 12 Drain Current ID 8 Drain to Source Voltage VDS (V) Ta (°C) 8 1.0 V 4 VDS = 6 V 1.5 V 1.5 V Drain Current 6 Drain Current vs. Gate1 to Source Voltage 3.0 V (mA) Typical Output Characteristics ID Channel Power Dissipation Pch (mW) Maximum Channel Power Dissipation Curve Pulse test 1.0 V 8 VG1S = 0.5 V 4 VG2S = 0.5 V 1 2 3 4 0 5 1 2 3 4 5 Gate1 to Source Voltage VG1S (V) Gate2 to Source Voltage VG2S (V) Forward Transfer Admittance vs. Gate1 to Source Voltage Power Gain vs. Drain Current 25 VDS = 6 V f = 1 kHz 24 VG2S = 3.0 V 18 2.5 V 2.0 V 12 1.5 V 6 PG (dB) 30 Power Gain Forward Transfer Admittance |yfs| (mS) 0 1.0 V 20 15 10 VDS = 4 V VG2S = 3 V f = 900 MHz 5 0.5 V 0 0.4 0.8 1.2 1.6 2.0 Gate1 to Source Voltage VG1S (V) Rev.3.00, Aug 10.2005, page 3 of 6 0 1 2 5 Drain Current 10 ID (mA) 20 3SK295 Noise Figure vs. Drain Current Power Gain vs. Drain to Source Voltage 25 4 PG (dB) VDS = 4 V VG2S = 3 V f = 900 MHz 3 Power Gain Noise Figure NF (dB) 5 2 1 0 1 2 5 10 Drain Current ID 20 (mA) Noise Figure NF (dB) 5 4 3 2 VG2S = 3 V ID = 10 mA f = 900 MHz 0 2 4 6 Drain to Source Voltage Rev.3.00, Aug 10.2005, page 4 of 6 8 15 10 VG2S = 3 V ID = 10 mA f = 900 MHz 5 0 2 4 6 Drain to Source Voltage Noise Figure vs. Drain to Source Voltage 1 20 10 VDS (V) 8 10 VDS (V) 3SK295 S11 Parameter vs. Frequency S21 Parameter vs. Frequency 1 90° .8 .6 1.5 Scale: 0.5 / div. 60° 120° 2 .4 3 4 5 .2 30° 150° 10 .2 0 .4 .6 .8 1.0 1.5 2 3 45 10 180° 0° –10 –5 –4 –.2 –3 –.4 –30° –150° –2 –.6 –.8 –1 –60° –120° –1.5 –90° Condition: VDS = 4 V, VG2S = 3 V ID = 10 mA, Zo = 50 Ω Condition: VDS = 4 V, VG2S = 3 V ID = 10 mA, Zo = 50 Ω 100 to 1000 MHz (50 MHz step) 100 to 1000 MHz (50 MHz step) S12 Parameter vs. Frequency S22 Parameter vs. Frequency 90° Scale: 0.002/ div. .8 60° 120° 1 .6 1.5 2 .4 3 30° 150° 4 5 .2 10 180° 0° .2 0 .4 .6 .8 1.0 1.5 2 3 45 10 –10 –5 –4 –.2 –30° –150° –3 –.4 –60° –120° –90° –2 –.6 –.8 –1 –1.5 Condition: VDS = 4 V, VG2S = 3 V ID = 10 mA, Zo = 50 Ω Condition: VDS = 4 V, VG2S = 3 V ID = 10 mA, Zo = 50 Ω 100 to 1000 MHz (50 MHz step) 100 to 1000 MHz (50 MHz step) Rev.3.00, Aug 10.2005, page 5 of 6 3SK295 Package Dimensions JEITA Package Code RENESAS Code SC-61AA Package Name PLSP0004ZA-A MASS[Typ.] MPAK-4 / MPAK-4V D 0.013g A e e2 b1 Q c B B E HE Reference Symbol L A LP L1 A A3 x M S b A e2 A2 e I1 A b5 S b b2 e1 A1 y S b1 b3 c1 c c1 I1 c b4 A-A Section B-B Section Pattern of terminal position areas A A1 A2 A3 b b1 b2 b3 c c1 D E e e2 HE L L1 LP x y b4 b5 e1 I1 Q Dimension in Millimeters Min 1.0 0 1.0 0.35 0.55 0.1 2.7 1.35 2.2 0.35 0.15 0.25 Nom 1.1 0.25 0.42 0.62 0.4 0.6 0.13 0.11 1.5 0.95 0.85 2.8 Max 1.3 0.1 1.2 0.5 0.7 0.15 3.1 1.65 3.0 0.75 0.55 0.65 0.05 0.05 0.55 0.75 1.95 1.05 0.3 Ordering Information Part Name 3SK295ZQ-TL-E Quantity 3000 Shipping Container φ178 mm Reel, 8 mm Emboss Taping Note: For some grades, production may be terminated. Please contact the Renesas sales office to check the state of production before ordering the product. Rev.3.00, Aug 10.2005, page 6 of 6 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. 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