RENESAS BB505CES

BB505C
Build in Biasing Circuit MOS FET IC
UHF RF Amplifier
REJ03G0364-0100Z
Rev.1.00
Jun.14.2004
Features
•
•
•
•
Build in Biasing Circuit; To reduce using parts cost & PC board space.
Low noise; NF = 1.5 dB typ. at f = 900 MHz
High gain; PG = 24 dB typ. at f = 900 MHz
Withstanding to ESD;
Build in ESD absorbing diode. Withstand up to 190 V at C = 200 pF, Rs = 0 conditions.
• Provide mini mold packages; CMPAK-4 (SOT-343mod)
Outline
CMPAK-4
2
3
1
4
Notes:
1. Source
2. Gate1
3. Gate2
4. Drain
1. Marking is “ES-”.
2. BB505C is individual type number of RENESAS BBFET.
Absolute Maximum Ratings
(Ta = 25°C)
Item
Symbol
Ratings
Unit
Drain to source voltage
Gate1 to source voltage
VDS
VG1S
6
+6
–0
V
V
Gate2 to source voltage
VG2S
+6
–0
V
ID
Pchnote3
Tch
Tstg
20
250
150
–55 to +150
mA
mW
°C
°C
Drain current
Channel power dissipation
Channel temperature
Storage temperature
Notes: 3. Value on the glass epoxy board (50 mm × 40 mm × 1 mm ).
Rev.1.00, Jun.14.2004, page 1 of 8
BB505C
Electrical Characteristics
(Ta = 25°C)
Item
Symbol
Min
Typ
Max
Unit
Test Conditions
Drain to source breakdown
voltage
V(BR)DSS
6
—
—
V
ID = 200 µA, VG1S = VG2S = 0
Gate1 to source breakdown
voltage
V(BR)G1SS
+6
—
—
V
IG1 = +10 µA, VG2S = VDS = 0
Gate2 to source breakdown
voltage
Gate1 to source cutoff current
Gate2 to source cutoff current
Gate1 to source cutoff voltage
Gate2 to source cutoff voltage
Drain current
V(BR)G2SS
+6
—
—
V
IG2 = +10 µA, VG1S = VDS = 0
IG1SS
IG2SS
VG1S(off)
VG2S(off)
ID(op)
—
—
0.5
0.5
7
—
—
0.7
0.7
11
+100
+100
1.0
1.0
15
nA
nA
V
V
mA
VG1S = +5 V, VG2S = VDS = 0
VG2S = +5 V, VG1S = VDS = 0
VDS = 5 V, VG2S = 4 V, ID = 100 µA
VDS = 5 V, VG1S = 5 V, ID = 100 µA
Forward transfer admittance
|yfs|
28
33
38
mS
VDS = 5 V, VG1 = 5 V, VG2S = 4 V
RG = 220 kΩ, f = 1 kHz
Input capacitance
Ciss
1.4
1.75
2.1
pF
Output capacitance
Coss
1.0
1.4
1.8
pF
VDS = 5 V, VG1 = 5 V, VG2S = 4 V
RG = 220 kΩ, f = 1 MHz
Reverse transfer capacitance
Power gain
Crss
PG
—
19
0.03
24
0.05
29
pF
dB
Noise figure
NF
—
1.5
2.2
dB
VDS = 5 V, VG1 = 5 V, VG2S = 4 V
RG = 220 kΩ
VDS = 5 V, VG1 = 5 V, VG2S = 4 V
RG = 220 kΩ, f = 900 MHz
Bias Circuit for Operating Items (ID(op), |yfs|, Ciss, Coss, Crss, NF, PG)
VG2
RG
Gate 2
Gate 1
Drain
Source
A
ID
Rev.1.00, Jun.14.2004, page 2 of 8
VG1
BB505C
900 MHz Power Gain, Noise Figure Test Circuit
VD
VG1 VG2
C6
C4
C5
R1
R2
C3
R3
RFC
Output (50 Ω)
D
G2
L3
Input (50 Ω)
L4
G1
S
L1
L2
C1
C1, C2
C3
C4 to C6
R1
R2
R3
C2
:
:
:
:
:
:
Variable Capacitor (10 pF MAX)
Disk Capacitor (1000 pF)
Air Capacitor (1000 pF)
220 kΩ
47 kΩ
4.7 kΩ
L2:
L1:
10
3
3
8
10
26
(φ1mm Copper wire)
Unit : mm
21
L4:
L3:
18
10
10
7
7
29
RFC : φ1mm Copper wire with enamel 4 turns inside dia 6 mm
Rev.1.00, Jun.14.2004, page 3 of 8
BB505C
Typical Output Characteristics
200
100
0
50
100
150
Ambient Temperature Ta (°C)
0k
Ω
kΩ
0
kΩ
0
=
G
10
kΩ
0
2
2 Ω
k
0
27 kΩ
0
33
5
0
200
12
15
15
300
VG2S = 4 V
VG1 = VDS
R
ID (mA)
20
18
Maximum Channel Power Dissipation Curve
400
Drain Current
Channel Power Dissipation Pch* (mW)
Main Characteristics
1
2
3
4
5
Drain to Source Voltage VDS (V)
* Value on the glass epoxy board (50mm × 40mm × 1mm)
Drain Current vs. Gate1 Voltage
|yfs| (mS)
20
15
Forward Transfer Admittance
Drain Current
ID (mA)
VDS = 5 V
RG = 220 kΩ
4V
3V
10
2V
5
VG2S = 1 V
0
1
2
3
4
Gate1 Voltage VG1 (V)
5
50
VDS = 5 V
VG1 = 5V
40 RG = 220 kΩ
f = 1 kHz
3V
2V
20
10
VG2S = 1 V
0
1
2
3
4
Gate1 Voltage VG1 (V)
5
Input Capacitance vs.
Gate2 to Source Voltage
20
4
VDS = 5 V
VG1 = 5 V
VG2S = 4 V
15
10
5
200
500
Gate Resistance RG (kΩ)
Rev.1.00, Jun.14.2004, page 4 of 8
1000
Input Capacitance Ciss (pF)
Drain Current ID (mA)
4V
30
Drain Current vs. Gate Resistance
0
100
Forward Transfer Admittance
vs. Gate1 Voltage
3
2
VDS = 5 V
VG1 = 5 V
RG = 220 kΩ
f = 1 MHz
1
0
0
2
1
3
4
Gate2 to Source Voltage VG2S (V)
BB505C
Power Gain vs. Gate Resistance
Noise Figure vs. Gate Resistance
NF (dB)
VDS = 5 V
VG1 = 5 V
40 VG2S = 4 V
f = 900 MHz
Noise Figure
30
20
10
0
100
25
Power Gain PG (dB)
4
20
VDS = 5 V
VG1 = 5 V
RG = 220 kΩ
f = 900 MHz
5
1
1
2
3
4
Gate2 to Source Voltage VG2S (V)
40
VDS = 5 V
VG1 = 5 V
RG = 220 kΩ
f = 900MHz
30
20
10
1
2
3
4
Gate2 to Source Voltage VG2S (V)
Rev.1.00, Jun.14.2004, page 5 of 8
200
500
1000
Noise Figure vs.
Gate2 to Source Voltage
5
4
3
2
1
Gain Reduction vs.
Gate2 to Source Voltage
Gain Reduction GR (dB)
2
Gate Resistance RG (kΩ)
Power Gain vs.
Gate2 to Source Voltage
10
0
3
100
1000
15
0
VDS = 5 V
VG1 = 5 V
VG2S = 4 V
f = 900 MHz
0
200
500
Gate Resistance RG (kΩ)
Noise Figure NF (dB)
Power Gain PG (dB)
50
0
VDS = 5 V
VG1 = 5 V
RG = 220 kΩ
f = 900 MHz
1
2
Gate2 to Source Voltage
3
VG2S (V)
4
BB505C
S21 Parameter vs. Frequency
S11 Parameter vs. Frequency
.8
1
.6
Scale: 1 / div.
90°
1.5
60°
120°
2
.4
3
30°
150°
4
5
.2
10
.2
0
.4
.6 .8 1
1.5 2
3 45
10
180°
0°
-10
-5
-4
-.2
-.4
-30°
-150°
-3
-2
-.6
-.8
-1
-90°
Condition: VDS = 5 V, VG1 = 5 V, VG2S = 4 V
RG = 220 kΩ, Zo = 50 Ω
50 to 1000 MHz (50 MHz Step)
Condition: VDS = 5 V, VG1 = 5 V, VG2S = 4 V
RG = 220 kΩ, Zo = 50 Ω
50 to 1000 MHz (50 MHz Step)
S12 Parameter vs. Frequency
Scale: 0.02 / div.
90°
S22 Parameter vs. Frequency
.8
60°
120°
-60°
-120°
-1.5
1
.6
1.5
2
.4
3
30°
150°
4
5
.2
10
180°
0°
.2
0
.4
.6 .8 1
1.5 2
3 45
10
-10
-5
-4
-.2
-30°
-150°
-3
-.4
-60°
-120°
-90°
Condition: VDS = 5 V, VG1 = 5 V, VG2S = 4 V
RG = 220 kΩ, Zo = 50 Ω
50 to 1000 MHz (50 MHz Step)
Rev.1.00, Jun.14.2004, page 6 of 8
-2
-.6
-.8
-1
-1.5
Condition: VDS = 5 V, VG1 = 5 V, VG2S = 4 V
RG = 220 kΩ, Zo = 50 Ω
50 to 1000 MHz (50 MHz Step)
BB505C
S parameter
(VDS = 5 V, VG1 = 5 V, VG2S = 4 V, RG = 200 kΩ, ZO = 50 Ω)
S11
f (MHz)
MAG
S21
ANG
MAG
S12
ANG
MAG
S22
ANG
MAG
ANG
50
100
150
200
250
300
350
400
450
500
550
600
650
700
750
0.991
0.991
0.993
0.983
0.977
0.969
0.962
0.952
0.944
0.929
0.914
0.897
0.881
0.863
0.842
-2.4
-5.9
-8.9
-11.9
-15.3
-18.5
-21.6
-25.2
-28.7
-32.2
-36.0
-40.0
-44.2
-48.3
-52.7
3.55
3.58
3.58
3.56
3.59
3.50
3.51
3.52
3.52
3.51
3.51
3.50
3.49
3.47
3.45
178.2
172.9
170.2
165.9
162.6
155.5
151.0
146.9
142.6
138.2
133.4
129.0
124.2
119.4
114.5
0.009
0.011
0.002
0.004
0.006
0.008
0.006
0.007
0.008
0.008
0.008
0.008
0.010
0.010
0.008
-64.5
18.0
61.4
77.7
87.6
87.8
94.6
80.9
87.1
78.1
74.7
84.8
72.6
67.5
78.7
0.976
0.995
0.990
0.986
0.986
0.990
0.984
0.982
0.977
0.973
0.968
0.963
0.957
0.950
0.943
-1.8
-3.1
-5.2
-6.5
-8.2
-12.9
-15.1
-17.3
-19.5
-21.8
-24.0
-26.1
-28.2
-30.4
-32.6
800
850
900
950
1000
0.819
0.797
0.775
0.746
0.721
-57.3
-62.0
-66.8
-71.8
-76.9
3.41
3.37
3.33
3.27
3.20
109.7
104.9
99.9
94.9
90.2
0.008
0.008
0.008
0.007
0.007
82.1
85.3
95.6
97.4
122.8
0.939
0.931
0.924
0.916
0.909
-34.6
-36.6
-38.7
-40.6
-42.4
Rev.1.00, Jun.14.2004, page 7 of 8
BB505C
Package Dimensions
As of January, 2003
Unit: mm
0.1
0.3 +– 0.05
0.2
0.65 0.6
1.25 ± 0.2
0.9 ± 0.1
0.1
0.4 +– 0.05
0 – 0.1
0.425
0.1
0.3 +– 0.05
+ 0.1
0.16– 0.06
2.1 ± 0.3
0.65 0.65
1.25 ± 0.1
0.1
0.3 +– 0.05
0.425
2.0 ± 0.2
1.3 ± 0.2
Package Code
JEDEC
JEITA
Mass (reference value)
CMPAK-4(T)
—
Conforms
0.006 g
Ordering Information
Part Name
BB505CES-
Quantity
3000
Shipping Container
Taping
Note: For some grades, production may be terminated. Please contact the Renesas sales office to check the state of
production before ordering the product.
Rev.1.00, Jun.14.2004, page 8 of 8
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Keep safety first in your circuit designs!
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble
may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary
circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
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Colophon .1.0