2SK1579 Silicon N Channel MOS FET REJ03G0956-0200 (Previous: ADE-208-1296) Rev.2.00 Sep 07, 2005 Application High speed power switching Features • Low on-resistance • High speed switching • Suitable for low voltage operation Outline RENESAS Package code: PLZZ0004CA-A (Package name: UPAK R ) 3 D 2 1 4 1. Gate 2. Drain 3. Source 4. Drain G S Note: Marking is “DY”. *UPAK is a trademark of Renesas Technology Corp. Rev.2.00 Sep 07, 2005 page 1 of 5 2SK1579 Absolute Maximum Ratings (Ta = 25°C) Item Drain to source voltage Gate to source voltage Drain current Drain peak current Body to drain diode reverse drain current Symbol VDSS Ratings 12 Unit V VGSS ID ±7 2 V A 4 2 A A ID(pulse) IDR *1 *2 Channel power dissipation Channel temperature Pch Tch 1 150 Storage temperature Tstg Notes: 1. PW ≤ 100 µs, duty cycle ≤ 10% 2. Value on the alumina ceramic board (12.5 × 20 × 0.7 mm) –55 to +150 W °C °C Electrical Characteristics (Ta = 25°C) Item Drain to source cutoff current Symbol IDSS Min — Typ — Max 1 Unit µA Test conditions VDS = 8 V, VGS = 0 Gate to source cutoff current Gate to source cutoff voltage IGSS VGS(off) — 0.4 — — ±5 1.4 µA V VGS = ±6.5 V, VDS = 0 VDS = 5 V, ID = 100 µA Drain to source on resistance (1) Drain to source on resistance (2) RDS(on)1 RDS(on)2 — — 0.36 0.25 0.7 0.35 Ω Ω VGS = 2.2 V, ID = 0.5 A *3 VGS = 4 V, ID = 1 A |yfs| 1 2.5 — S VDS = 5 V, ID = 1 A, *3 ∆VGS = 0.1 V VDS = 5 V, VGS = 0, f = 1 MHz DC forward transfer admittance Input capacitance Ciss — 110 — pF Reverse transfer capacitance Output capacitance Crss Coss — — 30 150 — — pF pF t(on) t(off) — — 500 1500 — — ns ns Turn-on time Turn-off time Note: 3. Pulse Test Rev.2.00 Sep 07, 2005 page 2 of 5 *3 ID = 0.2 A, VGS = 0, *3 Vin = 4 V, RL = 51 Ω 2SK1579 Maximum Channel Power Dissipation Curve Maximum Safe Operation Area 50 1.6 20 0.8 0.4 50 0 100 150 Ambient Temperature 2 1 200 ar n) PW = 10 ms 1 Shot era tio n( T C =2 5° 0.2 2 5 Ta = 25°C Pulse Test 3 2V 1 Ta = –25°C 25°C 75°C 4 3 2 VDS = 5 V Pulse Test 1 VGS = 1.5 V 6 8 3 2 5 4 Gate to Source Voltage VGS (V) Drain to Source on State Resistance vs. Gate to Source Voltage Static Drain to Source on State Resistance vs. Drain Current 0.4 ID = 0.1 A 0.2 A 0.3 0.5 A 1 A 0.2 0 1 Drain to Source Voltage VDS (V) 0.5 0.1 0 10 Ta = 25°C Pulse Test 1 2 3 4 Gate to Source Voltage VGS (V) Rev.2.00 Sep 07, 2005 page 3 of 5 5 Static Drain to Source on State Resistance RDS (on) (Ω) Drain to Source on State Resistance RDS (on) (Ω) 4 50 100 Typical Transfer Characteristics 2.5 V 2 10 20 Drain to Source Voltage VDS (V) Ta (°C) 4 0 C) 5 3.5 V 3V 2 Op 0.1 Ta = 25°C 0.05 0.1 0.2 0.5 1 Drain Current ID (A) Drain Current ID (A) 4V DC 0.5 Typical Output Characteristics 5 (o 5 ea 10 DS 1.2 O is per lim ati ite on d b in y R this Drain Current ID (A) Channel Power Dissipation Pch** (W) (** on the almina ceramic board) Main Characteristics 5 2 Ta = 25°C Pulse Test 2V 1 VGS = 3 V 0.5 4V 0.2 0.1 0.05 0.2 0.5 1 2 5 Drain Current ID (A) 10 20 Static Drain to Source on State Resistance vs. Temperature Forward Transfer Admittance vs. Drain Current 1.0 Pulse Test 0.8 0.6 0.4 ID = 1 A 0.5 A VGS = 2 V ID = 0.5 A VGS = 4 V 0.2 1A 0 –25 2A 0 50 25 75 100 Forward Transfer Admittance yfs (S) Static Drain to Source on State Resistance RDS (on) (Ω) 2SK1579 10 Ta = –25°C 25°C 75°C 5 2 1 0.05 0.2 1 0.5 5 2 10 Reverse Drain Current vs. Source to Drain Voltage Typical Capacitance vs. Drain to Source Voltage 20 500 Coss Pulse Test 4 Capacitance C (pF) Reverse Drain Current IDR (A) 20 Drain Current ID (A) 3 2 VGS = 2 V 1 VGS = 0 0 2.0 1.0 Source to Drain Voltage VSD (V) 5,000 VGS = 4 V, VDD = 10 V PW = 2 µs, Duty cycle = 1% 2,000 td(off) tf 200 tr 100 50 0.05 0.1 td(on) 0.2 0.5 1 2 Drain Current ID (A) Rev.2.00 Sep 07, 2005 page 4 of 5 Ciss 100 Crss 50 20 VGS = 0 f = 1 MHz 5 0.1 0.2 0.5 1 2 5 Drain to Source Voltage VDS (V) Switching Characteristics 1,000 200 10 0 Switching Time t (ns) VDS = 5 V Pulse Test Case Temperature TC (°C) 5 500 50 5 10 2SK1579 Package Dimensions RENESAS Code Package Name MASS[Typ.] PLZZ0004CA-A UPAK / UPAKV 0.050g 1.5 1.5 3.0 1.5 ± 0.1 0.44 Max 2.5 ± 0.1 4.25 Max (1.5) 0.44 Max (0.2) 0.53 Max 0.48 Max 0.8 Min φ1 0.4 4.5 ± 0.1 1.8 Max Unit: mm (2.5) SC-62 (0.4) JEITA Package Code Ordering Information Part Name 2SK1579DY Quantity 3000 pcs Shipping Container Taping, φ178 mm Reel Note: For some grades, production may be terminated. Please contact the Renesas sales office to check the state of production before ordering the product. Rev.2.00 Sep 07, 2005 page 5 of 5 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. 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