Ordering number : ENA2175 LC87F2608A CMOS IC 8K-byte FROM and 512-byte RAM integrated http://onsemi.com 8-bit 1-chip microcontroller Overview The LC87F2608A is an 8-bit microcontroller that, centered around a CPU running at a minimum bus cycle time of 100ns, integrates on a single chip a number of hardware features such as 8K-byte flash ROM, 512-byte RAM, an on-chip debugger, two sophisticated 16-bit timers/counters (may be divided into 8-bit timers), a synchronous SIO interface, a high-speed 12-bit PWM, two high-speed pulse width/period counters, a 3-channel AD converter with 12-/8-bit resolution selector, an analog comparator, a watchdog timer, an internal reset circuit, a system clock frequency divider, and a 16-source 10-vector interrupt feature. Package Dimensions Features Flash ROM • 8192 × 8 bits (LC87F2608A) • Capable of on-board-programming with wide range of voltage source (3.0 to 5.5V). • Block-erasable in 128-byte units unit : mm (typ) 3420 5.0 10 0.5 4.4 6.2 RAM • 512 × 9 bits (LC87F2608A) 1 0.8 MAX 2 1.0 0.15 0.35 0.05 (1.5) 1.55 Package Form • MFP10SK: Lead-/Halogen-free type • MFP14S (for debugging only): Lead-free type • MFP10S: Lead-/Halogen-free type (discontinued) MFP10SK(225mil) Package Dimensions Package Dimensions unit : mm (typ) 3111A unit : mm (typ) 3086B (for debugging only) (discontinued) 8 6 1 5 4.4 0.63 0.15 0.15 0.1 (1.5) 0.1 (1.5) 0.35 1.7max 7 1.0 1.7MAX 1 (1.0) 6.4 4.4 6.4 10 0.63 5.0 8.0 14 MFP14S(225mil) 0.35 1.0 (0.5) MFP10S(225mil) * This product is licensed from Silicon Storage Technology, Inc. (USA). Semiconductor Components Industries, LLC, 2013 April, 2013 40313HKIM 20120403-S00001 No.A2175-1/23 LC87F2608A Minimum Bus Cycle Time (Note1) • 100ns (10MHz) VDD=2.7 to 5.5V (Note2) Minimum Instruction Cycle Time • 300ns (10MHz) VDD=2.7 to 5.5V (Note2) Note1: The bus cycle time here refers to the ROM read speed. Note2: Use this product in a voltage range of 3.0 to 5.5V because the minimum release voltage (PORRL) of the power-on reset (POR) circuit is 2.87V±0.12V. Ports • I/O ports Ports whose I/O direction can be designated in 1 bit units: 7 (P10 to P12, P30 to P33) • Reset pins: 1 (RES) • Power pins: 2 (VSS1, VDD1) Timers • Timer 0: 16-bit timer/counter with a capture register Mode 0: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) × 2 channels Mode 1: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) + 8-bit counter (with an 8-bit capture register) Mode 2: 16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register) Mode 3: 16-bit counter (with a 16-bit capture register) • Timer 1: 16-bit timer/counter Mode 0: 8-bit timer with an 8-bit prescaler + 8-bit timer/counter with an 8-bit prescaler Mode 2: 16-bit timer/counter with an 8-bit prescaler Serial Interface • SIO7: 8-bit synchronous serial interface 1) LSB first/MSB first mode selectable 2) Built-in 8-bit baudrate generator (maximum transfer clock cycle = 4/3 tCYC) High-speed 12-bit PWM • System clock/high-speed RC oscillation clock (20MHz or 40MHz) operation selectable • Duty/period programmable • Continuous PWM output/specific count PWM output (automatic stop) selectable High-speed Pulse Width/Period Counter • HCT1: High-speed pulse width/period counter 1 1) System clock/high-speed RC oscillation clock (20MHz or 40MHz) operation selectable 2) H-level width/L-level width/period measurement modes selectable 3) Input triggering noise filter • HCT2: High-speed pulse width/period counter 2 1) System clock/high-speed RC oscillation clock (20MHz or 40MHz) operation selectable 2) Can measure both L-level width and period simultaneously. 3) Input triggering noise filter 4) Input trigger selectable (from 3 signals, i.e., P11/HCT2IN, P31/HCT2IN, and analog comparator output) No.A2175-2/23 LC87F2608A AD Converter: 12 bits × 3 channels • 12-/8-bit AD converter resolution selectable Analog Comparator • Sends output to the P32/CMPO port (polarity selectable). • Edge detection function (shared with INTC and also allows the selection of the noise filter function) Watchdog Timer • Can generate the internal reset signal on a timer overflow monitored by the WDT-dedicated low-speed RC oscillation clock (30kHz). • Allows selection of continue, stop, or hold mode operation of the counter on entry into the HALT/ HOLD mode. Interrupt Source Flags • 16 sources, 10 vector addresses 1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector address takes precedence. No. Vector Address Level 1 00003H X or L Interrupt Source 2 0000BH X or L INTB 3 00013H H or L INTC/T0L/INTE 4 0001BH H or L INTD/INTF 5 00023H H or L T0H/SIO7 6 0002BH H or L T1L/T1H INTA 7 00033H H or L HCT1 8 0003BH H or L HCT2 9 00043H H or L ADC/HPWM automatic stop/HPWM cycle 10 0004BH H or L None • Priority levels X > H > L • Of interrupts of the same level, the one with the smallest vector address takes precedence. Subroutine Stack Levels: 256 levels maximum (The stack is allocated in RAM.) High-speed Multiplication/Division Instructions • 16 bits × 8 bits (5 tCYC execution time) • 24 bits × 16 bits (12 tCYC execution time) • 16 bits ÷ 8 bits (8 tCYC execution time) • 24 bits ÷ 16 bits (12 tCYC execution time) Oscillation Circuits • Medium speed RC oscillation circuit (internal): For system clock (1MHz) • Low speed RC oscillation circuit (internal): For watchdog timer (30kHz) • High speed RC oscillation circuit (internal): For system clock (20MHz or 40MHz) 1) 2 source oscillation frequencies (20MHz or 40MHz) selectable for the high-speed RC oscillation circuit by optional configuration. System Clock Divider Function • Can run on low current. • The minimum instruction cycle selectable from 300ns, 600ns, 1.2μs, 2.4μs, 4.8μs, 9.6μs, 19.2μs, 38.4μs, and 76.8μs (when high speed RC oscillation is selected for system clock.). No.A2175-3/23 LC87F2608A Internal Reset Circuit • Power-on reset (POR) function 1) POR reset is generated only at power-on time. 2) The POR release level can be selected from 3 levels (2.87V, 3.86V, and 4.35V) by optional configuration. • Low-voltage detection reset (LVD) function 1) LVD and POR functions are combined to generate resets when power is turned on and when power voltage falls below a certain level. 2) The use or disuse of the LVD function and the low voltage threshold level (3 levels: 2.81V, 3.79V, and 4.28V) can be selected by optional configuration. Standby Function • HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation. 1) Oscillation is not halted automatically. 2) There are the following three ways of resetting the HALT mode. (1) Setting the Reset pin to the low level (2) Generating a reset signal via the watchdog timer or brown-out detector (3) Having an interrupt generated • HOLD mode: Suspends instruction execution and the operation of the peripheral circuits. 1) The medium- and high-speed RC oscillation circuits automatically stop operation. 2) There are the following four ways of resetting the HOLD mode. (1) Setting the Reset pin to the low level (2) Generating a reset signal via the watchdog timer or brown-out detector (3) Setting at least one of the INTA, INTB, INTC, INTD, INTE, and INTF pins to the specified level (INTA and INTB HOLD mode reset is available only when level detection is set.) (4) Applying input signals to the IN+ and IN- pins so that the analog comparator output is set to the specified level (when the analog comparator output is assigned to the INTC input) On-chip Debugger Function • Supports software debugging with the IC mounted on the target board (selectable from 3 series). 1) LC87D2708A : All terminal function of LC87F2608A can be used. 2) LC87F2708A : All terminal function of LC87F2608A can be used. The debug feature is limited. 3) LC87F2608A : The debugger terminal function when an On-chip debugger is used cannot be used. The debug feature is limited. • Two channels of on-chip debugger pins are available (LC87F2608A). Data Security Function (Note3) • Protects the program data stored in flash memory from unauthorized read or copy. Note3: This data security function does not necessarily provide absolute data security. No.A2175-4/23 LC87F2608A Development Tools • On-chip debugger: 1) TCB87-Type B + LC87D2708A or LC87F2708A 2) TCB87-Type B + LC87F2608A 3) TCB87-Type C (3 wire version) + LC87D2708A or LC87F2708A 4) TCB87-Type C (3 wire version) + LC87F2608A Programming Board Package Programming Board MFP10S MFP10SK W87F27M-DBG MFP14S Flash ROM Programming Board Maker Model Flash Support Group, Inc. (FSG) + Our company In-circuit Programmer Device Rev.01.01 or later LC87F2608A (FSG models) SIB87 (Inter Face Driver) (Our company model) (Note 4) Single/Gang Programmer Our company Version AF9101/AF9103 (Main body) In-circuit/ Gang Programmer Application Version SKK-DBG Type B 1.04 or later (Sanyo FWS) Chip Data Version LC87F2608A 2.10 or later For information about AF-series: Flash Support Group, Inc. TEL: +81-53-459-1050 E-mail: [email protected] Note4: On-board-programmer from FSG (AF9101/AF9103) and serial interface driver from Our company (SIB87) together can give a PC-less, standalone on-board-programming capabilities. No.A2175-5/23 LC87F2608A Pin Assignment P31/INTB/HCT2IN/DBGP01 1 10 P30/INTA/HCT1IN/DBGPX0 2 9 P32/INTC/CMPO/DBGP11 RES 3 8 P33/INTD/HPWM/DBGP12 P10/SO7/INTE/AN0/DBGP02 4 7 P11/SI7/SB7/INTE/IN+/HCT2IN/AN1 VSS1 5 6 P12/SCK7/INTF/IN-/AN2 VDD1 MFP10S “Lead-/Halogen-free type” MFP10SK “Lead-/Halogen-free type” MFP10S MFP10SK NAME 1 P31/INTB/HCT2IN/DBGP01 2 P30/INTA/HCT1IN/DBGPX0 3 RES 4 P10/SO7/INTE/AN0/DBGP02 5 VSS1 6 P12/SCK7/INTF/IN-/AN2 7 P11/SI7/SB7/INTE/IN+/HCT2IN/AN1 8 P33/INTD/HPWM/DBGP12 9 P32/INTC/CMPO/DBGP11 10 VDD1 No.A2175-6/23 LC87F2608A P31/INTB/HCT2IN/DBGP01 1 14 VDD1 P30/INTA/HCT1IN/DBGPX0 2 13 P32/INTC/CMPO/DBGP11 RES 3 12 P33/INTD/HPWM/DBGP12 P10/SO7/INTE/AN0/DBGP02 4 11 P11/SI7/SB7/INTE/IN+/HCT2IN/AN1 VSS1 5 10 P12/SCK7/INTF/IN-/AN2 NC 6 9 DBGP20 DBGP22 7 8 DBGP21 MFP14S (for debugging only) “Lead-free type” MFP14S NAME 1 P31/INTB/HCT2IN/DBGP01 2 P30/INTA/HCT1IN/DBGPX0 3 RES 4 P10/SO7/INTE/AN0/DBGP02 5 VSS1 6 NC 7 DBGP22 8 DBGP21 9 DBGP20 10 P12/SCK7/INTF/IN-/AN2 11 P11/SI7/SB7/INTE/IN+/HCT2IN/AN1 12 P33/INTD/HPWM/DBGP12 13 P32/INTC/CMPO/DBGP11 14 VDD1 No.A2175-7/23 LC87F2608A System Block Diagram Interrupt control IR Standby control PLA Flash ROM High-speed RC Freq. divider Mediumspeed RC Clock generator PC RES WDT (Low-speed RC) ACC Reset control Reset circuit (LVD/POR) Bus interface Timer 0 Port 1 (INTE-INTF) Timer 1 Port 3 (INTA-INTD) High-speed PWM DATA BUS SIO7 DATA BUS B register C register ALU PSW ADC RAR High-speed pulse width/period counter1 High-speed pulse width/period counter2 RAM Analog comparator Stack pointer On-chip debugger No.A2175-8/23 LC87F2608A Pin Description Pin Name I/O Description Option VSS1 - - power supply pin No VDD1 - + power supply pin No PORT1 I/O • 3-bit I/O port • I/O specifiable in 1-bit units P10 to P12 • Pull-up resistors can be turned on and off in 1-bit units • Multiplexed pins P10: SIO7 data output/ INTE input/HOLD release input/timer 1 event input/ timer 0L capture input/timer 0H capture input P11: SIO7 data input/bus I/O/ high-speed pulse width/period counter 2 inpu/t INTE input/HOLD release input/timer 1 event input/ timer 0L capture input/timer 0H capture input P12: SIO7 clock I/O/ Yes INTF input/HOLD release input/timer 1 event input/ timer 0L capture input/timer 0H capture input AD converter input ports: AN0 to AN2 (P10 to P12) Analog comparator input ports: IN+, IN- (P11, P12) On-chip debugger pin 1: DBGP02 (P10) • Interrupt acknowledge type PORT3 I/O Rising Falling INTE enable enable INTF enable enable Rising & H level L level enable disable disable enable disable disable Falling • 4-bit I/O port • I/O specifiable in 1-bit units P30 to P33 • Pull-up resistors can be turned on and off in 1-bit units • Multiplexed pins P30: INTA input/HOLD release input/timer 0L capture input/ high-speed pulse width/period counter 1 input P31: INTB input/HOLD release input/timer 0H capture input/ high-speed pulse width/period counter 2 input P32: INTC input/HOLD release input/timer 0 event input/ timer 0L capture input/analog comparator output P33: INTD input/HOLD release input/timer 0 event input/ Yes timer 0H capture input/high-speed PWM output On-chip debugger pin 1: DBGPX0 to DBGP01 (P30 to P31) On-chip debugger pin 2: DBGPX0 to DBGP12 (P30, P32 to P33) • Interrupt acknowledge type RES I/O Rising Falling INTA enable enable INTB enable enable INTC enable INTD enable Rising & H level L level disable enable enable disable enable enable enable enable disable disable enable enable disable disable External reset input/internal reset output Falling No No.A2175-9/23 LC87F2608A Port Output Types The table below lists the types of port outputs and the presence/absence of a pull-up resistor. Data can be read into any input port even if it is in the output mode. Port Name Option Selected P10 to P12 P30 to P33 Option Type in Units of 1 bit 1 bit Output Type Pull-up Resistor 1 CMOS 2 N-channel open drain Programmable 1 CMOS Programmable 2 N-channel open drain Programmable Programmable On-chip Debugger Pin Processing For the processing of the on-chip debugger pins, refer to the separately available documents entitled "RD87 On-chip Debugger Installation" and "LC872000 Series On-chip Debugger Pin Processing." Recommended Unused Pin Connections Recommended Unused Pin Connections Pin Name Board Software P10 to P12 OPEN Set output low P30 to P33 OPEN Set output low User Options Option Option Name Option Type Flash Version Switched in Description Unit of enable 1bit P30 to P33 enable 1bit - enable - enable - Brown-out trip level enable - 3 levels Power-on-reset level enable - 3 levels Oscillation frequency enable - Port output type Program start address Brown-out detector reset function Power-on-reset function High-speed RC oscillator circuit CMOS P10 to P12 Brown-out detector function N-channel open drain CMOS N-channel open drain 00000H 01E00H Enable: Used Disable: Not used 20 MHz 40 MHz MFP10S: LC87F2608A Package type - enable - MFP14S: Debugged by using LC87D2708A or LC87F2708A No.A2175-10/23 LC87F2608A Absolute Maximum Ratings at Ta=25°C, VSS1=0V Parameter Maximum supply Symbol Pin/Remarks VDD max VDD1 Input voltage VI Input/output VIO Conditions Specification VDD[V] min typ max -0.3 to +6.5 RES -0.3 to VDD+0.3 • Port 1 -0.3 to VDD+0.3 unit V voltage • Port 3 voltage Peak output IOPH(1) Port 1 High level output current IOPH(2) -7.5 mA Port 3 • CMOS output selected -10 • Per applicable pin Mean output IOMH(1) Port 1 (Note 1-1) • CMOS output selected -5 • Per applicable pin current IOMH(2) Port 3 • CMOS output selected -7.5 • Per applicable pin Total output ΣIOAH(1) current ΣIOAH(2) ΣIOAH(3) Low level output current • CMOS output selected • Per applicable pin current • Port 10 Total of currents at all • Ports 30, 31 applicable pins • Ports 11, 12 Total of currents at all • Ports 32, 33 applicable pins • Port 1 Total of currents at all • Port 3 applicable pins -20 -20 -35 Peak output IOPL(1) Port 1 Per applicable pin current IOPL(2) Port 3 Per applicable pin 10 Mean output IOML(1) Port 1 Per applicable pin 10 current IOML(2) Port 3 Per applicable pin 7.5 ΣIOAL(1) • Port 10 Total of currents at all 25 • Ports 30, 31 applicable pins (Note 1-1) Total output current ΣIOAL(2) ΣIOAL(3) Power dissipation Pd max(1) • Ports 11, 12 Total of currents at all • Ports 32, 33 applicable pins • Port 1 Total of currents at all • Port 3 applicable pins MFP10S 15 35 55 • Ta=-40 to +85°C 100 mW • Independent package • Ta=-40 to +85°C Pd max(2) 237 • Mounted on thermal test board (Note 1-2) Pd max(3) MFP10SK • Ta=-40 to +85°C 100 • Independent package Pd max(4) • Ta=-40 to +85°C 237 • Mounted on thermal test board (Note 1-2) Operating ambient Topr -40 to +85 Tstg -55 to +125 °C temperature Storage ambient temperature Note 1-1: Mean output current refers to the average of output currents measured for a period of 100ms. Note 1-2: Thermal test board used conforms to SEMI (size: 76.1×114.3×1.6tmm, glass epoxy board). Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. No.A2175-11/23 LC87F2608A Allowable Operating Conditions at Ta= -40 to +85°C, VSS1=0V Parameter Operating Symbol Pin/Remarks Conditions Specification VDD[V] min typ max unit VDD VDD1 0.272μs ≤ tCYC ≤ 100μs 2.7 5.5 VHD VDD1 RAM and register contents sustained 2.0 5.5 2.7 to 5.5 0.3VDD +0.7 VDD 2.7 to 5.5 0.75VDD VDD 4.0 to 5.5 VSS 0.1VDD+0.4 • Port 3 2.7 to 4.0 VSS RES 2.7 to 5.5 VSS 0.25VDD 2.7 to 5.5 0.272 100 μs 4.5 to 5.5 38 42 MH V supply voltage (Note 2-1) Memory sustaining in HOLD mode supply voltage High level VIH(1) Low level VIH(2) RES VIL(1) • Port 1 input voltage VIL(2) Instruction • Port 1 Output disabled • Port 3 input voltage Output disabled tCYC 0.2VDD cycle time (Note 2-2) Oscillation FmHRC(1) • High-speed RC oscillation frequency • 40MHz selected as option range • Ta=-20 to +85°C 40 z FmHRC(2) • High-speed RC oscillation 4.5 to 5.5 37.6 40 42.4 FmHRC(3) • 40MHz selected as option 3.5 to 5.5 36.8 40 43.2 FmHRC(4) FmHRC(5) • Ta=-40 to +85°C • High-speed RC oscillation 2.7 to 5.5 32 40 43.2 3.0 to 5.5 19 20 21 2.7 to 5.5 18.7 20 21.3 2.0 • 20MHz selected as option • Ta=-20 to +85°C FmHRC(6) • High-speed RC oscillation • 20MHz selected as option • Ta=-40 to +85°C Oscillation FmRC Medium-speed RC oscillation 2.7 to 5.5 0.5 1.0 FmSLRC Low-speed RC oscillation 2.7 to 5.5 15 30 tmsHRC • When high-speed RC oscillation 2.7 to 5.5 stabilization state is switched from stopped to time enabled. 60 kHz 100 μs • See Fig. 2. Note 2-1: Use this product in a voltage range of 3.0 to 5.5V because the minimum release voltage (PORRL) of the power-on reset (POR) circuit is 2.87V±0.12V. Note 2-2: Relationship between tCYC and oscillation frequency is as follows: • When system clock source is set to medium-speed RC oscillation 3/FmRC at a division ratio of 1/1, 6/FmRC at a division ratio of 1/2, 12/FmRC a division ratio of 1/4, and so forth • When system clock source is set to high-speed RC oscillation (40MHz selected by optional configuration) 12/FmHRC at a division ratio of 1/1, 24/FmHRC at a division ratio of 1/2, 48/FmHRC a division ratio of 1/4, and so forth • When system clock source is set to high-speed RC oscillation (20MHz selected by optional configuration) 6/FmHRC at a division ratio of 1/1, 12/FmHRC at a division ratio of 1/2, 24/FmHRC a division ratio of 1/4, and so forth No.A2175-12/23 LC87F2608A Electrical Characteristics at Ta= -40 to +85°C, VSS1=0V Parameter High level input Symbol IIH(1) current Pin/Remarks Conditions • Port 1 • Output disabled • Port 3 • Pull-up resistor off Specification VDD[V] 2.7 to 5.5 min typ max unit 1 μA • VIN=VDD (including output Tr. off leakage current) Low level input IIH(2) RES VIN=VDD 2.7 to 5.5 IIL • Port 1 • Output disabled 2.7 to 5.5 • Port 3 • Pull-up resistor off current 1 -1 • VIN=VSS (including output Tr. off leakage current) High level output VOH(1) CMOS output IOH=-1mA 4.5 to 5.5 VDD-1 voltage VOH(2) type port 1 IOH=-0.35mA 2.7 to 5.5 VDD-0.4 VOH(3) CMOS output IOH=-5mA 4.5 to 5.5 VDD-1.5 IOH=-0.7mA 2.7 to 5.5 VDD-0.4 IOL=10mA 4.5 to 5.5 1.5 IOL=1.4mA 2.7 to 5.5 0.4 VOH(4) type port 3 Low level output VOL(1) Port 1 voltage VOL(2) VOL(3) Port 3 VOL(4) Pull-up resistance Hysteresis voltage V IOL=5mA 4.5 to 5.5 1.5 IOL=0.7mA 2.7 to 5.5 0.4 VOH=0.9VDD Rpu(1) • Port 1 4.5 to 5.5 15 35 80 Rpu(2) • Port 3 2.7 to 4.5 18 50 150 Rpu(3) RES 2.7 to 5.5 216 360 504 VHYS • Port 1 2.7 to 5.5 0.1VDD V 2.7 to 5.5 10 pF kΩ • Port 3 • RES Pin capacitance CP All pins • VIN=VSS for pins other than that under test • f=1 MHz • Ta=25°C No.A2175-13/23 LC87F2608A Serial I/O Characteristics at Ta= -40 to +85°C, VSS1=0V SIO7 Serial I/O Characteristics (Note 4-1-1) Input clock Symbol Frequency tSCK(1) Low level tSCKL(1) Pin/Remarks SCK7(P12) Conditions • See Fig. 4. Specification VDD [V] 2.7 to 5.5 (Note 4-1-2) min typ max 2 unit tCYC 1 pulse width High level tSCKH(1) 1 pulse width Output clock Serial clock Parameter Frequency tSCK(2) Low level tSCKL(2) SCK7(P12) • CMOS output selected 2.7 to 5.5 4/3 • See Fig. 4. 1/2 tSCK pulse width High level tSCKH(2) 1/2 pulse width Serial input Data setup time SB7(P11), SI7(P11) • Must be specified with respect to 2.7 to 5.5 μs 0.03 Rising edge of SIOCLK. • See Fig. 4. Data hold time Input clock Output delay thDI(1) tdDO(1) time 0.03 SO7(P10), SB7(P11) • Must be specified with respect to rising edge of SIOCLK. 2.7 to 5.5 1tCYC +0.05 • Must be specified as the time to the beginning of output state change in open drain output Output clock Serial output tsDI(1) tdDO(2) mode. • See Fig. 4. (1/3)tCYC +0.05 Note 4-1-1: These specifications are theoretical values. Add margin depending on its use. Note 4-1-2: To use serial-clock-input in transmission/reception mode, the time from SI7RUN being set when serial clock is "H" to the first falling edge of the serial clock must be longer than 1tCYC. No.A2175-14/23 LC87F2608A Pulse Input Conditions at Ta= -40 to +85°C, VSS1=0V Parameter Symbol Pin/Remarks High/low level tPIH(1) INTA(P30), pulse width tPIL(1) INTB(P31), INTD(P33), INTE(P10, P11), Conditions • Interrupt source flag can be Specification VDD[V] 2.7 to 5.5 min typ max 1 unit tCYC set. • Event inputs for timers 0 and 1 are enabled. INTF(P12) tPIH(2) INTC(P32) when noise tPIL(2) filter time constant is • Interrupt source flag can be 2.7 to 5.5 1 2.7 to 5.5 64 2.7 to 5.5 128 2.7 to 5.5 256 2.7 to 5.5 3 set. "none" • Event inputs for timer 0 are tPIH(3) INTC(P32) when noise • Interrupt source flag can be tPIL(3) filter time constant is enabled. set. "1/16" • Event inputs for timer 0 are tPIH(4) INTC(P32) when noise • Interrupt source flag can be tPIL(4) filter time constant is enabled. set. "1/32" • Event inputs for timer 0 are tPIH(5) INTC(P32) when noise • Interrupt source flag can be tPIL(5) filter time constant is enabled. set. "1/64" • Event inputs for timer 0 are HCT1IN(P30) Pulses can be recognized as signals enabled. tPIH(6) tPIL(6) H1CK by the high-speed pulse (Note width/period counter 1. tPIH(7) HCT2IN(P11, P31) tPIL(7) Pulses can be recognized as signals 5-1) 2.7 to 5.5 6 H2CK by the high-speed pulse (Note width/period counter 2. tPIL(8) Resetting is enabled. RES 5-2) 2.7 to 5.5 μs 200 Note 5-1: H1CK denotes the period of the base clock (1 to 8 × high-speed RC oscillation clock or system clock) for the high-speed pulse width/period counter 1. Note 5-2: H2CK denotes the period of the base clock (2 to 16 × high-speed RC oscillation clock or system clock) for the high-speed pulse width/period counter 2. Comparator Characteristics at Ta= -40 to +85°C, VSS1=0V Parameter Common mode Symbol VCMIN input voltage Pin/Remarks Conditions IN+(P11), Specification VDD [V] 2.7 to 5.5 min typ VSS max unit VDD-1.5 V IN-(P12) range Offset voltage VOFF Within common mode input voltage 2.7 to 5.5 ±10 ±30 mV 2.7 to 5.5 200 600 ns 1.0 μs range Response time tRT • Within common mode input voltage range • Input amplitude=100mV • Overdrive=50mV Operation tCMW 2.7 to 5.5 stabilization time (Note 6-1) Note 6-1: The interval after CMPON is set till the operation gets stabilized. No.A2175-15/23 LC87F2608A AD Converter Characteristics at VSS1=0V <12-bit AD conversion mode at Ta=-40 to +85°C > Parameter Symbol Pin/Remarks Resolution N AN0(P10) Absolute ET to AN2(P12) Specification Conditions VDD [V] 3.0 to 5.5 min typ max unit 12 bit (Note 7-1) 3.0 to 5.5 ±16 LSB • See "Conversion time calculation 4.0 to 5.5 38 104.3 3.0 to 5.5 75.8 104.3 3.0 to 5.5 VSS VDD V 1 μA accuracy Conversion time tCAD method." μs (Note 7-2) Analog input VAIN voltage range Analog port input IAINH VAIN= VDD 3.0 to 5.5 current IAINL VAIN= VSS 3.0 to 5.5 -1 <8-bit AD Converter Mode at Ta=-40 to +85°C > Parameter Symbol Pin/Remarks Resolution N AN0(P10) Absolute ET to AN2(P12) Specification Conditions VDD [V] 3.0 to 5.5 (Note 7-1) 3.0 to 5.5 • See "Conversion time calculation 4.0 to 5.5 3.0 to 5.5 3.0 to 5.5 min typ max unit 8 bit ±1.5 LSB 23.4 64.3 μs 46.7 64.3 VSS VDD V 1 μA accuracy Conversion time tCAD method." (Note 7-2) Analog input VAIN voltage range Analog port IAINH VAIN= VDD 3.0 to 5.5 input current IAINL VAIN= VSS 3.0 to 5.5 -1 <Conversion time calculation method> 12-bit AD conversion mode: tCAD (conversion time) = ((52/(division ratio)) + 2) × (1/3) × tCYC 8-bit AD conversion mode: tCAD (conversion time) = ((32/(division ratio)) + 2) × (1/3) × tCYC <Recommended Operating Conditions> High-speed RC Oscillation (FmHRC) 40MHz/20MHz Supply Voltage Range (VDD) System Clock Division Ratio (SYSDIV) Cycle Time AD Division Ratio (tCYC) (ADDIV) Conversion Time (tCAD) 12-bit AD 8-bit AD 4.0V to 5.5V 1/1 300ns 1/8 41.8μs 25.8μs 3.0V to 5.5V 1/1 300ns 1/16 83.4μs 51.4μs Note 7-1: The quantization error (±1/2LSB) is excluded from the absolute accuracy. The absolute accuracy is measured when no change occurs in the I/O state of the pins that are adjacent to the analog input channel during AD conversion processing. Note 7-2: The conversion time refers to the interval from the time a conversion starting instruction is issued till the time the complete digital conversion value against the analog input value is loaded in the result register. *The conversion time is twice the normal value when one of the following conditions occurs: • The first AD conversion executed in the 12-bit AD conversion mode after a system reset. • The first AD conversion executed after the AD conversion mode is switched from 8-bit to 12-bit AD conversion mode. No.A2175-16/23 LC87F2608A Power-on Reset (POR) Characteristics at Ta= -40 to +85°C, VSS 1=0V Specification Parameter Symbol Pin/Remarks Conditions Option Selecting Voltage POR release PORRL voltage area max 2.87V 2.75 2.87 2.99 • See Fig. 6. 3.86V 3.73 3.86 3.99 4.35V 4.21 4.35 4.49 0.7 0.95 • See Fig. 6. POUKS typ • Option selected (Note 8-1) Unknown voltage min unit V (Note 8-2) Power startup time PORIS Power startup time 100 ms from VDD=0V to 2.8V Note 8-1: The POR release voltage can be selected from three levels when the low-voltage detection feature is deselected. Note 8-2: There is an unpredictable period before the power-on reset transistor starts to turn on. Low-voltage Detection (LVD) Characteristics at Ta=-40 to +85°C, VSS 1=0V Specification Parameter Symbol Pin/Remarks Conditions Option Selecting Voltage LVD reset voltage LVDET (Note 9-2) LVHYS 2.81V 2.71 2.81 2.91 3.79V 3.69 3.79 3.89 4.28V 4.18 4.28 4.38 (Note 9-3) 2.81V 60 3.79V 65 4.28V LVUKS area Minimum low voltage detection max • See Fig. 7. hysteresis Unknown voltage typ • Option selected (Note 9-1) LVD voltage min unit V mV 65 • See Fig. 7. 0.7 0.95 V (Note 9-4) tLVDW • LVDET-0.5V 0.2 ms • See Fig. 8. width (response sensitivity) Note 9-1: The LVD reset voltage can be selected from three levels when the low-voltage detection feature is selected. Note 9-2: The hysteresis voltage is not included in the LVD reset voltage value. Note 9-3: There are cases when the LVD reset voltage value is exceeded when a greater change in the output level or large current is applied to the port. Note 9-4: There is an unpredictable period before the low-voltage detection resetting transistor starts to run. No.A2175-17/23 LC87F2608A Consumption Current Characteristics at Ta=-40 to +85°C, VSS 1=0V Specification Parameter Normal mode Symbol IDDOP(1) VDD1 Conditions • FmHRC=40MHz oscillation mode VDD [V] min typ max 4.5 to 5.5 7.8 14 2.7 to 3.6 4.9 9.4 4.5 to 5.5 7.1 12.8 2.7 to 3.6 4.5 8.6 4.5 to 5.5 0.60 1.9 2.7 to 3.6 0.38 1.3 4.5 to 5.5 3.2 5.0 2.7 to 3.6 2.0 3.1 4.5 to 5.5 2.5 3.9 2.7 to 3.6 1.6 2.5 4.5 to 5.5 0.32 1.0 2.7 to 3.6 0.16 0.55 unit mA • System clock set to high-speed RC, consumption current (Note 10-1) Pin/Remarks 10MHz (1/4 of 40MHz) IDDOP(2) • Medium-speed RC oscillation stopped • System clock frequency division ratio set to 1/1 IDDOP(3) • FmHRC=20MHz oscillation mode • System clock set to high-speed RC, 10MHz (1/2 of 20MHz) IDDOP(4) • Medium-speed RC oscillation stopped • System clock frequency division ratio set to 1/1 IDDOP(5) • High-speed RC oscillation stopped • System clock set to medium-speed RC oscillation mode IDDOP(6) • System clock frequency division ratio set to 1/2 HALT mode IDDHALT(1) HALT mode consumption • FmHRC=40MHz oscillation mode current • System clock set to high-speed RC, (Note 10-1) IDDHALT(2) 10MHz(1/4 of 40MHz) • Medium-speed RC oscillation stopped • System clock frequency division ratio set to 1/1 IDDHALT(3) HALT mode • FmHRC=20MHz oscillation mode • System clock set to high-speed RC, IDDHALT(4) 10MHz (1/2 of 20MHz) • Medium-speed RC oscillation stopped • System clock frequency division ratio set to 1/1 IDDHALT(5) HALT mode • High-speed RC oscillation stopped • System clock set to medium-speed RC IDDHALT(6) oscillation mode • System clock frequency division ratio set to 1/2 HOLD mode IDDHOLD(1) HOLD mode 4.5 to 5.5 0.04 3.0 consumption IDDHOLD(2) • Ta=-10 to +50°C 2.7 to 3.6 0.02 1.8 IDDHOLD(3) HOLD mode 4.5 to 5.5 0.04 34 IDDHOLD(4) • Ta=-40 to +85°C 2.7 to 3.6 0.02 22 IDDHOLD(5) HOLD mode 4.5 to 5.5 3.1 6.8 IDDHOLD(6) • LVD option selected 2.7 to 3.6 2.4 4.2 IDDHOLD(7) HOLD mode 4.5 to 5.5 3.1 39 IDDHOLD(8) • LVD option selected 2.7 to 3.6 2.4 25 IDDHOLD(9) HOLD mode 4.5 to 5.5 3.4 10 IDDHOLD(10) • Watchdog timer active 2.7 to 3.6 1.7 6.0 IDDHOLD(11) HOLD mode 4.5 to 5.5 3.4 42 IDDHOLD(12) • Watchdog timer active 2.7 to 3.6 1.7 27 current (Note 10-1) • Ta=-10 to +50°C μA • Ta=-40 to +85°C • Ta=-10 to +50°C • Ta=-40 to +85°C IDDHOLD(13) HOLD mode 4.5 to 5.5 110 160 IDDHOLD(14) • Comparator active 2.7 to 3.6 65 100 (IN+= VDD, IN-= VSS) Note 10-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors. No.A2175-18/23 LC87F2608A F-ROM Programming Characteristics at Ta=+10 to +55°C, VSS1=0V Parameter Onboard Symbol IDDFW Pin/Remarks VDD 1 programming Conditions • Microcontroller consumption Specification VDD [V] 3.0 to 5.5 min typ max 5 unit 10 mA 20 30 ms 40 60 μs current is excluded. current Programming tFW(1) • Erase operation time tFW(2) • Programming operation 3.0 to 5.5 Power Pin Treatment Recommendations (VDD1, VSS1) Connect bypass capacitors that meet the following conditions between the VDD1 and VSS1 pins: • Connect among the VDD1 and VSS1pins and bypass capacitors C1 and C2 with the shortest possible heavy lead wires, making sure that the impedances between the both pins and the bypass capacitors are as equal as possible (L1=L1', L2=L2'). • Connect a large-capacity capacitor C1 and a small-capacity capacitor C2 in parallel. The capacitance of C2 should be approximately 0.1μF. L2 L1 VSS1 C1 C2 VDD1 L1’ L2’ No.A2175-19/23 LC87F2608A 0.5VDD Figure 1 AC Timing Measurement Point VDD Operating VDD lower limit 0V Power Reset time RES Medium-speed RC scillation tmsHRC High-speed RC oscillation Operating mode Unpredictable Reset Instruction execution Reset Time and Oscillation Stabilization Time HOLD/HALT release signal No HOLD release signal HOLD release Signal valid HALT release signal valid Medium-speed RC oscillation tmsHRC High-speed RC oscillation State HOLD HALT Instruction execution HOLD Release Signal and Oscillation Stabilization Time Figure 2 Oscillation Stabilization Times No.A2175-20/23 LC87F2608A VDD Note: The external peripheral circuit differs depending on the way in which the power-on reset and low-voltage detection reset functions are used. Refer to the Chapter, entitled "Reset Function," of the user's manual. RRES RES CRES Figure 3 Sample Reset Circuit SIOCLK: DATAIN: DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DATAOUT: DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 tSCK tSCKL tSCKH SIOCLK: tsDI thDI DATAIN: tdDO DATAOUT: Figure 4 Serial I/O Waveforms tPIL tPIH Figure 5 Pulse Input Timing Signal Waveform No.A2175-21/23 LC87F2608A (a) POR release voltage (PORRL) (b) VDD Reset period Reset period 100μs or longer Reset unknown area (POUKS) RES Figure 6 Example of POR Only (LVD Deselected) Mode Waveforms (at Reset Pin with RRES Pull-up Resistor Only) • The POR circuit generates a reset signal only when the power voltage is raised from the VSS level. • No stable reset signal is generated if power is turned on again when the power voltage does not go down to the VSS level as shown in (a). If this case is anticipated, use the LVD function as explained below or configure an external reset circuit. • A reset is effected only when power is turned on again after the power voltage goes down to and remains at the VSS level for 100μs or longer as shown in (b). LVD hysteresis width (LVHYS) LVD release voltage (LVDET+LVHYS) VDD LVD voltage (LVDET) Reset period Reset period Reset period Reset unknown area (LVUKS) RES Figure 7 Example of POR + LVD Mode Waveforms (at Reset Pin with RRES Pull-up Resistor Only) • A reset is effected both when power is turned on and when it goes down. • The hysteresis width (LVHYS) is introduced in the LVD circuit to prevent the iterations of the IC entering and exiting the reset state near the detection threshold level. No.A2175-22/23 LC87F2608A VDD LVD release voltage LVD voltage LVDET-0.5V tLVDW VSS Figure 8 Minimum Low Voltage Detection Width (Example of Short Interruption of Power/ Power Fluctuation Waveform) ON Semiconductor and the ON logo are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. 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