PI6ULS5V9306 ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Dual bidirectional I2C-bus and SMBus voltage-level translator exists between ports. The PI6ULS5V9306 is not a bus buffer that provides both level translation and physically isolates to either side of the bus when both sides are connected. The PI6ULS5V9306 only isolates both sides when the device is disabled and provides voltage level translation when active. The PI6ULS5V9306 can also be used to run two buses, one at 400 kHz operating frequency and the other at 100 kHz operating frequency. If the two buses are operating at different frequencies, the 100 kHz bus must be isolated when the 400 kHz operation of the other bus is required. If the master is running at 400 kHz, the maximum system operating frequency may be less than 400 kHz because of the delays added by the translator. As with the standard I2C-bus system, pull-up resistors are required to provide the logic HIGH levels on the translator’s bus. The PI6ULS5V9306 has a standard open-collector configuration of the I2C-bus. The size of these pull-up resistors depends on the system, but each side of the translator must have a pull-up resistor. The device is designed to work with Standardmode, Fast-mode and Fast mode Plus I2C-bus devices in addition to SMBus devices. When the SDA1 or SDA2 port is LOW, the clamp is in the ON-state and a low resistance connection exists between the SDA1 and SDA2 ports. When the higher voltage is on the SDA2 port, and the SDA2 port is HIGH , the voltage on the SDA1 port is limited to the voltage set by VREF1. When the SDA1 port is HIGH, the SDA2 port is pulled to the drain pull-up supply voltage (VDPU) by the pull-up resistors. This functionality allows a seamless translation between higher and lower voltages selected by the user without the need for directional control. The SCL1/SCL2 channel also functions as the SDA1/SDA2 channel. All channels have the same electrical characteristics and there is minimal deviation from one output to another in voltage or propagation delay. This is a benefit over discrete transistor voltage translation solutions, since the fabrication of the switch is symmetrical. The translator provides excellent ESD protection to lower voltage devices, and at the same time protects less ESDresistant devices. Features 2-bit bidirectional translator for SDA and SCL lines in mixed-mode I2C-bus applications Standard-mode, Fast-mode, and Fast-mode Plus I2C-bus and SMBus compatible Less than 1.5 ns maximum propagation delay to accommodate Standard mode and Fast mode I2Cbus devices and multiple masters Allows voltage level translation between: 0.9V VREF1 and 1.8 V, 2.5 V, 3.3 V or 5 V VREF2 1.2 V VREF1 and 1.8 V, 2.5 V, 3.3 V or 5 V VREF2 1.5 V VREF1 and 2.5 V, 3.3 V or 5 V VREF2 1.8 V VREF1 and 3.3 V or 5 V VREF2 2.5 V VREF1 and 5 V VREF2 3.3 V VREF1 and 5 V VREF2 Provides bidirectional voltage translation with no direction pin Low 3.5 ohm -state connection between input and output ports provides less signal distortion Open-drain I2C-bus I/O ports (SCL1, SDA1, SCL2 and SDA2) 5 V tolerant I2C-bus I/O ports to support mixedmode signal operation High-impedance SCL1, SDA1, SCL2 and SDA2 pins for EN = LOW Lock-up free operation for isolation when EN = LOW Flow through pin out for ease of printed-circuit board trace routing ESD protection exceeds 4KV HBM per JESD22A114 Package: TDFN2x3-8L, MSOP-8L,SOIC-8L Description The PI6ULS5V9306 is a dual bidirectional I2C-bus and SMBus voltage-level translator with an enable (EN) input, and is operational from 1.0 V to 3.3 V (VREF1) and 1.8 V to 5.5 V(VREF2). The PI6ULS5V9306 allows bidirectional voltage translations between 1.0 V and 5 V without the use of a direction pin. The low ON-state resistance (Ron) of the switch allows connections to be made with minimal propagation delay. When EN is HIGH, the translator switch is on, and the SCL1 and SDA1 I/O are connected to the SCL2 and SDA2 I/O respectively, allowing bidirectional data flow between ports. When EN is LOW, the translator switch is off, and a high-impedance state 2015-08-0006 PT0451-5 1 8/18/15 PI6ULS5V9306 Dual bidirectional I2C-bus and SMBus voltage-level translator ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Pin Configuration MSOP-8L/SOIC-8L(Top View) TDFN2x3-8L(Top View) Pin Description Pin No 1 2 3 4 5 6 7 8 Name GND VREF1 SCL1 SDA1 SDA2 SCL2 VREF2 EN Description ground (0 V) low-voltage side reference supply voltage for SCL1 and SDA1 serial clock, low-voltage side; connect to VREF1 through a pull-up resistor serial data, low-voltage side; connect to VREF1 through a pull-up resistor serial data, high-voltage side; connect to VREF2 through a pull-up resistor serial clock, high-voltage side; connect to VREF2 through a pull-up resistor high-voltage side reference supply voltage for SCL2 and SDA2 switch enable input; connect to VREF2 and pull-up through a high resistor Block Diagram EN H L Function SCL1 = SCL2; SDA1 = SDA2 disabled Figure.1Block Diagram 2015-08-0006 PT0451-5 2 8/18/15 PI6ULS5V9306 Dual bidirectional I2C-bus and SMBus voltage-level translator ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Maximum Ratings Note: 1. Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. The input and input/output negative voltage ratings may be exceeded if the input and input/output clamp current ratings are observed. Storage Temperature ................................................................................... -65oC to +150oC Reference Voltage(2)..........................................................................................-0.5V to +6.0V Reference bias voltage.......................................................................................-0.5V to+6.0V DC Input Voltage .............................................................................................-0.5V to +6.0V Control Input Votage(EN) ...............................................................................-0.5V to+6.0V channel current (DC)....................................................................... 128mA Input clamping Current..................................................................... -50mA ESD: HBM Mode...........................................................................................................4000V Recommended operation conditions VCC = 2.7 V to 5.5 V; GND = 0 V; TA = -40 C to +85 C; unless otherwise specified Symbol Parameter Test Conditions Min. Typ. Max. Unit VI/O Voltage on an input/output pin SCL1, SDA1, SCL2, SDA2 0 - 5 V VREF1 Reference voltage (1) VREF1 0 - 5 V VREF2 Reference bias voltage (2) VREF2 0 - 5 V VI(EN) Input voltage on pin EN - 0 - 5 V I(pass) Pass switch current - - - 64 mA TA Ambient temperature - -40 - 85 oC DC Electrical Characteristics TA = -40 C to +85 C; unless otherwise specified Parameter Description Input and output SDAB and SCLB VIK input clamping voltage IIH Ci(EN) Cio(off) Cio(on) HIGH-level input current input capacitance on pin EN off-state input/output capacitance (SCLn, SDAn) on-state input/output capacitance (SCLn, SDAn) Test Conditions(1) Min Typ.(2) Max Unit II = -18mA; VI(EN) = 0 V - - -1.2 V VI = 5 V; VI(EN) = 0 V VI = 3 V or 0 V - 11 5 - µA pF VO = 3 V or 0 V; VI(EN) = 0 V - 4 - pF VO = 3 V or 0 V; VI(EN) = 3 V - 10.5 - pF VI(EN) = 4.5 V - 3.5 5.5 Ω VI(EN) = 3 V - 4.7 7.0 Ω VI(EN) = 2.3 V - 6.3 9.5 Ω VI(EN) = 1.5 V - 60 140 Ω VI(EN) = 4.5 V 1 6 15 Ω VI(EN) = 3 V 20 60 140 Ω VI(EN) = 2.3 V 20 60 140 Ω VI = 0V; IO = 64mA Ron ON-state resistance (SCLn, SDAn) (2) VI = 2.4V; IO = 15mA VI = 1.7V; IO = 15mA Notes: 1) All typical values are at TA = 25 °C. 2) Measured by the voltage drop between the SCL1 and SCL2, or SDA1 and SDA2 terminals at the indicated current through the switch. ON-state resistance is determined by the lowest voltage of the two terminals. 2015-08-0006 PT0451-5 3 8/18/15 PI6ULS5V9306 Dual bidirectional I2C-bus and SMBus voltage-level translator ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Dynamic characteristics TA = -40 C to +85 C; unless otherwise specified. Values guaranteed by design. CL = 50 pF Symbol Parameter CL = 30 pF CL = 15 pF Conditions Unit Min VI(EN) = 3.3 V; VIH = 3.3 V; VIL = 0 V; VM = 1.15 V LOW-to-HIGH from (input) SCL2 or SDA2 tPLH 0 propagation delay to (output) SCL1 or SDA1 HIGH-to-LOW from (input) SCL2 or SDA2 tPHL 0 propagation delay to (output) SCL1 or SDA1 VI(EN) = 2.5 V; VIH = 3.3 V; VIL = 0 V; VM = 0.75 V LOW-to-HIGH from (input) SCL2 or SDA2 tPLH 0 propagation delay to (output) SCL1 or SDA1 HIGH-to-LOW from (input) SCL2 or SDA2 tPHL 0 propagation delay to (output) SCL1 or SDA1 VI(EN) = 3.3 V; VIH = 2.3 V; VIL = 0 V; VT = 3.3 V; VM = 1.15 V; RL = 300 LOW-to-HIGH ffrom (input) SCL1 orSDA1 tPLH 0 propagation delay to (output) SCL2 or SDA2 HIGH-to-LOW from (input) SCL1 or SDA1 tPHL 0 propagation delay to (output) SCL2 or SDA2 VI(EN) = 2.5 V; VIH = 1.5 V; VIL = 0 V; VT = 2.5 V; VM = 0.75 V; RL = 300 LOW-to-HIGH from (input) SCL1 orSDA1 tPLH 0 propagation delay to (output) SCL2 or SDA2 HIGH-to-LOW from (input) SCL1 or SDA1 tPHL 0 propagation delay to (output) SCL2 or SDA2 Max Min Max Min Max 0.8 0 0.6 0 0.3 ns 1.2 0 1 0 0.5 ns 1 0 0.7 0 0.4 ns 1.3 0 1 0 0.6 ns 0.9 0 0.6 0 0.4 ns 1.4 0 1.1 0 0.7 ns 1 0 0.6 0 0.4 ns 1.3 0 1.3 0 0.8 ns Figure.2 Load Circuit for Outputs 2015-08-0006 PT0451-5 4 8/18/15 PI6ULS5V9306 Dual bidirectional I2C-bus and SMBus voltage-level translator ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Functional Description The PI6ULS5V9306 is a dual bidirectional I2C-bus and SMBus voltage-level translator with an enable (EN) input, and is operational from 1.2 V to 3.3 V (VREF1) and 1.8 V to 5.5 V(VREF2). The PI6ULS5V9306 allows bidirectional voltage translations between 1.2 V and 5 V without the use of a direction pin. The low ON-state resistance (Ron) of the switch allows connections to be made with minimal propagation delay. When EN is HIGH, the translator switch is on, and the SCL1 and SDA1 I/O are connected to the SCL2 and SDA2 I/O respectively, allowing bidirectional data flow between ports. When EN is LOW, the translator switch is off, and a high-impedance state exists between ports. The PI6ULS5V9306 is not a bus buffer that provides both level translation and physically isolates to either side of the bus when both sides are connected. The PI6ULS5V9306 only isolates both sides when the device is disabled and provides voltage level translation when active. The PI6ULS5V9306 can also be used to run two buses, one at 400kHz operating frequency and the other at 100 kHz operating frequency. If the two buses are operating at different frequencies, the 100 kHz bus must be isolated when the 400 kHz operation of the other bus is required. If the master is running at 400kHz, the maximum system operating frequency may be less than 400 kHz because of the delays added by the translator. As with the standard I2C-bus system, pull-up resistors are required to provide the logic HIGH levels on the translator’s bus. The PI6ULS5V9306 has a standard open-collector configuration of the I2C-bus. The size of these pull-up resistors depends on the system, but each side of the translator must have a pull-up resistor. The device is designed to work with Standard-mode, Fastmode and Fast mode Plus I2C-bus devices in addition to SMBus devices. When the SDA1 or SDA2 port is LOW, the clamp is in the ON-state and a low resistance connection exists between the SDA1 and SDA2 ports. When the higher voltage is on the SDA2 port, and the SDA2 port is HIGH, the voltage on the SDA1 port is limited to the voltage set by VREF1. When the SDA1 port is HIGH, the SDA2 port is pulled to the drain pull-up supply voltage (VDPU) by the pull-up resistors. This functionality allows a seamless translation between higher and lower voltages selected by the user without the need for directional control. The SCL1/SCL2 channel also functions as the SDA1/SDA2 channel. All channels have the same electrical characteristics and there is minimal deviation from one output to another in voltage or propagation delay. This is a benefit over discrete transistor voltage translation solutions, since the fabrication of the switch is symmetrical. The translator provides excellent ESD protection to lower voltage devices, and at the same time protects less ESDresistant devices. Application Information 0.1μF or 0.01μF Figure.3 Typical Open Drain Application Circuit (Switch Always Enabled ) 2015-08-0006 PT0451-5 5 8/18/15 PI6ULS5V9306 Dual bidirectional I2C-bus and SMBus voltage-level translator ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 0.1μF or 0.01μF Figure.4 Typical Open Drain Application Circuit (Switch Enabled Control) Open Drain Application For the bidirectional clamping configuration (higher voltage to lower voltage or lower voltage to higher voltage), the EN input must be connected to VREF2 and both pins pulled to high-side VDPU through a pull-up resistor (typically 200 kΩ). This allows VREF2 to regulate the EN input. A filter capacitor on VREF2 is recommended. Figure.5 Typical push-pull Application Circuit (Switch Enabled Control) Push Pull Application If used in push-pull system, the pull-up resistors on REF side are also needed. The data must be unidirectional or the outputs must be 3-stateable and be controlled by some direction-control mechanism to prevent high-to-low contentions in either direction. 2015-08-0006 PT0451-5 6 8/18/15 PI6ULS5V9306 Dual bidirectional I2C-bus and SMBus voltage-level translator ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Operating Voltage Refer to Figure 2 VDPU EN VREF1 IPASS IREF TA Ref2 side pull-up voltage on 200kΩ Enable input voltage Reference voltage Pass switch current Reference-transistor current Operating free-air temperature MIN TYP (1) MAX VREF1 + 0.6 2.1 5 VREF1 + 0.6 2.1 5 0 1.5 4.4 14 5 –40 85 UNIT V V V mA µA °C The pass through current : I_pass I_pass is determined by the pull-up and the low voltage added on the PI6LS5V9306 In figure 6, I_pass= (VREF1-VOL1_9306)/RPU1 When V_IN is 0V, the PI6ULS5V9306 can support as large as 64mA pass through current in theory. But we recommend it’s better to limit the I_pass in 15mA Figure 6. Typical Open Drain Application Circuit (1) The sink current : I_sink The device would sink the total current from both pull-up resistors. For example ,in figure bellow, when the SDA2 is pulled low by the I2C device, the sink current of the I2C device I_sink=Ipass+I_2=I_1+I_2 . The same thing will happen when I2C master pull low the I2C bus. The I_sink should be limited to not larger than the tolerance of the I2C devices. (2) VIL,VOL of the external drive and VOL of PI6ULS5V9306 In normal application , the VIL of external devices should always be larger than the VOL of PI6ULS5V9306. The value of PI6ULS5V9306’s VOL is determined by the pass through current and the low voltage added on the SDA,SCL pins. The VOL_9306 =VIN_L + VUP ( VUP is mainly determined by the I_pass, it always less than 0.35V.) (3) Low VREF application The PI6ULS5V9306 can support very low Vref1 application in theory ,but we recommend not lower than 0.9V.Because when VREF1 is less than 1.8V, the VOL of REF1 side is a concern in system . For example, in figure 6, if VREF1=0.9V ,VDPU=3.3V he VIL of the REF1 side I2C master is normally 0.3*VREF1 =0.25V, but the VOL of REF2 side can up to 0.1*VDPU=0.36V sometimes. The system designer must make sure this situation doesn’t happen. A limit for the V OL of REF2 side devices is required then. 2015-08-0006 PT0451-5 7 8/18/15 PI6ULS5V9306 Dual bidirectional I2C-bus and SMBus voltage-level translator ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| The bellow table shows the requirement for VOL of VREF2 side devices when using PI6ULS5V9306 (Requirement for VOL_DEVICE in figure 6) The VOL requirement of VREF2 side external devices (Temp=25ºC, Assume the VIL of VREF1 side devices is 0.3*VREF1) ≤3mA 10mA 15mA 0.9V ≤0.15V ≤0.1V Not Recommended 1.2V ≤0.2V ≤0.15V Not Recommended 1.5V ≤0.3V ≤0.25V ≤0.2V 1.8V ≤0.4V ≤0.35V ≤0.3V I_pass VREF1 Pull-up resistors and minimum values Sizing the pull-up resistor on an open-drain bus is specific to the individual application and is dependent on the following driver characteristics: The driver sink current The VOL of driver The VOL of the PI6ULS5V9306 The VIL of the driver Frequency of operation The following tables can be used to estimate the pull-up resistor value in different use cases so that the minimum resistance for the pull-up resistor can be found. Tables in bellow contain suggested minimum values of pull-up resistors for the PI6UILS5V9306 with typical voltage translation levels and drive currents. The calculated values assume that both drive currents are the same. VOL = VIL = 0.1*VCC and accounts for a 5 % VCC tolerance of the supplies, 1 % resistor values. It should be noted that the resistor chosen in the final application should be equal to or larger than the values shown in the tablew to ensure that the pass voltage is less than 10 % of the VCC voltage, and the external driver should be able to sink the total current from both pull-up resistors. Pull-up resistor minimum values, 3 mA driver sink current for PI6ULS5V9306 A Side 0.9V 1.5V RPU(A) = 845Ω RPU(B) = 845Ω 1.8V RPU(A) = 976Ω RPU(B) = 976Ω RPU(A) = 1.02kΩ RPU(B) = 1.02kΩ 1.2V 1.5V 1.8V B side 2.5V RPU(A) = none RPU(B) = 887Ω Or both 1.2kΩ RPU(A) = none RPU(B) = 887Ω Or both 1.3kΩ RPU(A) = none RPU(B) = 866Ω Or both 1.38kΩ RPU(A) = 1.47kΩ RPU(B) = 1.47kΩ 2.5V 3.3V 2015-08-0006 3.3V RPU(A) = none RPU(B) = 1.18kΩ Or both 1.5kΩ RPU(A) = none RPU(B) = 1.18kΩ Or both 1.5kΩ RPU(A) = none RPU(B) = 1.18kΩ Or both 1.5kΩ RPU(A) = none RPU(B) = 1.15kΩ Or both 1.5kΩ RPU(A) = 1.96kΩ RPU(B) = 1.96kΩ 5.0V RPU(A) = none RPU(B) = 1.82kΩ Or both 2.15kΩ RPU(A) = none RPU(B) = 1.82kΩ Or both 2.25kΩ RPU(A) = none RPU(B) = 1.78kΩ Or both 2.31kΩ RPU(A) = none RPU(B) = 1.78kΩ Or both 2.42kΩ RPU(A) = none RPU(B) = 1.78kΩ Or both 2.67kΩ RPU(A) = none RPU(B) = 1.74kΩ Or both 2.95kΩ PT0451-5 8 8/18/15 PI6ULS5V9306 Dual bidirectional I2C-bus and SMBus voltage-level translator ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Pull-up resistor minimum values, 10 mA driver sink current for PI6ULS5V9306 A Side B side 1.5V RPU(A) = 255Ω RPU(B) = 255Ω 0.9V 1.8V RPU(A) = 287Ω RPU(B) = 287Ω RPU(A) = 309Ω RPU(B) = 309Ω 1.2V 1.5V 1.8V 2.5V RPU(A) = none RPU(B) = 267Ω Or both 363Ω RPU(A) = none RPU(B) = 267Ω Or both 395Ω RPU(A) = none RPU(B) = 261Ω Or both 427Ω RPU(A) = 442Ω RPU(B) = 442Ω 2.5V 3.3V RPU(A) = none RPU(B) = 357Ω Or both 449Ω RPU(A) = none RPU(B) = 357Ω Or both 481Ω RPU(A) = none RPU(B) = 348Ω Or both 506Ω RPU(A) = none RPU(B) = 348Ω Or both 538Ω RPU(A) = 590Ω RPU(B) = 590Ω 3.3V 5.0V RPU(A) = none RPU(B) = 549Ω Or both 648Ω RPU(A) = none RPU(B) = 549Ω Or both 681Ω RPU(A) = none RPU(B) = 536Ω Or both 697Ω RPU(A) = none RPU(B) = 536Ω Or both 729Ω RPU(A) = none RPU(B) = 521Ω Or both 782Ω RPU(A) = none RPU(B) = 521Ω Or both 865Ω Pull-up resistor minimum values, 15 mA driver sink current for PI6ULS5V9306 A Side 0.9V 1.5V RPU(A) = 169Ω RPU(B) = 169Ω 1.8V RPU(A) = 191Ω RPU(B) = 191Ω RPU(A) = 205Ω RPU(B) = 205Ω 1.2V 1.5V 1.8V B side 2.5V RPU(A) = none RPU(B) = 178Ω Or both 242Ω RPU(A) = none RPU(B) = 178Ω Or both 263Ω RPU(A) = none RPU(B) = 174Ω Or both 278Ω RPU(A) = 294Ω RPU(B) = 294Ω 2.5V 3.3V 2015-08-0006 3.3V RPU(A) = none RPU(B) = 237Ω Or both 302Ω RPU(A) = none RPU(B) = 237Ω Or both 323Ω RPU(A) = none RPU(B) = 232Ω Or both 337Ω RPU(A) = none RPU(B) = 232Ω Or both 359Ω RPU(A) = 392Ω RPU(B) = 392Ω 5.0V RPU(A) = none RPU(B) = 365Ω Or both 431Ω RPU(A) = none RPU(B) = 365Ω Or both 453Ω RPU(A) = none RPU(B) = 464Ω Or both 697Ω RPU(A) = none RPU(B) = 486Ω Or both 729Ω RPU(A) = none RPU(B) = 536Ω Or both 782Ω RPU(A) = none RPU(B) = 348Ω Or both 578Ω PT0451-5 9 8/18/15 PI6ULS5V9306 Dual bidirectional I2C-bus and SMBus voltage-level translator ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Max Frequency Application The maximum frequency is limited by the minimum pulse width LOW and HIGH as well as rise time and fall time. The rise and fall times are dependent upon translation voltages, the drive strength, the total node capacitance (CL) and the pullup resistors (RPU) that are present on the bus. The node capacitance is the addition of the PCB trace capacitance and the device capacitance that exists on the bus. Because of the dependency of the external components, PCB layout and the different device operating states the calculation of rise and fall times is complex and has several inflection points along the curve. The main component of the rise and fall times is the RC time constant of the bus line when the device is in its two primary operating states: when device is in the ON state and it is low-impedance, the other is when the device is OFF isolating the A-side from the B-side. There are some basic guidelines to follow that will help maximize the performance of the device: • Keep trace length to a minimum by placing the PI6ULS5V9306 close to the processor. • The signal round trip time on trace should be shorter than the rise or fall time of signal to reduce reflections. • The faster the edge of the signal, the higher the chance for ringing. • The higher drive strength controlled by the pull-up resistor (up to 15 mA), the higher the frequency the device can use. The system designer must design the pull-up resistor value based on external current drive strength and limit the node capacitance (minimize the wire, stub, connector and trace length) to get the desired operation frequency result. 2015-08-0006 PT0451-5 10 8/18/15 PI6ULS5V9306 Dual bidirectional I2C-bus and SMBus voltage-level translator ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Mechanical Information TDFN2x3-8(ZE) PKG. DIMENSIONS(MM) SYMBOL MIN. MAX A 0.70 0.80 A1 0.00 0.50 0.20REF A3 D 1.92 2.08 E 2.92 3.07 D1 1.40 1.60 E1 1.40 1.60 0.20MIN k b 0.20 0.30 e 0.50TYP L 0.22 0.38 Note: Ref: JEDEC MO-229 2015-08-0006 PT0451-5 11 8/18/15 PI6ULS5V9306 Dual bidirectional I2C-bus and SMBus voltage-level translator ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| Recommended Land pattern for TDFN2x3-8L Note: All linear dimensions are in millimeters 2015-08-0006 PT0451-5 12 8/18/15 PI6ULS5V9306 Dual bidirectional I2C-bus and SMBus voltage-level translator ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| MSOP-8(U) 2015-08-0006 PT0451-5 13 8/18/15 PI6ULS5V9306 Dual bidirectional I2C-bus and SMBus voltage-level translator ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| SOIC-8(W) Ordering Information Part No. Package Code Package PI6ULS5V9306ZEEX ZE Lead free and Green TDFN2x3-8L,Tape & Reel PI6ULS5V9306UE U Lead free and Green MSOP-8L PI6ULS5V9306UEX U Lead free and Green MSOP-8L,Tape & Reel PI6ULS5V9306WE W 8-Pin,150 mil Wide SOIC PI6ULS5V9306WEX W 8-Pin,150 mil Wide SOIC, Tape & Reel Note: E = Pb-free and Green Adding X Suffix= Tape/Reel Pericom Semiconductor Corporation 1-800-435-2336 www.pericom.com Pericom reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. Pericom does not assume any responsibility for use of any circuitry described other than the circuitry embodied in Pericom product. The company makes no representations that circuitry described herein is free from patent infringement or other rights, of Pericom. 2015-08-0006 PT0451-5 14 8/18/15