Preliminary Datasheet RJK0855DPB 80V, 30A, 11 m max. Silicon N Channel Power MOS FET Power Switching R07DS1056EJ0200 (Previous: REJ03G1884-0100) Rev.2.00 Apr 11, 2013 Features High speed switching Low drive current Low on-resistance RDS(on) = 8.2 m typ. (at VGS = 10 V) Pb-free Halogen-free High density mounting Outline RENESAS Package code: PTZZ0005DA-A (Package name: LFPAK) 5 D 5 1, 2, 3 4 5 4 G 3 12 4 Source Gate Drain S S S 1 2 3 Absolute Maximum Ratings (Ta = 25°C) Item Drain to source voltage Gate to source voltage Drain current Drain peak current Body-drain diode reverse drain current Avalanche current Avalanche energy Channel dissipation Channel to Case Thermal Resistance Channel temperature Storage temperature Symbol VDSS VGSS ID ID(pulse)Note1 Ratings 80 20 30 120 Unit V V A A IDR IAP Note 2 EAS Note 2 Pch Note3 ch-C Tch Tstg 30 30 12 60 2.08 150 –55 to +150 A A mJ W C/W C C Notes: 1. PW 10 s, duty cycle 1% 2. Value at L=10uH, Tch = 25C, Rg 50 3. Tc = 25C R07DS1056EJ0200 Rev.2.00 Apr 11, 2013 Page 1 of 6 RJK0855DPB Preliminary Electrical Characteristics (Ta = 25°C) Item Drain to source breakdown voltage Gate to source leak current Zero gate voltage drain current Gate to source cutoff voltage Static drain to source on state resistance Forward transfer admittance Input capacitance Output capacitance Reverse transfer capacitance Gate Resistance Total gate charge Gate to source charge Gate to drain charge Turn-on delay time Rise time Turn-off delay time Fall time Symbol V(BR)DSS IGSS IDSS VGS(off) RDS(on) |yfs| Ciss Coss Crss Rg Qg Qgs Qgd td(on) tr td(off) tf Min 80 — — 2.0 — — — — — — — — — — — — — Typ — — — — 8.2 42 2550 500 130 0.5 35 11 6.5 14 6.4 34 8.0 Max — 0.1 1 4.0 11 — — — — — — — — — — — — Unit V A A V m S pF pF pF nC nC nC ns ns ns ns Body–drain diode forward voltage Body–drain diode reverse recovery time VDF trr — — 0.8 44 1.1 — V ns Test Conditions ID = 10 mA, VGS = 0 V VGS = 20 V, VDS = 0 V VDS = 80 V, VGS = 0 V VDS = 10 V, ID = 1 mA ID = 15 A, VGS = 10 V Note4 ID = 15 A, VDS = 10 V Note4 VDS = 10 V, VGS = 0 V, f = 1 MHz VDD = 25 V, VGS = 10 V, ID = 30 A VGS = 10 V, ID = 15 A, VDD 30 V, RL = 2 , Rg = 4.7 IF = 30 A, VGS = 0 V Note4 IF = 30 A, VGS = 0 V diF/ dt = 100 A/ s Notes: 4. Pulse test R07DS1056EJ0200 Rev.2.00 Apr 11, 2013 Page 2 of 6 RJK0855DPB Preliminary Main Characteristics Maximum Safe Operation Area Power vs. Temperature Derating 1000 Drain Current ID (A) Channel Dissipation Pch (W) 80 60 40 20 0 50 100 150 100 10 1 s 1 Operation in PW = 10 ms this area is limited by RDS(on) 0.1 DC Operation 0.01 0.1 200 m 1 10 100 Case Temperature Tc (°C) Drain to Source Voltage VDS (V) Typical Output Characteristics Typical Transfer Characteristics 50 50 Pulse Test 4.8 V 10 V VDS = 10 V Pulse Test 40 4.4 V 30 20 4.2 V 10 4.0 V Drain Current ID (A) 4.6 V Drain Current ID (A) Tc = 25°C 1 shot Pulse 40 30 20 Tc = 75°C 25°C 10 –25°C VGS = 3.8 V Drain to Source Saturation Voltage VDS (on) (mV) 0 2 4 6 8 10 0 1 2 3 5 4 Drain to Source Voltage VDS (V) Gate to Source Voltage VGS (V) Drain to Source Saturation Voltage vs. Gate to Source Voltage Static Drain to Source on State Resistance vs. Drain Current 400 100 Pulse Test Pulse Test 320 240 10 VGS = 10 V ID = 20 A 160 10 A 80 5A 0 4 8 12 16 20 Gate to Source Voltage VGS (V) R07DS1056EJ0200 Rev.2.00 Apr 11, 2013 1 1 10 100 1000 Drain Current ID (A) Page 3 of 6 RJK0855DPB Preliminary Static Drain to Source on State Resistance vs. Temperature 25 Typical Capacitance vs. Drain to Source Voltage 10000 Pulse Test ID = 15 A Capacitance C (pF) 20 15 VGS = 10 V 10 5 Ciss 1000 Coss 100 Crss VGS = 0 V f = 1 MHz 25 50 75 40 60 80 Drain to Source Voltage V DS (V) Dynamic Input Characteristics Reverse Drain Current vs. Source to Drain Voltage 20 80 16 VGS VDD = 50 V 25 V 10 V VDS 12 40 8 VDD = 50 V 25 V 10 V 20 4 0 0 20 Case Temperature Tc ( °C) ID = 30 A 60 0 100 125 150 10 20 30 0 50 40 50 Reverse Drain Current IDR (A) 100 10 0 Gate to Source Voltage V GS (V) Drain to Source Voltage V DS (V) 0 –25 Pulse Test 10 V 40 30 20 VGS = 0 V 10 0 0.4 0.8 1.2 1.6 2.0 Source to Drain Voltage V SD (V) Gate Charge Qg (nC) Maximum Avalanche Energy vs. Channel Temperature Derating Avalanche Energy EAS (mJ) 15 12 9 6 3 0 25 50 75 100 125 150 Channel Temperature Tch ( °C) R07DS1056EJ0200 Rev.2.00 Apr 11, 2013 Page 4 of 6 RJK0855DPB Preliminary Normalized Transient Thermal Impedance vs. Pulse Width 3 Tc = 25°C 1 D=1 0.5 0.3 0.2 0.1 0.1 0.05 0.03 .02 0 D= PDM se ul p 1 0.0 hot s 1 PW T PW T 0.01 1m 10 m 100 m 1 10 Pulse Width PW (s) Avalanche Test Circuit Avalanche Waveform EAS = L VDS Monitor 1 L • IAP2 • 2 VDSS VDSS – VDD IAP Monitor V(BR)DSS IAP Rg VDS VDD D. U. T ID Vin 15 V 0 VDD Switching Time Test Circuit Switching Time Waveform Vout Monitor Vin Monitor 90% D.U.T. Rg RL Vin Vout Vin 10 V 10% 10% VDS = 30 V 90% td(on) R07DS1056EJ0200 Rev.2.00 Apr 11, 2013 10% tr 90% td(off) tf Page 5 of 6 RJK0855DPB Preliminary Package Dimensions JEITA Package Code SC-100 Previous Code LFPAKV RENESAS Code PTZZ0005DA-A 4.9 5.3 Max 4.0 ± 0.2 MASS[Typ.] 0.080g +0.05 4.2 6.1 –0.3 +0.1 3.95 5 4 +0.05 0.20 –0.03 0° – 8° +0.25 1 1.1 Max +0.03 0.07 –0.04 3.3 1.0 0.25 –0.03 Unit: mm 0.6 –0.20 1.3 Max Package Name LFPAK 0.75 Max 0.10 1.27 0.40 ± 0.06 0.25 M (Ni/Pd/Au plating) Ordering Information Part No. RJK0855DPB-00-J5 Quantity 2500 pcs R07DS1056EJ0200 Rev.2.00 Apr 11, 2013 Shipping Container Taping Page 6 of 6 Notice 1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. 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