PreliminaryData Sheet μPD5753T7G SiGe/CMOS Integrated Circuit 4 × 2 IF Switch Matrix with Tone/Voltage Controller R09DS0014EJ0100 Rev.1.00 Feb 22, 2011 FEATURES • 4 independent IF channels, integral switching to channel input to either channel output • 4 × 2 switch matrix with integrated switch control - Tone/Voltage - Switch’s Enable/Disable function is linked with POLA input voltage level • Switch’s Enable condition : VPOLA > 9.5 V • Frequency range : f = 250 MHz to 2150 MHz • High isolation : ISLD/U = 33 dB TYP. @Worst mode • Insertion loss : LINS = 7 dB TYP. @ ZS = ZL = 50 Ω • Insertion loss flatness : ΔLINS = 1.0 dB TYP. • 20-pin 4 × 4 mm square micro lead package ( 20-pin plastic QFN (0.5 mm pitch)) APPLICATIONS • DBS IF switching • Multiswitch, Switch box • 4 × 2 switching application for microwave signal ORDERING INFORMATION Part Number μPD5753T7G-E1 Order Number Package Marking Supplying Form μPD5753T7G-E1-A 20-pin plastic QFN D5753 • Embossed tape 12 mm wide (0.5 mm pitch) • Pin 6 to 10 face the perforation side of the tape (Pb-Free) • Qty 5 kpcs/reel • Dry packing specification (MSL 3 Equivalent) Remark To order evaluation samples, please contact your nearby sales office. Part number for sample order: μPD5753T7G CAUTION Observe precautions when handling because these devices are sensitive to electrostatic discharge. R09DS0014EJ0100 Rev.1.00 Feb 22, 2011 Page 1 of 13 μPD5753T7G ABSOLUTE MAXIMUM RATINGS (TA = +25°C, unless otherwise specified) Parameter Symbol Ratings Unit Supply Voltage Logic mode Control Voltage (MO and M1) Note Power Dissipation Storage Temperature Operating Ambient Temperature Input Power VDD VMO, VM1 +4.0 +4.0 V V PD Tstg TA Pin VPOLA 325 −55 to +125 −40 to +85 +15 +25 mW °C °C dBm V VTONE 1 Vp-p POLA Control Input Voltage (POLA1 and POLA2) TONE Signal Input Voltage Note: Mounted on double-sided copper-clad 50 × 50 × 0.51 mm laminates PWB, TA = +85°C RECOMMENDED OPERATING RANGE (TA = +25°C, unless otherwise specified) Parameter Supply Voltage Operating Ambient Temperature POLA Control Input Voltage TONE Signal Frequency TONE Signal Input Voltage Symbol VDD TA VPOLA MIN. +3.0 −40 0 TYP. +3.3 +25 − MAX. +3.6 +85 21 Unit V °C V fTONE VTONE 18 0.4 22 0.6 26 0.8 kHz Vp-p ELECTRICAL CHARACTERISTICS (TA = +25°C, VDD = +3.3 V, ZS = ZL = 50 Ω for each port, Worst mode, unless otherwise specified) Parameter Supply Current Symbol IDD Insertion Loss 1 Insertion Loss 2 Isolation D/U Ratio 2 Note Output Return Loss 1 Output Return Loss 2 LINS1 LINS2 ISLD/U2 RLout1 RLout2 POLA Control Threshold Voltage, Channel Selection Vth_POLA TONE Signal Threshold Voltage, Channel Selection Vth_TONE Note: Test Conditions Non–RF, Non control Signal/Voltage Pin = 0 dBm, f = 0.95 GHz Pin = 0 dBm, f = 2.15 GHz Pin = 0 dBm, f = 2.15 GHz Pin = 0 dBm, f = 0.95 GHz Pin = 0 dBm, f = 2.15 GHz OFF to ON fTONE = 22 kHz, Duty Cycle = 50%, pulse wave, OFF to ON MIN. TYP. MAX. Unit − 1.9 3.0 mA − − 28 15 10 14 6.5 7.5 33 25 13 14.75 8.5 9.5 − − − 15.5 dB dB dB dB dB V 0.1 0.15 0.35 Vp-p Isolation D/U (Desire/Un-desire) ratio = ⎪(Signal Leakage (off-state)) − (Insertion loss (on-state))⎪ at Worst mode R09DS0014EJ0100 Rev.1.00 Feb 22, 2011 Page 2 of 13 μPD5753T7G STANDARD CHARACTERISTICS FOR REFERENCE (TA = +25°C, VDD = +3.3 V, ZS = ZL = 50 Ω for each port, Worst mode, unless otherwise specified) Parameter Insertion Loss Flatness Isolation D/U Ratio 1 Note Input Return Loss 1 Input Return Loss 2 POLA Control Current POLA Switching Time TONE Switching Time Note: Symbol ΔLINS ISLD/U1 RLin1 RLin2 IPOLA TPOLA TTONE Test Conditions |LINS1-LINS2| Pin = 0 dBm, f = 0.95 GHz Pin = 0 dBm, f = 0.95 GHz Pin = 0 dBm, f = 2.15 GHz VPOLA = 21 V VPOLA = 18 V, OFF to ON fTONE = 22 kHz, Duty Cycle = 50%, pulse wave, VTONE = 600 mVp-p, OFF to ON Reference Value 1.0 40 20 14 230 0.75 220 Unit dB dB dB dB μA μs μs Isolation D/U (Desire/Un-desire) ratio = ⎪(Signal Leakage (off-state)) − (Insertion loss (on-state))⎪ at Worst mode R09DS0014EJ0100 Rev.1.00 Feb 22, 2011 Page 3 of 13 μPD5753T7G PIN CONNECTIONS (Top View) (Bottom View) Pin 1 Identifier 5 4 3 2 1 1 2 3 4 5 6 20 20 6 7 19 19 7 18 18 17 17 9 16 16 10 D5753 8 9 10 11 12 13 14 15 GND 8 15 14 13 12 11 Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name 1 2 3 4 5 TONE1 POLA1 GND IN-A GND 6 7 8 9 10 IN-B GND GND GND IN-D 11 12 13 14 15 GND IN-C GND POLA2 TONE2 16 17 18 19 20 OUT2 M1 VDD M0 OUT1 Remark Heat Sink (Bottom side) : GND R09DS0014EJ0100 Rev.1.00 Feb 22, 2011 Page 4 of 13 μPD5753T7G TRUTH TABLE SWITCHING CONTROL OF OUT1 SIGNAL PATH Logic Pattern Select M0 0 1 0 1 M1 0 1 1 0 CONTROL PINS OUT1 for OUT1 SWITCHING CONTROL OF OUT2 SIGNAL PATH CONTROL PINS Logic Pattern Select M0 OUT2 for OUT2 POLA1 TONE1 Output Signal POLA2 TONE2 Output Signal No Voltage 22 kHz None No Voltage 22 kHz None No Voltage 0 None No Voltage 0 None Low 22 kHz IN-C Low 22 kHz IN-C Low 0 IN-D Low 0 IN-D High 0 IN-B High 0 IN-B High 22 kHz IN-A High 22 kHz IN-A No Voltage 22 kHz None No Voltage 22 kHz None No Voltage 0 None No Voltage 0 None Low 22 kHz IN-A Low 22 kHz IN-A 0 1 M1 0 1 Low 0 IN-B Low 0 IN-B High 0 IN-D High 0 IN-D High 22 kHz IN-C High 22 kHz IN-C No Voltage 22 kHz None No Voltage 22 kHz None No Voltage 0 None No Voltage 0 None Low 22 kHz IN-D Low 22 kHz IN-D Low 0 IN-C High 0 IN-B 0 1 Low 0 IN-C High 0 IN-B High 22 kHz IN-A High 22 kHz IN-A No Voltage 22 kHz None No Voltage 22 kHz None No Voltage 0 None No Voltage 0 None Low 22 kHz IN-B IN-B Low 0 IN-A High 0 High 22 kHz Low 22 kHz Low 0 IN-A IN-D High 0 IN-D IN-C High 22 kHz IN-C 1 0 Remarks M0, M1 : “0“ : 0 V dc (Connected to GND line) “1“ : VDD dc (Connected to VDD line) VDD = + 3.3 V dc POLA1, 2 : “Low” : 9.5 V to 14 V dc “High” : 15.5 V to 19 V dc “No Voltage” : 0 V dc (< 5 V dc) or Open Switch’s Enable/Disable function is linked with POLA input voltage level Switch’s Enable condition : VPOLA > 9.5 V R09DS0014EJ0100 Rev.1.00 Feb 22, 2011 Page 5 of 13 μPD5753T7G FUNCTIONAL DIAGRAM TONE1 POLA1 GND IN-A 5 GND (Top View) 1 20 4 × 2 Switch Matrix IN-B GND GND GND 4 : 16 DECODER 6 IN-D OUT1 Enable1 M0 Switch Controller VDD M1 Enable2 OUT2 16 R09DS0014EJ0100 Rev.1.00 Feb 22, 2011 TONE2 POLA2 GND IN-C 11 GND 10 15 Page 6 of 13 μPD5753T7G EVALUATION CIRCUIT 330 pF Note R = 0 kΩ POLA1 POLA control = 13 V/18 V RF input A TONE1 TONE control = 0/22 kHz, 0.6 Vp-p, pluse 10 000 pF (10 nF) 100 pF 100 pF 20 4 × 2 Switch Matrix IN-B GND GND RF input D 100 pF OUT1 Output 1 1 6 GND 4 : 16 DECODER RF input B 100 pF GND 5 GND IN-A IN-D Logic mode control = 0/1 (0 V dc / VDD dc) = Connected to GND line/VDD Line M0 Enable1 VDD VDD = +3.3 V Switch Controller Enable2 16 GND 11 RF input C GND 10 1 000 pF M1 Logic mode control = 0/1 (0 V dc/VDD dc) = Connected to GND line/VDD Line 15 IN-C 100 pF 100 pF OUT2 Output 2 10 000 pF (10 nF) TONE2 TONE control = 0/22 kHz, 0.6 Vp-p, pluse Note R = 0 kΩ POLA2 POLA control = 13 V/18 V 330 pF Note: R = 0 kΩ (at POLA control = 13 V/18 V) = 5.6 kΩ (at POLA control = 14 V/18 V) Remarks Heat Sink (Bottom Side): GND ZS = ZL = 50 Ω Switch’s Enable/Disable function is linked with POLA input voltage level Switch’s Enable condition : VPOLA > 9.5 V The application circuits and their parameters are for reference only and are not intended for use in actual design-ins. R09DS0014EJ0100 Rev.1.00 Feb 22, 2011 Page 7 of 13 μPD5753T7G TYPICAL CHARACTERISTICS (TA = +25°C, VDD = +3.3 V, Pin = 0 dBm, ZS = ZL = 50 Ω for each port, unless otherwise specified) INSERTION LOSS vs. FREQUENCY (IN-x - OUT2) –5.0 –5.0 –5.5 –5.5 –6.0 –6.0 Insertion Loss LINS (dB) Insertion Loss LINS (dB) INSERTION LOSS vs. FREQUENCY (IN-x - OUT1) –6.5 –7.0 –7.5 –8.0 –8.5 –9.0 –6.5 –7.0 –7.5 –8.0 –8.5 –9.0 –9.5 –10.0 0.0 1.0 1.5 2.0 2.5 0.5 1.0 1.5 2.0 2.5 Frequency f (GHz) Frequency f (GHz) ISOLATION D/U RATIO vs. FREQUENCY (IN-A - OUT1) ISOLATION D/U RATIO vs. FREQUENCY (IN-B - OUT1) 0.0 –10.0 –10.0 Isolation D/U Ratio ISLD/U (dB) 0.0 –20.0 –30.0 –40.0 –50.0 –60.0 –70.0 –80.0 –90.0 0.0 Isolation D/U Ratio ISLD/U (dB) 0.5 0.5 1.0 1.5 2.0 –20.0 –30.0 –40.0 –50.0 –60.0 –70.0 –80.0 –90.0 0.0 2.5 0.5 1.0 1.5 2.0 2.5 Frequency f (GHz) Frequency f (GHz) ISOLATION D/U RATIO vs. FREQUENCY (IN-C - OUT1) ISOLATION D/U RATIO vs. FREQUENCY (IN-D - OUT1) 0.0 0.0 –10.0 –10.0 Isolation D/U Ratio ISLD/U (dB) Isolation D/U Ratio ISLD/U (dB) –9.5 –10.0 0.0 –20.0 –30.0 –40.0 –50.0 –60.0 –70.0 –80.0 –90.0 0.0 0.5 1.0 1.5 2.0 2.5 Frequency f (GHz) –20.0 –30.0 –40.0 –50.0 –60.0 –70.0 –80.0 –90.0 0.0 0.5 1.0 1.5 2.0 2.5 Frequency f (GHz) Remark The graphs indicate nominal characteristics. R09DS0014EJ0100 Rev.1.00 Feb 22, 2011 Page 8 of 13 μPD5753T7G 0.0 –10.0 –10.0 –20.0 –30.0 –40.0 –50.0 –60.0 –70.0 –80.0 0.5 1.0 1.5 2.0 –20.0 –30.0 –40.0 –50.0 –60.0 –70.0 –80.0 –90.0 0.0 2.5 0.5 1.0 1.5 2.0 2.5 Frequency f (GHz) Frequency f (GHz) ISOLATION D/U RATIO vs. FREQUENCY (IN-C - OUT2) ISOLATION D/U RATIO vs. FREQUENCY (IN-D - OUT2) 0.0 0.0 –10.0 –10.0 Isolation D/U Ratio ISLD/U (dB) Isolation D/U Ratio ISLD/U (dB) Isolation D/U Ratio ISLD/U (dB) 0.0 –90.0 0.0 –20.0 –30.0 –40.0 –50.0 –60.0 –70.0 –80.0 –90.0 0.0 Output Return Loss RLout (dB) ISOLATION D/U RATIO vs. FREQUENCY (IN-B - OUT2) 0.5 1.0 1.5 2.0 –20.0 –30.0 –40.0 –50.0 –60.0 –70.0 –80.0 –90.0 0.0 2.5 0.5 1.0 1.5 2.0 2.5 Frequency f (GHz) Frequency f (GHz) OUTPUT RETURN LOSS vs. FREQUENCY (IN-x - OUT1) OUTPUT RETURN LOSS vs. FREQUENCY (IN-x - OUT2) 0.0 0.0 Output Return Loss RLout (dB) Isolation D/U Ratio ISLD/U (dB) ISOLATION D/U RATIO vs. FREQUENCY (IN-A - OUT2) –10.0 –20.0 –30.0 –40.0 –50.0 –60.0 0.0 0.5 1.0 1.5 2.0 2.5 Frequency f (GHz) –10.0 –20.0 –30.0 –40.0 –50.0 –60.0 0.0 0.5 1.0 1.5 2.0 2.5 Frequency f (GHz) Remark The graphs indicate nominal characteristics. R09DS0014EJ0100 Rev.1.00 Feb 22, 2011 Page 9 of 13 μPD5753T7G INPUT RETURN LOSS vs. FREQUENCY (IN-B - OUTx) 0.0 0.0 –5.0 –5.0 Input Return Loss RLin (dB) Input Return Loss RLin (dB) INPUT RETURN LOSS vs. FREQUENCY (IN-A - OUTx) –10.0 –15.0 –20.0 –25.0 –30.0 –35.0 –40.0 –45.0 –50.0 0.0 –15.0 –20.0 –25.0 –30.0 –35.0 –40.0 –45.0 0.5 1.0 1.5 2.0 –50.0 0.0 2.5 0.5 1.0 1.5 2.0 2.5 Frequency f (GHz) Frequency f (GHz) INPUT RETURN LOSS vs. FREQUENCY (IN-C - OUTx) INPUT RETURN LOSS vs. FREQUENCY (IN-D - OUTx) 0.0 0.0 –5.0 Input Return Loss RLin (dB) –5.0 Input Return Loss RLin (dB) –10.0 –10.0 –15.0 –20.0 –25.0 –30.0 –35.0 –40.0 –45.0 –50.0 0.0 –10.0 –15.0 –20.0 –25.0 –30.0 –35.0 –40.0 –45.0 0.5 1.0 1.5 2.0 2.5 Frequency f (GHz) –50.0 0.0 0.5 1.0 1.5 2.0 2.5 Frequency f (GHz) Remark The graphs indicate nominal characteristics. R09DS0014EJ0100 Rev.1.00 Feb 22, 2011 Page 10 of 13 μPD5753T7G MOUNTING PAD LAYOUT DIMENSIONS 20-PIN 4 × 4 mm SQUARE MICRO LEAD PACKAGE (20-PIN PLASTIC QFN (0.5 mm pitch)) (UNIT: mm) 2.15 1.65 0.5 1.35 1.35 1.35 2.15 1.65 2.15 1.65 1.35 2.15 1.65 20-0.2 Remark The mounting pad layout in this document is for reference only. R09DS0014EJ0100 Rev.1.00 Feb 22, 2011 Page 11 of 13 μPD5753T7G PACKAGE DIMENSIONS 20-PIN 4 × 4 mm SQUARE MICRO LEAD PACKAGE (20-PIN PLASTIC QFN (0.5 mm pitch)) (UNIT: mm) (Top View) (Side View) 0.57+0.03 –0.05 4±0.1 4±0.1 (Bottom View) 0.15 1.72 2.7±0.1 0.15 1.72 A A 0.2+0.07 –0.05 0.08 MIN. Pin 1 0.35±0.075 0.5±0.1 2.7±0.1 Remark A>0 R09DS0014EJ0100 Rev.1.00 Feb 22, 2011 Page 12 of 13 μPD5753T7G RECOMMENDED SOLDERING CONDITIONS This product should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact your nearby sales office. Soldering Method Infrared Reflow Partial Heating Soldering Conditions Peak temperature (package surface temperature) Time at peak temperature Time at temperature of 220°C or higher Preheating time at 120 to 180°C Maximum number of reflow processes Maximum chlorine content of rosin flux (% mass) : 260°C or below : 10 seconds or less : 60 seconds or less : 120±30 seconds : 3 times : 0.2%(Wt.) or below Peak temperature (package surface temperature) : 350°C or below Soldering time (per side of device) : 3 seconds or less Maximum chlorine content of rosin flux (% mass) : 0.2%(Wt.) or below Condition Symbol IR260 HS350 CAUTION Do not use different soldering methods together (except for partial heating). R09DS0014EJ0100 Rev.1.00 Feb 22, 2011 Page 13 of 13 μPD5753T7G Data Sheet Revision History Rev. 1.00 Date Page Feb 22, 2011 − Description Summary First edition issued All trademarks and registered trademarks are the property of their respective owners. C-1 Notice 1. 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