HD74HCT137 3-to-8-line Decoder/Demultiplexer with Address Latch REJ03D0658–0200 (Previous ADE-205-546) Rev.2.00 Mar 30, 2006 Description The HD74HCT137 implements a three-to-eight line decoder with latches on the three address inputs. When GL goes from low to high, the address present at the select inputs (A, B and C) is stored in the latches. As long as GL remains high no address changes will be recognized. Output enable controls, G1 and G2, control the state of the outputs independently of the select or latch-enable inputs. All of the outputs are high unless G1 is high and G2 is low. The HD74HCT137 is ideally suited for the implementation of glitch free decoders in stored-address applications in bus oriented systems. Features • • • • • • High Speed Operation: tpd (A, B, C to Y) = 16.5 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 V to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) Ordering Information Part Name HD74HCT137FPEL Package Type SOP-16 pin (JEITA) Package Code (Previous Code) PRSP0016DH-B (FP-16DAV) Package Abbreviation FP PRSP0016DG-A RP (FP-16DNV) Note: Please consult the sales office for the above package availability. HD74HCT137RPEL SOP-16 pin (JEDEC) Rev.2.00 Mar 30, 2006 page 1 of 7 Taping Abbreviation (Quantity) EL (2,000 pcs/reel) EL (2,500 pcs/reel) HD74HCT137 Function Table GL X X L L L L L L L L H H: L: X: Inputs Enable G1 G2 C X H X L X X H L L H L L H L L H L L H L H H L H H L H H L H H L X High level Low level Irrelevant Select B X X L L H H L L H H X Outputs A X X L H L H L H L H X Y0 H H L H H H H H H H Y1 Y2 Y3 Y4 Y5 Y6 H H H H H H H H H H H H H H H H H H L H H H H H H L H H H H H H L H H H H H H L H H H H H H L H H H H H H L H H H H H H Output Corresponding to stored address L; all Others. H Pin Arrangement 16 VCC A 1 A Y0 15 Y0 C Y1 14 Y1 GL 4 GL Y2 13 Y2 G2 5 G2 Y3 12 Y3 G1 6 G1 Y4 11 Y4 Y7 7 Y7 Y5 10 Y5 B 2 B C 3 Y6 9 Y6 GND 8 (Top view) Rev.2.00 Mar 30, 2006 page 2 of 7 Y7 H H H H H H H H H L HD74HCT137 Logic Diagram CK Y0 A CK CK CK Y1 B Y2 C Y3 CK Y4 CK GL Y5 Y6 Y7 G2 G1 Absolute Maximum Ratings Item Supply voltage range Input voltage Output voltage Output current DC current drain per VCC, GND DC input diode current DC output diode current Power dissipation per package Storage temperature Symbol VCC VIN VOUT IOUT ICC, IGND IIK IOK PT Tstg Rating –0.5 to +7.0 –0.5 to VCC + 0.5 –0.5 to VCC + 0.5 ±25 ±50 ±20 ±20 500 –65 to +150 Unit V V V mA mA mA mA mW °C Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. Recommended Operating Conditions Item Symbol Ratings Supply voltage VCC 4.5 to 5.5 Input / Output voltage VIN, VOUT 0 to VCC Operating temperature Ta –40 to 85 Input rise / fall time*1 tr, tf 0 to 500 Notes: 1. This item guarantees maximum limit when one input switches. Waveform: Refer to test circuit of switching characteristics. Rev.2.00 Mar 30, 2006 page 3 of 7 Unit V V °C ns Conditions VCC = 4.5 V HD74HCT137 Electrical Characteristics Item Symbol VCC (V) VIH VIL VOH 4.5 to 5.5 4.5 to 5.5 4.5 4.5 4.5 4.5 5.5 5.5 Input voltage Output voltage VOL Input current Iin Quiescent supply current ICC Ta = 25°C Min Typ Max 2.0 — — — — 0.8 4.4 — — 4.18 — — — — 0.1 — — 0.26 — — ±0.1 — — 4.0 Ta = –40 to+85°C Min Max 2.0 — — 0.8 4.4 — 4.13 — — 0.1 — 0.33 — ±1.0 — 40 Unit V V V V µA µA Test Conditions Vin = VIH or VIL IOH = –20 µA IOH = –4 mA Vin = VIH or VIL IOL = 20 µA IOL = 4 mA Vin = VCC or GND Vin = VCC or GND, Iout = 0 µA Switching Characteristics (CL = 50 pF, Input tr = tf = 6 ns) Item Symbol VCC (V) Propagation delay time Pulse width Setup time Hold time Output rise/fall time Input capacitance Ta = 25°C Ta = –40 to +85°C tPLH tPHL 4.5 4.5 Min — — Typ 14 22 Max 34 48 Min — — Max 43 60 tPLH tPHL 4.5 4.5 — — 11 23 26 39 — — tPLH tPHL 4.5 4.5 — — 13 17 30 39 tPLH tPHL 4.5 4.5 — — 16 23 tw tsu th 4.5 4.5 4.5 16 20 10 tTLH tTHL Cin 4.5 — Unit Test Conditions ns A, B or C to Y 33 49 ns G2 to Y — — 38 49 ns G1 to Y 35 50 — — 44 63 ns GL to Y 6 3 0 — — — 20 25 13 — — — ns ns ns — 5 15 — 19 ns — 5 10 — 10 pF Test Circuit VCC VCC Input Pulse Generator Zout = 50 Ω See Function Table Pulse Generator Zout = 50 Ω Output A Input B Y0 C CL = 50 pF GL G2 G1 Output Y7 Note : 1. CL includes probe and jig capacitance. Rev.2.00 Mar 30, 2006 page 4 of 7 CL = 50 pF HD74HCT137 Waveforms • Waveform – 1 6 ns 6 ns Input A,B,C 90% 90% 1.3 V 10% 10% VCC 90% 1.3 V 10% 90% 10% 1.3 V tW tW tPLH 0V tPHL 90% 1.3 V Output Y VOH 90% 1.3 V 10% 10% tTLH VOL tTHL Notes: 1. Input waveform: PRR ≤ 1 MHz, Zo = 50 Ω, tr ≤ 6 ns, tf ≤ 6 ns 2. The output are measured one at a time with one transition per measurement. • Waveform – 2 6 ns 6 ns G2 VCC 90% 1.3 V 90% 1.3 V 10% 10% 0V tPHL tPLH 90% 1.3 V 10% Output Y 90% 1.3 V 10% tTHL VOH VOL tTLH Notes: 1. Input waveform: PRR ≤ 1 MHz, Zo = 50 Ω, tr ≤ 6 ns, tf ≤ 6 ns 2. The output are measured one at a time with one transition per measurement. • Waveform – 3 6 ns 6 ns 90% 1.3 V G1 VCC 90% 1.3 V 10% 10% tPHL tPLH 90% Output Y 0V 1.3 V 10% tTHL 90% 1.3 V 10% VOH VOL tTLH Notes: 1. Input waveform: PRR ≤ 1 MHz, Zo = 50 Ω, tr ≤ 6 ns, tf ≤ 6 ns 2. The output are measured one at a time with one transition per measurement. Rev.2.00 Mar 30, 2006 page 5 of 7 HD74HCT137 • Waveform – 4 6 ns 6 ns VCC 90% 1.3 V 90% GL 1.3 V 10% 1.3 V 10% 0V tW tPHL tPLH 90% 1.3 V Output Y VOH 90% 1.3 V 10% 10% tTLH VOL tTHL Notes: 1. Input waveform: PRR ≤ 1 MHz, Zo = 50 Ω, tr ≤ 6 ns, tf ≤ 6 ns 2. The output are measured one at a time with one transition per measurement. • Waveform – 5 tW Input A,B,C VCC 1.3 V 1.3 V 0V tsu th VCC GL 1.3 V 0V Notes: 1. Input waveform: PRR ≤ 1 MHz, Zo = 50 Ω, tr ≤ 6 ns, tf ≤ 6 ns 2. The output are measured one at a time with one transition per measurement. Rev.2.00 Mar 30, 2006 page 6 of 7 HD74HCT137 Package Dimensions JEITA Package Code P-SOP16-3.95x9.9-1.27 RENESAS Code PRSP0016DG-A *1 Previous Code FP-16DNV MASS[Typ.] 0.15g D F 16 NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. 9 c *2 Index mark HE E bp Terminal cross section ( Ni/Pd/Au plating ) 1 Reference Dimension in Millimeters Symbol 8 *3 e Z bp x M A L1 A1 θ L y Detail F JEITA Package Code P-SOP16-5.5x10.06-1.27 RENESAS Code PRSP0016DH-B *1 Previous Code FP-16DAV D E A2 A1 A bp b1 c c1 θ HE e x y Z L L1 Min Nom Max 9.90 10.30 3.95 0.10 0.14 0.25 1.75 0.34 0.40 0.46 0.15 0.20 0.25 0° 8° 5.80 6.10 6.20 1.27 0.25 0.15 0.635 0.40 0.60 1.27 1.08 MASS[Typ.] 0.24g D F 16 NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. 9 c HE *2 E bp Index mark Terminal cross section ( Ni/Pd/Au plating ) 1 Z 8 e *3 bp x Reference Dimension in Millimeters Symbol M A L1 A1 θ y L Detail F Rev.2.00 Mar 30, 2006 page 7 of 7 D E A2 A1 A bp b1 c c1 θ HE e x y Z L L1 Min Nom Max 10.06 10.5 5.50 0.00 0.10 0.20 2.20 0.34 0.40 0.46 0.15 0.20 0.25 0° 8° 7.50 7.80 8.00 1.27 0.12 0.15 0.80 0.50 0.70 0.90 1.15 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. 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