TSM7N65 - Farnell

TSM7N65
650V N-Channel Power MOSFET
ITO-220
Pin Definition:
1. Gate
2. Drain
3. Source
PRODUCT SUMMARY
VDS (V)
RDS(on)(Ω)
650
ID (A)
1.2 @ VGS =10V
6.4
d
TO-220
General Description
Block Diagram
Features
Low RDS(ON) 1.2Ω (Max.)
Low gate charge typical @ 32nC (Typ.)
Low Crss typical @ 25pF (Typ.)
Fast Switching
Part No.
e co
Ordering Information
mm
●
●
●
●
en
de
The TSM7N65 N-Channel enhancement mode Power MOSFET is produced by planar stripe DMOS technology.
This advanced technology has been especially tailored to minimize on-state resistance, provide superior
switching performance, and withstand high energy pulse in the avalanche and commutation mode. These
devices are well suited for high efficiency switch mode power supply, power factor correction, electronic lamp
ballast based on half bridge.
Package
Packing
TO-220
ITO-220
50pcs / Tube
50pcs / Tube
tR
TSM7N65CZ C0
TSM7N65CI C0
N-Channel MOSFET
Absolute Maximum Rating (TA=25oC unless otherwise noted)
Parameter
No
Drain-Source Voltage
Gate-Source Voltage
Ta =25ºC
Continuous Drain Current
Ta =100ºC
Symbol
Limit
VDS
650
V
VGS
±30
V
6.4
A
3.8
A
ID
Unit
Pulsed Drain Current *
IDM
22
A
Single Pulse Avalanche Energy (Note 2)
EAS
216
mJ
Repetitive Avalanche Current (Note 1)
IAR
6
A
o
Total Power Dissipation @ TC = 25 C
TO-220
ITO-220
Operating Junction Temperature
PTOT
TJ
Storage Temperature Range
* Limited by maximum junction temperature
TSTG
1/9
125
30
150
-55 to +150
W
ºC
o
C
Version: D12
TSM7N65
650V N-Channel Power MOSFET
Thermal Performance
Parameter
Symbol
TO-220
Thermal Resistance - Junction to Case
RӨJA
Electrical Specifications (Ta = 25oC unless otherwise noted)
Typ
Max
Unit
BVDSS
650
--
--
V
RDS(ON)
--
1.0
1.2
Ω
VGS(TH)
2.0
--
4.0
V
--
--
1
--
--
50
IGSS
--
--
±10
uA
VDS = 8V, ID = 1A
gfs
--
3.7
--
S
IS = 6A, VGS = 0V
VSD
--
--
1.6
V
Qg
--
32
46
Qgs
--
6
--
Qgd
--
11
--
Ciss
--
905
--
Coss
--
115
--
Crss
--
25
--
Drain-Source On-State Resistance
VGS = 10V, ID = 3A
Gate Threshold Voltage
VDS = VGS, ID = 250uA
en
VGS = 0V, ID = 250uA
VDS = 650V, VGS = 0V
mm
IDSS
VDS = 650V, VGS = 0V,
TC=125ºC
Forward Transfer Conductance
Dynamic
VGS = ±20V, VDS = 0V
e co
Diode Forward Voltage
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
VDS = 300V, ID = 6A,
VGS = 10V
tR
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
C/W
Min
Drain-Source Breakdown Voltage
Gate Body Leakage
o
Symbol
Static
Zero Gate Voltage Drain Current
C/W
62.5
de
Conditions
o
4.2
d
Thermal Resistance - Junction to Ambient
Note: Surface mounted on FR4 board t ≤ 10sec
Unit
1.0
RӨJC
ITO-220
Parameter
Limit
VDS = 25V, VGS = 0V,
f = 1.0MHz
uA
nC
pF
No
Switching
Turn-On Delay Time
td(on)
--
14
--
Turn-On Rise Time
VGS = 10V, ID = 6A,
tr
--
14
--
Turn-Off Delay Time
VDD = 300V, RG = 25Ω
td(off)
--
47
--
tf
--
19
--
tfr
--
638
--
nS
--
4.8
--
uC
Turn-Off Fall Time
Reverse Recovery Time
VGS = 0V, IS = 6A,
dIF/dt = 100A/us
Reverse Recovery Charge
Qfr
Note:
1. Repetitive Rating: Pulse Width Limited by Maximum Junction Temperature
2. VDD = 50V, IAS=3.6A, L=30mH, VDS=500V
3. Pulse test: pulse width ≤300uS, duty cycle ≤2%
4. Essentially Independent of Operating Temperature
2/9
nS
Version: D12
TSM7N65
650V N-Channel Power MOSFET
Electrical Characteristics Curve (Ta = 25oC, unless otherwise noted)
Transfer Characteristics
mm
en
de
d
Output Characteristics
Gate Charge
No
tR
e co
On-Resistance vs. Drain Current
On-Resistance vs. Junction Temperature
Source-Drain Diode Forward Voltage
3/9
Version: D12
TSM7N65
650V N-Channel Power MOSFET
Electrical Characteristics Curve (Ta = 25oC, unless otherwise noted)
Threshold Voltage
mm
en
de
d
On-Resistance vs. Gate-Source Voltage
Maximum Safe Operating Area - ITO-220
tR
e co
Maximum Safe Operating Area - TO-220
No
Normalized Thermal Transient Impedance, Junction-to-Ambient
4/9
Version: D12
TSM7N65
650V N-Channel Power MOSFET
mm
en
de
d
Gate Charge Test Circuit & Waveform
tR
e co
Resistive Switching Test Circuit & Waveform
No
EAS Test Circuit & Waveform
5/9
Version: D12
TSM7N65
650V N-Channel Power MOSFET
No
tR
e co
mm
en
de
d
Diode Reverse Recovery Time Test Circuit & Waveform
6/9
Version: D12
TSM7N65
650V N-Channel Power MOSFET
Unit: Millimeters
tR
e co
mm
en
de
d
TO-220 Mechanical Drawing
Marking Diagram
No
Y = Year Code
M = Month Code
(A=Jan, B=Feb, C=Mar, D=Apl, E=May, F=Jun, G=Jul, H=Aug,
I=Sep, J=Oct, K=Nov, L=Dec)
L = Lot Code
7/9
Version: D12
TSM7N65
650V N-Channel Power MOSFET
Unit: Millimeters
tR
e co
mm
en
de
d
ITO-220 Mechanical Drawing
No
Marking Diagram
Y = Year Code
M = Month Code
(A=Jan, B=Feb, C=Mar, D=Apl, E=May, F=Jun, G=Jul, H=Aug,
I=Sep, J=Oct, K=Nov, L=Dec)
L = Lot Code
8/9
Version: D12
TSM7N65
No
tR
e co
mm
en
de
d
650V N-Channel Power MOSFET
Notice
Specifications of the products displayed herein are subject to change without notice. TSC or anyone on its behalf,
assumes no responsibility or liability for any errors or inaccuracies.
Information contained herein is intended to provide a product description only. No license, express or implied, to
any intellectual property rights is granted by this document. Except as provided in TSC’s terms and conditions of
sale for such products, TSC assumes no liability whatsoever, and disclaims any express or implied warranty,
relating to sale and/or use of TSC products including liability or warranties relating to fitness for a particular purpose,
merchantability, or infringement of any patent, copyright, or other intellectual property right.
The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications.
Customers using or selling these products for use in such applications do so at their own risk and agree to fully
indemnify TSC for any damages resulting from such improper use or sale.
9/9
Version: D12