Eon Silicon Solution Inc. Application Note EON EN25Q32B (Version: A) VS. SST SST25VF032B This Application Note may be revised by subsequent versions or modifications due to changes in technical specifications. 1 (Version: 03) ©2010 Eon Silicon Solution Inc. Rev. A, Issue Date: 2010/12/29 www.eonssi.com Eon Silicon Solution Inc. 1. INTRODUCTION The application note introduces how to implement a system design from SST flash SST25VF032B to Eon flash EN25Q32B. 2. GENERAL FUNCTION COMPARISON TABLE: 2.1. The following table highlights the major features of these two devices. Features EN25Q32B SST25VF032B Voltage Range Pin to Pin Compatible SPI Mode 2.7V ~ 3.6V 2.7V ~ 3.6V Yes Yes Mode 0 / Mode 3 104MHz (standard mode) SPI Frequency 80MHz @ dual & quad mode Uniform z 1024 sectors of 4Kbyte z Sector Architecture z 64 blocks of 64Kbyte z z Any sector or block can be z erased individually. Lockable OTP 512 Bytes Security Sector HOLD# Pin No Page Programming Yes Auto Address Increment (AAI) No Word Programming Block Erase No 32KBytes Minimum Endurance Cycle Package1. 100K Mode 0 / Mode 3 80MHz (standard mode) Uniform 1024 sectors of 4Kbyte 64 blocks of 64Kbyte Any sector or block can be erased individually. No Yes No Yes Yes 100K 8 pins SOP 200mil body width 8 pins SOP 200mil body width 8 contact VDFN (5x6mm) 8 pins WSON (5x6mm) 16 pins SOP 300mil body width z All Pb-free packages are 24 balls BGA (6x8mm) RoHS compliant z All Pb-free packages are RoHS compliant Note: 1. Please refer to the datasheet in detail. This Application Note may be revised by subsequent versions or modifications due to changes in technical specifications. 2 ©2010 Eon Silicon Solution Inc. Rev. A, Issue Date: 2010/12/29 www.eonssi.com Eon Silicon Solution Inc. 3. HARDWARE CONSIDERATIONS 3.1. ICC Comparison EN25Q32B SST25VF032B Max ( @ Single 104MHz) Max ( @ 80MHz) Read ICC3 25 25 mA Page Program (PP) ICC4 28 30 mA Sector Erase (SE) ICC6 25 30 mA Standby ICC1 20 20 μA Current Unit 3.2. Pins Description Pin Name CLK DI (DQ0) DO (DQ1) EN25Q32B Function Pin Name Serial Clock Input SCK Serial Data Input (Data Input SI Output 0) *1 Chip Enable Write Protect (Data Input WP# (DQ2) Output 2) *2 Not Connect (Data Input NC(DQ3) Output 3) *2 Vcc Supply Voltage (2.7-3.6V) Vss Ground NC No Connect Note: 1. 2. Serial Data Input CS# Serial Data Output (Flash busy status pin in AAI mode if SO is configured as a hardware RY/BY# pin) Chip Enable WP# Write Protect HOLD# Hold Input VDD Vss NC Supply Voltage (2.7-3.6V) Ground No Connect Serial Data Output (Data Input SO (RY/BY#) Output 1) *1 CS# SST25VF032B Function Serial Clock Input DQ0 and DQ1 are used for Dual and Quad instructions. DQ0 ~ DQ3 are used for Quad instructions. * Users must take care of the different pin definition! This Application Note may be revised by subsequent versions or modifications due to changes in technical specifications. 3 ©2010 Eon Silicon Solution Inc. Rev. A, Issue Date: 2010/12/29 www.eonssi.com Eon Silicon Solution Inc. 4. SOFTWARE CONSIDERATIONS 4.1. Manufacturer, Memory Type & Device Identification (M7~M0: manufacture ID, D15~ID0: memory type, ID7~ID0: memory density) comparison. 4.1.1. For EN25Q32B：MANUFACTURER/DEVICE ID TABLE OP Code (M7-M0) (ID15-ID0) ABh 4.1.2. (ID7-ID0) 15h 90h 1Ch 9Fh 1Ch 15h 3016h For SST25VF032B：MANUFACTURER/DEVICE ID TABLE This Application Note may be revised by subsequent versions or modifications due to changes in technical specifications. 4 ©2010 Eon Silicon Solution Inc. Rev. A, Issue Date: 2010/12/29 www.eonssi.com Eon Silicon Solution Inc. 4.2. Instruction Set Comparison 4.2.1. For EN25Q32B：Instruction Set Instruction Name Byte 1 Code EQIO 38h Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 n-Bytes RSTQIO(2) / Release Quad I/O or Fast Read Enhanced Mode FFh RSTEN 66h RST(1) 99h Write Enable Write Disable / Exit OTP mode Read Status Register Write Status Register 06h 04h 05h (S7-S0)(3) 01h S7-S0 continuous(4) Page Program Sector Erase / OTP erase Block Erase 02h A23-A16 A15-A8 A7-A0 20h A23-A16 A15-A8 A7-A0 D8h A23-A16 A15-A8 A7-A0 Chip Erase C7h/ 60h Deep Power-down Release from Deep Power-down, and read Device ID Release from Deep Power-down Manufacturer/ Device ID Read Identification Enter OTP mode B9h D7-D0 Next byte continuous (5) dummy dummy 90h dummy dummy 9Fh 3Ah (M7-M0) (ID15-ID8) dummy (ID7-ID0) 00h 01h (ID7-ID0) (M7-M0) (ID7-ID0) (7) ABh (ID7-ID0) (M7-M0) (6) Notes: 1. RST command only executed if RSTEN command is executed first. Any intervening command will disable Reset. 2. Device accepts eight-clocks command in Standard SPI mode, or two-clocks command in Quad SPI mode 3. Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis “( )” indicate data being read from the device on the DO pin. 4. The Status Register contents will repeat continuously until CS# terminates the instruction. 5. The Device ID will repeat continuously until CS# terminates the instruction. 6. The Manufacturer ID and Device ID bytes will repeat continuously until CS# terminates the instruction. 00h on Byte 4 starts with MID and alternate with DID, 01h on Byte 4 starts with DID and alternate with MID. 7. (M7-M0) : Manufacturer, (ID15-ID8) : Memory Type, (ID7-ID0) : Memory Capacity. This Application Note may be revised by subsequent versions or modifications due to changes in technical specifications. 5 ©2010 Eon Silicon Solution Inc. Rev. A, Issue Date: 2010/12/29 www.eonssi.com Eon Silicon Solution Inc. Instruction Set (Read Instruction) Instruction Name Byte 1 Code Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 n-Bytes Read Data Fast Read 03h A23-A16 A15-A8 A7-A0 (D7-D0) (Next byte) 0Bh A23-A16 A15-A8 A7-A0 dummy (D7-D0) 3Bh A23-A16 A15-A8 A7-A0 dummy (D7-D0, …) (1) BBh A23-A8(2) A7-A0, dummy (2) (D7-D0, …) (1) (dummy, D7-D0 ) (5) (D7-D0, …) (3) continuous (Next Byte) continuous (one byte per 4 clocks, continuous) (one byte per 4 clocks, continuous) (one byte per 2 clocks, continuous) Dual Output Read Fast Dual I/O Fast Read Quad I/O Fast Read EBh A23-A0, dummy (4) Notes: 1. Dual Output data DQ0 = (D6, D4, D2, D0) DQ1 = (D7, D5, D3, D1) 2. Dual Input Address DQ0 = A22, A20, A18, A16, A14, A12, A10, A8 ; A6, A4, A2, A0, dummy 6, dummy 4, dummy 2, dummy 0 DQ1 = A23, A21, A19, A17, A15, A13, A11, A9 ; A7, A5, A3, A1, dummy 7, dummy 5, dummy 3, dummy 1 3. Quad Data DQ0 = (D4, D0, …… ) DQ1 = (D5, D1, …… ) DQ2 = (D6, D2, …... ) DQ3 = (D7, D3, …... ) 4. Quad Input Address DQ0 = A20, A16, A12, A8, A4, A0, dummy 4, dummy 0 DQ1 = A21, A17, A13, A9, A5, A1, dummy 5, dummy 1 DQ2 = A22, A18, A14, A10, A6, A2, dummy 6, dummy 2 DQ3 = A23, A19, A15, A11, A7, A3, dummy 7, dummy 3 5. Quad I/O Fast Read Data DQ0 = ( dummy 12, dummy 8, dummy 4, dummy 0, D4, D0 ) DQ1 = ( dummy 13, dummy 9, dummy 5, dummy 1, D5, D1 ) DQ2 = ( dummy 14, dummy 10, dummy 6, dummy 2, D6, D2 ) DQ3 = ( dummy 15, dummy 11, dummy 7, dummy 3, D7, D3 ) This Application Note may be revised by subsequent versions or modifications due to changes in technical specifications. 6 ©2010 Eon Silicon Solution Inc. Rev. A, Issue Date: 2010/12/29 www.eonssi.com Eon Silicon Solution Inc. 4.2.2. For SST25VF032B：Instruction Set Note: 1. The major differences are pointed out by the blue arrows. Please refer to the datasheet in detail. 2. Users must modify the codes for EN25Q32B! This Application Note may be revised by subsequent versions or modifications due to changes in technical specifications. 7 ©2010 Eon Silicon Solution Inc. Rev. A, Issue Date: 2010/12/29 www.eonssi.com Eon Silicon Solution Inc. 4.3. Different Block Protection Area * The definitions of Block Protection Area are different! 4.3.1. For EN25Q32B： Protected Area Sizes Sector Organization Table Status Register Content BP3 Bit 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 BP2 Bit 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 4.3.2. BP1 Bit 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 BP0 Bit 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Memory Content Protect Areas Addresses None Block 0 to 62 Block 0 to 61 Block 0 to 59 Block 0 to 55 Block 0 to 47 Block 0 to 31 All None Block 63 to 1 Block 63 to 2 Block 63 to 4 Block 63 to 8 Block 63 to 16 Block 63 to 32 All None 000000h-3EFFFFh 000000h-3DFFFFh 000000h-3BFFFFh 000000h-37FFFFh 000000h-2FFFFFh 000000h-1FFFFFh 000000h-3FFFFFh None 3FFFFFh-010000h 3FFFFFh-020000h 3FFFFFh-040000h 3FFFFFh-080000h 3FFFFFh-100000h 3FFFFFh-200000h 000000h-3FFFFFh Density(KB) None 4032KB 3968KB 3840KB 3584KB 3072KB 2048KB 4096KB None 4032KB 3968KB 3840KB 3584KB 3072KB 2048KB 4096KB Portion None Lower 63/64 Lower 62/64 Lower 60/64 Lower 56/64 Lower 48/64 Lower 32/64 All None Upper 63/64 Upper 62/64 Upper 60/64 Upper 56/64 Upper 48/64 Upper 32/64 All For SST25VF032B： This Application Note may be revised by subsequent versions or modifications due to changes in technical specifications. 8 ©2010 Eon Silicon Solution Inc. Rev. A, Issue Date: 2010/12/29 www.eonssi.com Eon Silicon Solution Inc. 4.4. Different RDSR Bits Definition * The definitions of RDSR bits [S7:S6] are different! 4.4.1. For EN25Q32B： Status Register Bit Locations S7 SRP S6 OTP_LOCK Status Register Protect bit (note 1) 1 = status register write disable 1 = OTP sector is protected Non-volatile bit WPDIS (WP# disable) 1 = WP# disable 0 = WP# enable S5 S4 S3 S2 S1 S0 BP3 BP2 BP1 BP0 WEL (Block (Block (Block (Block (Write Enable Protected bits) Protected bits) Protected bits) Protected bits) Latch) (note 2) (note 2) (note 2) (note 2) Non-volatile bit Non-volatile bit Non-volatile bit Non-volatile bit Non-volatile bit 1 = write enable 0 = not write enable volatile bit WIP (Write In Progress bit) 1 = write operation 0 = not in write operation volatile bit Note 1. In OTP mode, SRP bit is served as OTP_LOCK bit. 2. See the table “Protected Area Sizes Sector Organization”. 4.4.2. For SST25VF032B： This Application Note may be revised by subsequent versions or modifications due to changes in technical specifications. 9 ©2010 Eon Silicon Solution Inc. Rev. A, Issue Date: 2010/12/29 www.eonssi.com Eon Silicon Solution Inc. 4.5. Different One Time Programming Definition * The definitions of OTP are different! 4.5.1. For EN25Q32B： OTP Sector Address Sector Sector Size Address Range 1023 512 Bytes 3FF000h – 3FF1FFh Note: The OTP sector is mapping to sector 1023 4.5.2. For SST25VF032B：NO This Application Note may be revised by subsequent versions or modifications due to changes in technical specifications. 10 ©2010 Eon Silicon Solution Inc. Rev. A, Issue Date: 2010/12/29 www.eonssi.com Eon Silicon Solution Inc. 5. PERFORMANCE DIFFERENCES 5.1. KEY AC PARAMETER PERFORMANCE Parameter EN25Q32B SST25VF032B tCH (serial clock high time) Min @ 4ns Min @ 6ns tCL (serial clock low time) Min @ 4ns Min @ 6ns tCLCH(serial clock rise time) Min @ 0.1V / ns Min @ 0.1V / ns tCLCL(serial clock fall time) Min @ 0.1V / ns Min @ 0.1V / ns Min@ 5ns Min @ 15ns Min @ 50ns Min @ 5ns Min @ 50ns tDSU(Data in setup time) Min @ 2ns Min @ 2ns tDH(Data in hold time) Min @ 5ns Min @ 4ns tCHSH(CS# active setup / hold time) (CS# high time for read) (CS# high time for program/erase) tSHSL 5.2. Power-On Timings Parameter Description EN25Q32B tVSL VCC(min) to CS# low 10µs tPUW Time delay to Write instruction 10ms tPU-READ tPU-WRITE VDD Min to Read/Write Operation SST25VF032B 100µs 5.3. ERASE AND PROGRAM PERFORMANCE The ERASE and PROGRAM Performance Comparison EN25Q32B Parameter SST25VF032B Typ Max 0.8ms 5ms 10μs*1 Sector Erase Time 0.05 0.3 0.025 sec Block Erase Time 0.2 2 0.025 sec Chip Erase Time 15 25 0.05 sec Page Programming Time Typ Unit Max Note: 1. For one byte programming time. This Application Note may be revised by subsequent versions or modifications due to changes in technical specifications. 11 ©2010 Eon Silicon Solution Inc. Rev. A, Issue Date: 2010/12/29 www.eonssi.com Eon Silicon Solution Inc. Revisions List Revision No Description Date A 2010/12/29 Initial Release This Application Note may be revised by subsequent versions or modifications due to changes in technical specifications. 12 ©2010 Eon Silicon Solution Inc. Rev. A, Issue Date: 2010/12/29 www.eonssi.com