Technical Data Sheet

VNH3SP30-E
Automotive fully integrated H-bridge motor driver
Features
Type
RDS(on)
Iout
Vccmax
VNH3SP30-E
45mmax
per leg)
30A
40V
MultiPowerSO-30™
■
Output current: 30A
■
5V logic level compatible inputs
■
Undervoltage and overvoltage shutdown
■
Overvoltage clamp
■
Thermal shut down
■
Cross-conduction protection
■
Linear current limiter
■
Very low standby power consumption
■
PWM operation up to 10 kHz
■
Protection against loss of ground and loss of
VCC
■
Package: ECOPACK®
The low-side switches are vertical MOSFETs
manufactured using STMicroelectronics
proprietary EHD (“STripFET™”) process.The
three circuits are assembled in a MultiPowerSO30 package on electrically isolated lead frames.
This package, specifically designed for the harsh
automotive environment, offers improved thermal
performance thanks to exposed die pads.
Moreover, its fully symmetrical mechanical design
provides superior manufacturability at board level.
The input signals INA and INB can directly
interface with the microcontroller to select the
motor direction and the brake condition. Pins
DIAGA/ENA or DIAGB/ENB, when connected to an
external pull-up resistor, enable one leg of the
bridge. They also provide a feedback digital
diagnostic signal. The normal condition operation
is explained in The speed of the motor can be
controlled in all possible conditions by the PWM
up to kHz. In all cases, a low level state on the
PWM pin will turn off both the LSA and LSB
switches. When PWM rises to a high level, LSA or
LSB turn on again depending on the input pin
state.
Description
The VNH3SP30-E is a full-bridge motor driver
intended for a wide range of automotive
applications. The device incorporates a dual
monolithic high-side driver (HSD) and two lowside switches. The HSD switch is designed using
STMicroelectronics proprietary VIPower™ M0-3
technology that efficiently integrates a true Power
MOSFET with an intelligent signal/protection
circuit on the same die.
Table 1.
Device summary
Order codes
Package
MultiPowerSO-30
September 2013
Tube
Tape & reel
VNH3SP30-E
VNH3SP30TR-E
Rev 8
1/33
www.st.com
33
Contents
VNH3SP30-E
Contents
1
Block diagram and pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
4
2.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3
Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.1
Reverse battery protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.2
Open load detection in Off mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.3
Test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.1
5
6
2/33
MultiPowerSO-30 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.1.1
Thermal calculation in clockwise and anti-clockwise operation in steadystate mode 26
4.1.2
Thermal resistances definition
(values according to the PCB heatsink area) . . . . . . . . . . . . . . . . . . . . . 26
4.1.3
Thermal calculation in transient mode . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.1.4
Single pulse thermal impedance definition
(values according to the PCB heatsink area) . . . . . . . . . . . . . . . . . . . . . 26
Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.1
ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5.2
MultiPowerSO-30 package mechanical data . . . . . . . . . . . . . . . . . . . . . . 29
5.3
Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
VNH3SP30-E
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Block description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin functions description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Logic inputs (INA, INB, ENA, ENB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Switching (VCC = 13V, RLOAD = 1.1, unless otherwise specified) . . . . . . . . . . . . . . . . . . 10
Protection and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Truth table in normal operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Truth table in fault conditions (detected on OUTA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Electrical transient requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Thermal calculation in clockwise and anti-clockwise operation in steady-state mode . . . . 26
Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
MultiPowerSO-30 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3/33
List of figures
VNH3SP30-E
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
4/33
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Definition of the delay times measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Definition of the low side switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Definition of the high side switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
On state supply current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Off state supply current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Input high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Input low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
High level enable pin current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Delay time during change of operation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Enable clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
High level enable voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Low level enable voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
PWM high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
PWM low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
PWM high level current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Overvoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Current limitation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
On state high side resistance vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
On state low side resistance vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
On state high side resistance vs Vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
On state low side resistance vs Vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Output voltage rise time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Output voltage fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Enable output low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
ON state leg resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Typical application circuit for DC to 10 kHz PWM operation short circuit protection . . . . . 20
Half-bridge configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Multi-motors configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Waveforms in full bridge operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Waveforms in full bridge operation (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
MultiPowerSO-30™ PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Chipset configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Auto and mutual Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . 25
MultiPowerSO-30 HSD thermal impedance junction ambient single pulse . . . . . . . . . . . . 27
MultiPowerSO-30 LSD thermal impedance junction ambient single pulse . . . . . . . . . . . . . 27
Thermal fitting model of an H-bridge in MultiPowerSO-30 . . . . . . . . . . . . . . . . . . . . . . . . . 28
MultiPowerSO-30 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
MultiPowerSO-30 suggested pad layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
MultiPowerSO-30 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
MultiPowerSO-30 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
VNH3SP30-E
1
Block diagram and pins description
Block diagram and pins description
Figure 1.
Block diagram
Table 2.
Block description
Name
Description
Logic control
Allows the turn-on and the turn-off of the high side and the low side switches
according to the truth table
Overvoltage +
undervoltage
Shuts down the device outside the range [5.5V..36V] for the battery voltage
High side and low
side clamp voltage
Protects the high side and the low side switches from the high voltage on the
battery line in all configurations for the motor
High side and low
side driver
Drives the gate of the concerned switch to allow a proper RDS(on) for the leg of
the bridge
Linear current limiter
Limits the motor current by reducing the high side switch gate-source voltage
when short-circuit to ground occurs
Overtemperature
protection
In case of short-circuit with the increase of the junction’s temperature, shuts
down the concerned high side to prevent its degradation and to protect the die
Fault detection
Signals an abnormal behavior of the switches in the half-bridge A or B by
pulling low the concerned ENx/DIAGx pin
5/33
Block diagram and pins description
VNH3SP30-E
Figure 2.
Configuration diagram (top view)
Table 3.
Pin definitions and functions
Pin No
1, 25, 30
Symbol
Function
OUTA, Heat Slug3 Source of high side switch A / Drain of low side switch A
2, 4, 7, 9, 12,
14, 17, 22, 24, NC
29
Not connected
3, 13, 23
VCC, Heat Slug1
Drain of high side switches and power supply voltage
6
ENA/DIAGA
Status of high side and low side switches A; open drain output
5
INA
Clockwise input
8
PWM
PWM input
11
INB
Counter clockwise input
10
ENB/DIAGB
Status of high side and low side switches B; open drain output
15, 16, 21
OUTB, Heat Slug2 Source of high side switch B / Drain of low side switch B
26, 27, 28
GNDA
Source of low side switch A(1)
18, 19, 20
GNDB
Source of low side switch B(1)
1. GNDA and GNDB must be externally connected together.
6/33
VNH3SP30-E
Block diagram and pins description
Table 4.
Pin functions description
Name
VCC
Description
Battery connection
GNDA, GNDB Power grounds; must always be externally connected together
OUTA, OUTB
Power connections to the motor
INA, INB
Voltage controlled input pins with hysteresis, CMOS compatible. These two pins
control the state of the bridge in normal operation according to the truth table (brake
to VCC, brake to GND, clockwise and counterclockwise).
PWM
Voltage controlled input pin with hysteresis, CMOS compatible. Gates of low side
FETs are modulated by the PWM signal during their ON phase allowing speed
control of the motor.
ENA/DIAGA,
ENB/DIAGB
Open drain bidirectional logic pins. These pins must be connected to an external pull
up resistor. When externally pulled low, they disable half-bridge A or B. In case of
fault detection (thermal shutdown of a high side FET or excessive ON state voltage
drop across a low side FET), these pins are pulled low by the device (see truth table
in fault condition).
7/33
Electrical specifications
2
Electrical specifications
Figure 3.
2.1
8/33
VNH3SP30-E
Current and voltage conventions
Absolute maximum ratings
Table 5.
Absolute maximum ratings
Symbol
Parameter
Value
Unit
-0.3...40
V
Vcc
Supply voltage
Imax1
Maximum output current (continuous)
30
IR
Reverse output current (continuous)
-30
IIN
Input current (INA and INB pins)
10
IEN
Enable input current (DIAGA/ENA and DIAGB/ENB pins)
10
Ipw
PWM input current
10
VESD
Electrostatic discharge (R = 1.5k, C = 100pF)
– logic pins
– output pins: OUTA, OUTB, VCC
Tj
Junction operating temperature
Tc
Case operating temperature
-40 to 150
TSTG
Storage temperature
-55 to 150
A
4
5
mA
kV
kV
Internally limited
°C
VNH3SP30-E
2.2
Electrical specifications
Electrical characteristics
Vcc = 9V up to 18V; -40°C < Tj < 150°C, unless otherwise specified.
Table 6.
Symbol
VCC
IS
Power section
Parameter
Test Conditions
Operating supply
voltage
Supply current
Min Typ
Max Unit
5.5
36
V
30
40
µA
µA
15
mA
Off state:
INA = INB = PWM = 0; Tj = 25°C; VCC = 13V
INA = INB = PWM = 0
20
On state:
INA or INB = 5V, no PWM
RONHS
Static high side
resistance
IOUT = 12A; Tj = 25°C
IOUT = 12A; Tj = -40 to 150°C
23
30
60
RONLS
Static low side
resistance
IOUT = 12A; Tj = 25°C
IOUT = 12A; Tj = -40 to 150°C
11
15
30
Vf
High side freewheeling diode
forward voltage
If = 12 A
0.8
1.1
V
High side off state
output current
(per channel)
Tj = 25°C; VOUTX = ENX = 0V; VCC = 13V
Tj = 125°C; VOUTX = ENX = 0V; VCC = 13V
3
5
µA
IL(off)
Table 7.
Symbol
VIL
m
Logic inputs (INA, INB, ENA, ENB)
Parameter
Test conditions
Min Typ Max Unit
Input low level voltage
VIH
Input high level voltage
VIHYST
Input hysteresis voltage
VICL
Input clamp voltage
IINL
1.5
Normal operation (DIAGX/ENX pin acts
as an input pin)
3.25
0.5
V
IIN = 1mA
6
6.8
8
IIN = -1mA
-1
-0.7 -0.3
Input low current
VIN = 1.5V
1
IINH
Input high current
VIN = 3.25V
10
VDIAG
Enable output low level
voltage
Fault operation (DIAGX/ENX pin acts as
an output pin); IEN = 1mA
0.4
µA
V
9/33
Electrical specifications
Table 8.
Symbol
PWM
Parameter
Vpwl
PWM low level voltage
Ipwl
PWM low level pin
current
Vpwh
PWM high level voltage
Ipwh
PWM high level pin
current
Vpwhhyst
PWM hysteresis voltage
Vpwcl
PWM clamp voltage
Vpwtest
Test mode PWM pin
voltage
Ipwtest
Test mode PWM pin
current
Table 9.
Symbol
Test Conditions
Min
Vpw = 1.5V
Typ
Max
Unit
1.5
V
1
µA
3.25
V
Vpw = 3.25V
10
µA
V
0.5
Ipw = 1mA
VCC + 0.3
VCC + 0.7
VCC + 1
Ipw = -1mA
-5
-3.5
-2
-3.5
-2
-0.5
-2000
-500
VIN = -2 V
Switching (VCC = 13V, RLOAD = 1.1, unless otherwise specified)
Parameter
Test Conditions
Min
Typ
0
Max
Unit
10
kHz
PWM frequency
td(on)
Turn-on delay time
Input rise time < 1µs
(see Figure 6)
100
300
td(off)
Turn-off delay time
Input rise time < 1µs
(see Figure 6)
85
255
tr
Rise time
(see Figure 5)
1.5
3
tf
Fall time
(see Figure 5)
2
5
tDEL
Delay time during change
of operating mode
(see Figure 4)
600
1800
Symbol
V
µA
f
Table 10.
10/33
VNH3SP30-E
µs
Protection and diagnostic
Parameter
Test Conditions
Min
Typ
VUSD
Undervoltage shut-down
VOV
Overvoltage shut-down
36
43
ILIM
Current limitation
30
45
TTSD
Thermal shut-down temperature
150
170
TTR
Thermal reset temperature
THYST
Thermal hysteresis
Max
Unit
5.5
V
VIN = 3.25V
200
°C
135
7
A
15
VNH3SP30-E
Figure 4.
Electrical specifications
Definition of the delay times measurement
VINA
t
VINB
t
PWM
t
ILOAD
tDEL
tDEL
t
Figure 5.
Definition of the low side switching times
PWM
t
VOUTA, B
90%
tf
80%
20%
10%
tr
t
11/33
Electrical specifications
Figure 6.
VNH3SP30-E
Definition of the high side switching times
VINA
tD(on)
tD(off)
t
VOUTA
90%
10%
t
12/33
VNH3SP30-E
Electrical specifications
Table 11.
INA
Truth table in normal operating conditions
INB
DIAGA/ENA
DIAGB/ENB
OUTA
1
1
OUTB
H
Brake to VCC
L
Clockwise (CW)
H
Counterclockwise (CCW)
L
Brake to GND
H
0
1
Operating mode
1
1
0
L
0
Table 12.
INA
Truth table in fault conditions (detected on OUTA)
INB
DIAGA/ENA
DIAGB/ENB
OUTA
1
OUTB
H
1
0
L
1
1
H
0
0
0
X
X
OPEN
0
L
OPEN
1
H
1
0
L
Fault Information
Note:
Protection Action
Notice that saturation detection on the low side power MOSFET is possible only if the
impedance of the short-circuit from the output to the battery is less than 100m when the
device is supplied with a battery voltage of 13.5V.
13/33
Electrical specifications
Table 13.
VNH3SP30-E
Electrical transient requirements
ISO T/R - 7637/1
Test Level
Test Level
Test Level
Test Level
Test Levels
Test Pulse
I
II
III
IV
Delays and Impedance
1
-25V
-50V
-75V
-100V
2ms, 10
2
+25V
+50V
+75V
+100V
0.2ms, 10
3a
-25V
-50V
-100V
-150V
3b
+25V
+50V
+75V
+100V
4
-4V
-5V
-6V
-7V
100ms, 0.01
5
+26.5V
+46.5V
+66.5V
+86.5V
400ms, 2
0.1µs, 50
ISO T/R - 7637/1
Test Pulse
Test Levels
Result I
Test Levels
Result II
Test Levels
Result III
Test Levels
Result IV
C
C
C
E
E
E
1
2
3a
C
3b
4
5(1)
1. For load dump exceeding the above value a centralized suppressor must be adopted
Class
14/33
Contents
C
All functions of the device are performed as designed after exposure to
disturbance.
E
One or more functions of the device are not performed as designed after
exposure to disturbance and cannot be returned to proper operation without
replacing the device.
VNH3SP30-E
Electrical specifications
2.3
Electrical characteristics curves
Figure 7.
On state supply current
Figure 8.
Figure 9.
High level input current
Figure 10. Input clamp voltage
Figure 11. Input high level voltage
Off state supply current
Figure 12. Input low level voltage
15/33
Electrical specifications
VNH3SP30-E
Figure 13. Input hysteresis voltage
Figure 14. High level enable pin current
Figure 15. Delay time during change of
operation mode
Figure 16. Enable clamp voltage
Figure 17. High level enable voltage
Figure 18. Low level enable voltage
16/33
VNH3SP30-E
Electrical specifications
Figure 19. PWM high level voltage
Figure 20. PWM low level voltage
Figure 21. PWM high level current
Figure 22. Overvoltage shutdown
Figure 23. Undervoltage shutdown
Figure 24. Current limitation
17/33
Electrical specifications
VNH3SP30-E
Figure 25. On state high side resistance vs
Tcase
Figure 26. On state low side resistance vs
Tcase
Figure 27. On state high side resistance vs
Vcc
Figure 28. On state low side resistance vs Vcc
Figure 29. Output voltage rise time
Figure 30. Output voltage fall time
18/33
VNH3SP30-E
Figure 31. Enable output low level voltage
Electrical specifications
Figure 32. ON state leg resistance
19/33
Application information
3
VNH3SP30-E
Application information
In normal operating conditions the DIAGX/ENX pin is considered as an input pin by the
device. This pin must be externally pulled high.
PWM pin usage: In all cases, a “0” on the PWM pin will turn off both LSA and LSB switches.
When PWM rises back to “1”, LSA or LSB turn on again depending on the input pin state.
Figure 33. Typical application circuit for DC to 10 kHz PWM operation short circuit
protection
µC
Note:
The value of the blocking capacitor (C) depends on the application conditions and defines voltage and
current ripple onto supply line at PWM operation. Stored energy of the motor inductance may fly back
into the blocking capacitor, if the bridge driver goes into tri-state. This causes a hazardous overvoltage
if the capacitor is not big enough. As basic orientation, 500µF per 10A load current is recommended.
In case of a fault condition the DIAGX/ENX pin is considered as an output pin by the device.
The fault conditions are:
20/33
●
overtemperature on one or both high sides
●
short to battery condition on the output (saturation detection on the low side power
MOSFET)
VNH3SP30-E
Application information
Possible origins of fault conditions may be:
●
●
OUTA is shorted to ground  overtemperature detection on high side A.
OUTA is shorted to VCC  low side power MOSFET saturation detection(a).
When a fault condition is detected, the user can know which power element is in fault by
monitoring the INA, INB, DIAGA/ENA and DIAGB/ENB pins.
In any case, when a fault is detected, the faulty leg of the bridge is latched off. To turn on the
respective output (OUTX) again, the input signal must rise from low to high level.
3.1
Reverse battery protection
Three possible solutions can be considered:
1.
a Schottky diode D connected to VCC pin
2.
an N-channel MOSFET connected to the GND pin (see Figure 33: Typical application
circuit for DC to 10 kHz PWM operation short circuit protection on page 20
3.
a P-channel MOSFET connected to the VCC pin
The device sustains no more than -30A in reverse battery conditions because of the two
body diodes of the power MOSFETs. Additionally, in reverse battery condition the I/Os of
VNH3SP30-E will be pulled down to the VCC line (approximately -1.5V). A series resistor
must be inserted to limit the current sunk from the microcontroller I/Os. If IRmax is the
maximum target reverse current through µC I/Os, the series resistor is:
V IOs – V CC
R = --------------------------------I Rmax
3.2
Open load detection in Off mode
It is possible for the microcontroller to detect an open load condition by adding a simply
resistor (for example, 10k ohm) between one of the outputs of the bridge (for example,
OUTB) and one microcontroller input. A possible sequence of inputs and enable signals is
the following: INA = 1, INB = X, ENA = 1, ENB = 0.
●
normal condition: OUTA = H and OUTB = H
●
open load condition: OUTA = H and OUTB = L: In this case the OUTB pin is internally
pulled down to GND. This condition is detected on OUTB pin by the microcontroller as
an open load fault.
a. An internal operational amplifier compares the Drain-Source MOSFET voltage with the internal reference (2.7V
Typ.). The relevant low side power MOS is switched off when its Drain-Source voltage exceeds the reference
voltage.
21/33
Application information
3.3
VNH3SP30-E
Test mode
The PWM pin can be used to test the load connection between two half-bridges. In the Test
mode (Vpwm = -2V) the internal power MOS gate drivers are disabled. The INA or INB inputs
can be used to turn on the high side A or B, respectively, in order to connect one side of the
load at VCC voltage. The check of the voltage on the other side of the load can be used to
verify the continuity of the load connection. In case of load disconnection, the DIADX/ENX
pin corresponding to the faulty output is pulled down.
Figure 34. Half-bridge configuration
VCC
INA
INB
DIAGA/ENA
DIAGB/ENB
PWM
INA
INB
DIAGA/ENA
DIAGB/ENB
PWM
OUTA
GNDA
Note:
M
OUTB
GNDA
GNDB
OUTB
OUTA
GNDB
The VNH3SP30-E can be used as a high power half-bridge driver achieving an On
resistance per leg of 22.5m.
Figure 35. Multi-motors configuration
VCC
INA
INB
DIAGA/ENA
DIAGB/ENB
PWM
INA
INB
DIAGA/ENA
DIAGB/ENB
PWM
OUTA
OUTB
GNDA
GNDB
M1
Note:
22/33
M2
OUTB
OUTA
GNDA
GNDB
M3
The VNH3SP30-E can easily be designed in multi-motors driving applications such as seat
positioning systems where only one motor must be driven at a time. DIAGX/ENX pins allow
to put unused half-bridges in high impedance.
VNH3SP30-E
Application information
Figure 36. Waveforms in full bridge operation
23/33
Application information
Figure 37. Waveforms in full bridge operation (continued)
24/33
VNH3SP30-E
VNH3SP30-E
Package and PCB thermal data
4
Package and PCB thermal data
4.1
MultiPowerSO-30 thermal data
Figure 38. MultiPowerSO-30™ PC board
Layout condition of Rth and Zth measurements (PCB FR4 area = 58mm x 58mm, PCB
thickness = 2mm, Cu thickness = 35m, Copper areas: from minimum pad layout to
16cm2).
Figure 39. Chipset configuration
HIGH SIDE
CHIP
HSAB
LOW SIDE
CHIP A
LOW SIDE
CHIP B
LSA
LSB
Figure 40. Auto and mutual Rthj-amb vs PCB copper area in open box free air
condition
45
RthHS
40
RthLS
35
RthHSLS
30
RthLSLS
25
20
15
°C/W
Note:
10
5
0
0
5
10
15
cm2 of Cu area (refer to PCB layout)
20
25/33
Package and PCB thermal data
4.1.1
Thermal calculation in clockwise and anti-clockwise operation in
steady-state mode
Table 14.
Thermal calculation in clockwise and anti-clockwise operation in steadystate mode
HSA HSB LSA LSB
4.1.2
VNH3SP30-E
TjHSAB
TjLSA
TjLSB
ON OFF OFF ON
PdHSA x RthHS + PdLSB PdHSA x RthHSLS +
x RthHSLS + Tamb
PdLSB x RthLSLS + Tamb
PdHSA x RthHSLS + PdLSB
x RthLS + Tamb
OFF ON
PdHSB x RthHS + PdLSA PdHSB x RthHSLS +
x RthHSLS + Tamb
PdLSA x RthLS + Tamb
PdHSB x RthHSLS + PdLSA
x RthLSLS + Tamb
ON OFF
Thermal resistances definition
(values according to the PCB heatsink area)
RthHS = RthHSA = RthHSB = High Side Chip Thermal Resistance Junction to Ambient (HSA or
HSB in ON state)
RthLS = RthLSA = RthLSB = Low Side Chip Thermal Resistance Junction to Ambient
RthHSLS = RthHSALSB = RthHSBLSA = Mutual Thermal Resistance Junction to Ambient
between High Side and Low Side Chips
RthLSLS = RthLSALSB = Mutual Thermal Resistance Junction to Ambient between Low Side
Chips
4.1.3
Thermal calculation in transient mode(b)
TjHSAB = ZthHS x PdHSAB + ZthHSLS x (PdLSA + PdLSB) + Tamb
TjLSA = ZthHSLS x PdHSAB + ZthLS x PdLSA + ZthLSLS x PdLSB + Tamb
TjLSB = ZthHSLS x PdHSAB + ZthLSLS x PdLSA + ZthLS x PdLSB + Tamb
4.1.4
Single pulse thermal impedance definition
(values according to the PCB heatsink area)
ZthHS = High Side Chip Thermal Impedance Junction to Ambient
ZthLS = ZthLSA = ZthLSB = Low Side Chip Thermal Impedance Junction to Ambient
ZthHSLS = ZthHSABLSA = ZthHSABLSB = Mutual Thermal Impedance Junction to Ambient
between High Side and Low Side Chips
ZthLSLS = ZthLSALSB = Mutual Thermal Impedance Junction to Ambient between Low Side
Chips
b.
Calculation is valid in any dynamic operating condition. Pd values set by user.
26/33
VNH3SP30-E
Package and PCB thermal data
Equation 1: pulse calculation formula
Z TH = R TH   + Z THtp  1 –  
where  = t p  T
Figure 41.
MultiPowerSO-30 HSD thermal impedance junction ambient single pulse
100
Footprint
4 cm2
8 cm2
16 cm2
ZthHS
Footprint
4 cm2
8 cm2
16 cm2
10
°C/W
ZthHSLS
1
0.1
0.001
0.01
0.1
time (sec)
1
10
100
1000
Figure 42. MultiPowerSO-30 LSD thermal impedance junction ambient single pulse
100
Footprint
4 cm2
8 cm2
16 cm2
Footprint
4 cm2
8 cm2
16 cm2
°C/W
10
1
0,1
0,001
0,01
0,1
time (sec)
1
10
100
1000
27/33
Package and PCB thermal data
VNH3SP30-E
Figure 43. Thermal fitting model of an H-bridge in MultiPowerSO-30
Table 15.
Thermal parameters(1)
Area/island (cm2)
Footprint
R1 = R7 (°C/W)
0.05
R2 = R8 (°C/W)
0.3
R3 (°C/W)
0.5
R4 (°C/W)
1.3
R5 (°C/W)
14
R6 (°C/W)
44.7
R9 = R10= R15= R16 (°C/W)
0.6
R11 = R17 (°C/W)
0.8
R12 = R18 (°C/W)
1.5
R13 = R19 (°C/W)
20
R14 = R20 (°C/W)
46.9
R21 = R22 = R23 (°C/W)
115
C1 = C7 = C9 = C15 (W.s/°C)
0.001
C2 = C8 (W.s/°C)
0.005
C3 = (W.s/°C)
0.02
C4 = C13 = C19 (W.s/°C)
0.3
C5 (W.s/°C)
0.6
C6 (W.s/°C)
5
C10 = C11= C16 = C17 (W.s/°C)
0.003
C12 = C18 (W.s/°C)
0.075
C14 = C20 (W.s/°C)
2.5
4
8
16
39.1
31.6
23.7
36.1
30.4
20.8
7
9
11
3.5
4.5
5.5
1. The blank space means that the value is the same as the previous one.
28/33
VNH3SP30-E
Package and packing information
5
Package and packing information
5.1
ECOPACK® packages
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second-level interconnect. The category of
Second-Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97.
The maximum ratings related to soldering conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
5.2
MultiPowerSO-30 package mechanical data
Figure 44. MultiPowerSO-30 package outline
29/33
Package and packing information
Table 16.
VNH3SP30-E
MultiPowerSO-30 mechanical data
Millimeters
Symbol
Min
Typ
A
2.35
A2
1.85
2.25
A3
0
0.1
B
0.42
0.58
C
0.23
0.32
D
17.1
E
18.85
E1
15.9
e
17.2
17.3
19.15
16
16.1
1
F1
5.55
6.05
F2
4.6
5.1
F3
9.6
10.1
L
0.8
1.15
N
S
10deg
0deg
Figure 45. MultiPowerSO-30 suggested pad layout
30/33
Max
7deg
VNH3SP30-E
Package and packing information
5.3
Packing information
Note:
The devices can be packed in tube or tape and reel shipments (see the Device summary on
page 1 for packaging quantities).
Figure 46. MultiPowerSO-30 tube shipment (no suffix)
Dimension
A
C
mm
Tube length (± 0.5)
A
B
C (± 0.13)
B
532
3.82
23.6
0.8
Figure 47. MultiPowerSO-30 tape and reel shipment (suffix “TR”)
Reel dimensions
Dimension
mm
A (max)
B (min)
C (± 0.2)
D (min)
G (+ 2 / -0)
N (min)
T (max)
330
1.5
13
20.2
32
100
38.4
Tape dimensions
According to Electronic Industries
Association (EIA) Standard 481 rev. A, Feb
1986
Description
Dimension
mm
Tape width
Tape Hole Spacing
Component Spacing
Hole Diameter
Hole Diameter
Hole Position
W
P0 (± 0.1)
P
D (± 0.1/-0)
D1 (min)
F (± 0.1)
32
4
24
1.5
2
14.2
End
Start
Top
cover
tape
No components
Components
No components
500 mm min
500 mm min
Empty components pockets
User direction of feed
31/33
Revision history
6
VNH3SP30-E
Revision history
Table 17.
Document revision history
Date
Revision
Description of changes
Aug-2004
1
Initial release of lead-free version based on the VNH3SP30 datasheet
(May 2004 - Rev.1)
Aug- 2005
2
Modified figure 5
3
Document converted into new ST corporate template.
Changed document title .
Changed features on page 1 to add ECOPACK® package.
Added section 1: device block description on page 5.
Added section 2: pinout description on page 6.
Added section 3: maximum ratings on page 8.
Added section 4: electrical characteristics on page 9.
Added “low” and “high” to parameters for IINL and IINH in Table 6 on
page 9.
Added section 5: Waveforms and truth table on page 12.
Changed first of two fault conditions in section 5 on page 12.
Inserted note in Figure 4 on page 12.
Added vertical limitation line to left side arrow of tD(off) to Figure 7 on
page 17.
Added section 6: thermal data on page 26.
Added section 7: package characteristics on page 30.
Added section 8: packaging information on page 32.
Updated disclaimer (last page) to include a mention about the use of
ST products in automotive applications.
20-Jun-2007
4
Document reformatted.
Changed Table 6: Power section on page 9 : supply current and static
resistance values.
Added Table 7: Logic inputs (INA, INB, ENA, ENB) on page 9 : VDIAG
ROW .
Deleted Enable (Logic I/O pin) Table.
13-Sep-2007
5
Updated Table 2: Block description on page 5.
15-Nov-2007
6
Corrected Figure 34 note : changed On resistance per leg from 9.5
mto 22.5 m.
06-Feb-2008
7
Corrected Heat Slug numbers in Table 3: Pin definitions and functions.
24-Sep-2013
8
Updated disclaimer.
20-Dec-2006
32/33
VNH3SP30-E
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33/33