VNH5180A-E
Automotive fully integrated H-bridge motor driver
Features
Type
RDS(on)
Iout
VCCmax
VNH5180A-E
180 mΩ max
(per leg)
8A
41 V
PowerSSO-36 TP
■
Output current: 8 A
■
3 V CMOS compatible inputs
■
Undervoltage shutdown
■
Overvoltage clamp
■
Thermal shutdown
■
Cross-conduction protection
■
Current and power limitation
■
Very low standby power consumption
■
PWM operation up to 20 KHz
■
Protection against loss of ground and loss of
VCC
■
Current sense output proportional to motor
current
■
Output protected against short to ground and
short to VCC
■
Package: ECOPACK®
Description
The VNH5180A-E is a full bridge motor driver
intended for a wide range of automotive
applications. The device incorporates a dual
monolithic high-side driver and two low-side
switches. Both switches are designed using
STMicroelectronics’ well known and proven
Table 1.
proprietary VIPower® M0 technology that allows
to efficiently integrate on the same die a true
Power MOSFET with an intelligent
signal/protection circuitry. The three dies are
assembled in PowerSSO-36 TP package on
electrically isolated leadframes. This package,
specifically designed for the harsh automotive
environment offers improved thermal
performance thanks to exposed die pads.
Moreover, its fully symmetrical mechanical design
allows superior manufacturability at board level.
The input signals INA and INB can directly
interface to the microcontroller to select the motor
direction and the brake condition. The DIAGA/ENA
or DIAGB/ENB, when connected to an external
pull-up resistor, enables one leg of the bridge.
Each DIAGA/ENA provides a feedback digital
diagnostic signal as well. The normal operating
condition is explained in the truth table. The CS
pin allows to monitor the motor current by
delivering a current proportional to its value when
CS_DIS pin is driven low or left open. When
CS_DIS is driven high, CS pin is in high
impedance condition. The PWM, up to 20 KHz,
allows to control the speed of the motor in all
possible conditions. In all cases, a low level state
on the PWM pin turns off both the LSA and LSB
switches.
Device summary
Order codes
Package
PowerSSO-36 TP
December 2011
Tube
Tape and reel
VNH5180A-E
VNH5180ATR-E
Doc ID 17074 Rev 5
1/31
www.st.com
1
Contents
VNH5180A-E
Contents
1
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
2.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1
4
Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.1
5
6
2/31
Reverse battery protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
PowerSSO-36 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.1.1
Thermal calculation in clockwise and anti-clockwise operation in
steady-state mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.1.2
Thermal calculation in transient mode . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.1
ECOPACK® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.2
PowerSSO-36 TP package information . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.3
PowerSSO-36 TP packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Doc ID 17074 Rev 5
VNH5180A-E
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Block description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin functions description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Logic inputs (INA, INB, ENA, ENB, PWM, CS_DIS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Switching (VCC = 13 V, RLOAD = 5 W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Protections and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Current sense (9 V < VCC < 18 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Truth table in normal operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Truth table in fault conditions (detected on OUTA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Electrical transient requirements (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Electrical transient requirements (part 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Electrical transient requirements (part 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Thermal calculation in clockwise and anti-clockwise operation in steady-state mode . . . . 23
Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
PowerSSO-36 TP mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Doc ID 17074 Rev 5
3/31
List of figures
VNH5180A-E
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
4/31
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Definition of the delay times measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Definition of the low-side switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Definition of the high-side switching times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Definition of dynamic cross conduction current during a PWM operation. . . . . . . . . . . . . . 14
Definition of delay response time of sense current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Waveforms in full-bridge operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Waveforms in full-bridge operation (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Typical application circuit for DC to 20 kHz PWM operation short circuit protection . . . . . 19
Behavior in fault condition (how a fault can be cleared) . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Half-bridge configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Multi-motors configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
PowerSSO-36™ PC board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Chipset configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Auto and mutual Rthj-amb vs PCB copper area in open box free air condition . . . . . . . . . 23
Detailed chipset configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
PowerSSO-36 HSD thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . 25
PowerSSO-36 LSD thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . 25
Thermal fitting model of an H-bridge in PowerSSO-36. . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
PowerSSO-36 TP package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
PowerSSO-36 TP tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
PowerSSO-36 TP tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Doc ID 17074 Rev 5
VNH5180A-E
1
Block diagram and pin description
Block diagram and pin description
Figure 1.
Block diagram
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Table 2.
Block description
Name
Description
Logic control
Allows the turn-on and the turn-off of the high-side and the
low-side switches according to the truth table.
Undervoltage
Shuts down the device for battery voltage lower than 5V.
High-side and low-side clamp voltage
Protect the high-side and the low-side switches from the
high voltage on the battery line.
High-side and low-side driver
Drive the gate of the concerned switch to allow a proper
RDS(on) for the leg of the bridge.
Current limitation
Limits the motor current in case of short circuit.
In case of short-circuit with the increase of the junction
High-side and low-side overtemperature
temperature, it shuts down the concerned driver to prevent
protection
degradation and to protect the die.
Low-side overload detector
Detects when low side current exceeds shutdown current
and latches off the concerned Low side.
Fault detection
Signalizes the abnormal behaviour of the switch (output
shorted to ground or output shorted to battery) by pulling
down the concerned ENx/DIAGx pin.
Power limitation
Limits the power dissipation of the high-side driver inside
safe range in case of short to ground condition.
Doc ID 17074 Rev 5
5/31
Block diagram and pin description
Figure 2.
VNH5180A-E
Configuration diagram (top view)
1
NC
DRAIN LSA
GND_A
GND_A
NC
GND_A
GND_A
DRAIN LSA
NC
SOURCE HSA
SOURCE HSA
SOURCE HSA
VCC
Slug2
NC
IN_A
EN/DIAG_A
IN_PWM
NC
Table 3.
Slug3
Slug1
19
18
NC
DRAIN LSB
GND_B
GND_B
NC
GND_B
GND_B
DRAIN LSB
NC
SOURCE HSB
SOURCE HSB
SOURCE HSB
VCC
NC
IN_B
EN/DIAG_B
CS_DIS
CS
Suggested connections for unused and not connected pins
Connection / pin
Current sense
N.C.
SOURCE_HSx
DRAIN_LSx
INPUTx, PWM
DIAGx/ENx
CS_DIS
Floating
Not allowed
X
X
X
X
To ground
Through 1 kΩ
resistor
X
Not allowed
X
Through 10 kΩ
resistor
Table 4.
6/31
36
Pin definitions and functions
Pin N°
Symbol
Function
13, 24
VCC, Heat Slug1
1, 5, 9, 14, 18, 23,
28, 32, 36
NC
Not connected.
15
INA
Clockwise input
16
ENA/DIAGA
17
IN_PWM
19
CS
Drain of high-side switches and power supply voltage.
Status of high-side and low-side switches A;
open drain output.
PWM input.
Output of current sense.
Doc ID 17074 Rev 5
VNH5180A-E
Block diagram and pin description
Table 4.
Pin definitions and functions (continued)
Pin N°
Symbol
Function
20
CS_DIS
Active high CMOS compatible pin to disable current sense
pin.
21
ENB/DIAGB
22
INB
25, 26, 27, 29, 35
OUTB, Heat Slug3
30, 31, 33, 34
GNDB
2, 8, 10, 11, 12
OUTA, Heat Slug2
3, 4, 6, 7
GNDA
Table 5.
Status of high-side and low-side switches b;
open drain output.
Counter clockwise input.
Source of high-side switch B / drain of low-side switch B.
Source of low-side switch B.
Source of high-side switch A / drain of low-side switch A.
Source of low-side switch A.
Pin functions description
Name
Description
VCC
Battery connection.
GND
Power ground.
OUTA
OUTB
Power connections to the motor.
INA
INB
Voltage controlled input pins with hysteresis, CMOS compatible. These two pins
control the state of the bridge in normal operation according to the truth table (brake
to VCC, Brake to GND, clockwise and counterclockwise).
PWM
Voltage controlled input pin with hysteresis, CMOS compatible. Gates of low-side
FETS get modulated by the PWM signal during their ON phase allowing speed control
of the motor.
ENA/DIAGA
ENB/DIAGB
Open drain bidirectional logic pins.These pins must be connected to an external pull
up resistor. When externally pulled low, they disable half-bridge A or B. In case of fault
detection (thermal shutdown of a high-side FET or excessive ON-state voltage drop
across a low-side FET), these pins are pulled low by the device (see Table 14: Truth
table in fault conditions (detected on OUTA)).
CS
Analog current sense output. This output delivers a current proportional to the motor
current if CS_DIS is low or left open. The information can be read back as an analog
voltage across an external resistor.
CS_DIS
Active high CMOS compatible pin to disable the current sense pin.
Doc ID 17074 Rev 5
7/31
Electrical specifications
2
VNH5180A-E
Electrical specifications
Figure 3.
Current and voltage conventions
IS
VCC
IINA
IINB
IENA
IENB
VCC
INA
INB
CS
CS_DIS
DIAGB/ENB
PWM
VOUTA
ISENSE
ICSD
VOUTB
VSENSE
GND
Ipw
IGND
2.1
IOUTB
OUTB
DIAGA/ENA
VINA VINB VENA VENB
IOUTA
OUTA
VCSD
Vpw
Absolute maximum ratings
Stressing the device above the rating listed in the Table 6: Absolute maximum ratings may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality document.
Table 6.
Absolute maximum ratings
Symbol
Parameter
VCC
Supply voltage
Imax
Maximum output current (continuous)
Unit
+ 41
V
Internally limited
A
-15
A
IR
Reverse output current (continuous)
IIN
Input current (INA and INB pins)
+/- 10
mA
IEN
Enable input current (DIAGA/ENA and DIAGB/ENB pins)
+/- 10
mA
Ipw
PWM Input current
+/- 10
mA
CS_DIS input current
+/- 10
mA
VCC-41/+VCC
V
2
kV
Junction operating temperature
-40 to 150
°C
TSTG
Storage temperature
-55 to 150
°C
IGND
DC reverse ground pin current
200
mA
ICS_DIS
VCS
Current sense maximum voltage
VESD
Electrostatic discharge
(Human body model: R=1.5 kΩ, C=100 pF)
Tc
8/31
Value
Doc ID 17074 Rev 5
VNH5180A-E
2.2
Electrical specifications
Thermal data
Table 7.
Thermal data
Symbol
2.3
Parameter
Rthj-case
Thermal resistance junction-case (per leg)
Rthj-amb
Thermal resistance junction-ambient
Max. value
Unit
HSD
4.8
°C/W
LSD
4.6
See Figure 17
°C/W
Electrical characteristics
Values specified in this section are for VCC = 9 V up to 18 V; -40 °C < TJ < 150 °C, unless
otherwise specified.
Table 8.
Power section
Symbol
Parameter
Test conditions
VCC
Operating supply voltage
Supply current
Typ.
5.5
V
6
µA
Off-state with all fault cleared and
ENx = 0 (standby)
INA = INB = PWM = 0;
VCC = 13 V; Tj = - 40 to 150 °C
10
µA
Off-state (no standby)
INA = INB = PWM = 0; ENx = 5 V;
Tj = - 40 to 150 °C
5
mA
6
mA
6
mA
On-state:
INA or INB = 5 V; no PWM
3
3
On-state:
INA or INB = 5 V; PWM = 20 kHz
RONHS
Static high-side resistance
IOUT = 2.5 A; Tj = -40 °C
75
mΩ
IOUT = 2.5 A; Tj = 25 °C
115
mΩ
IOUT = 2.5 A; Tj = 150 °C
230
mΩ
IOUT = 2.5 A; Tj = - 40 to 150 °C
RONLS
Vf
Static low-side resistance
IOUT = 2.5 A; Tj = 25 °C
250
53.5
IOUT = 2.5 A; Tj = - 40 to 150 °C
High-side free-wheeling
diode forward voltage
Max. Unit
18
Off-state with all fault cleared and
ENx = 0 (standby)
INA = INB = PWM = 0; Tj = 25 °C;
VCC = 13 V
IS
Min.
IOUT = -2.5 A; Tj = 150 °C
Doc ID 17074 Rev 5
0.7
mΩ
mΩ
110
mΩ
0.9
V
9/31
Electrical specifications
Table 8.
Symbol
IL(off)
IRM
Table 9.
Symbol
Power section (continued)
Parameter
Test conditions
High-side off-state output
current (per channel)
Dynamic crossconduction current
Min.
Typ.
Max. Unit
Tj = 25 °C; VOUTX = ENX = 0 V;
VCC = 13 V
0
3
µA
Tj = 125 °C; VOUTX = ENX = 0 V;
VCC = 13 V
0
5
µA
IOUT= 2.5A (see Figure 6)
0.6
A
Logic inputs (INA, INB, ENA, ENB, PWM, CS_DIS)
Parameter
Test conditions
Min.
Typ.
Max.
Unit
0.9
V
VIL
Input low level voltage
Normal operation
(DIAGX/ENX pin acts as an
input pin)
VIH
Input high level voltage
Normal operation
(DIAGX/ENX pin acts as an
input pin)
2.1
V
VIHYST
Input hysteresis voltage
Normal operation
(DIAGX/ENX pin acts as an
input pin)
0.15
V
IIN = 1 mA
5.5
6.3
7.5
V
IIN = -1 mA
-1.0
-0.7
-0.3
V
1
VICL
Input clamp voltage
IINL
Input current
VIN = 0.9 V
IINH
Input current
VIN = 2.1 V
10
µA
Enable output low
level voltage
Fault operation
(DIAGX/ENX pin acts as an
output pin); IEN = 1 mA
0.4
V
Max.
Unit
20
kHz
VDIAG
Table 10.
Symbol
f
µA
Switching (VCC = 13 V, RLOAD = 5 Ω)
Parameter
Test conditions
PWM frequency
Min.
Typ.
0
td(on)
Turn-on delay time
Input rise time < 1µs
(see Figure 6)
250
µs
td(off)
Turn-off delay time
Input rise time < 1µs
(see Figure 6)
250
µs
tr
Rise time
See Figure 5
1
2
µs
tf
Fall time
See Figure 5
1
2
µs
Delay time during change
of operating mode
See Figure 4
400
1600
µs
High-side free wheeling
diode reverse recovery
time
See Figure 7
tDEL
trr
10/31
VNH5180A-E
Doc ID 17074 Rev 5
200
400
ns
VNH5180A-E
Electrical specifications
Table 11.
Protections and diagnostics
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
5
V
VUSD
Undervoltage shutdown
3
VUSDhyst
Undervoltage shutdown
hysteresis
0.5
V
ILIM_H
High-side current limitation
8
12
16
A
ISD_LS
Shutdown LS current
16
30
52
A
VCLPH
High-side clamp voltage (VCC to
OUTA = 0 or OUTB = 0)
IOUT = 2.5 A
41
46
52
V
VCLPLS
Low-side clamp voltage
(OUTA = VCC or
OUTB = VCC to GND)
IOUT = 2.5 A
41
46
52
V
TTSD(1)
Thermal shutdown temperature
VIN = 2.1 V
150
175
200
°C
TTR(2)
Thermal reset temperature
THYST
(2)
TTSD_LS
135
°C
Thermal hysteresis (TSD - TR)
7
Low-side thermal shutdown
temperature
VIN = 2.1 V
VCLP
Total clamp voltage (VCC to GND) IOUT = 2.5 A
tSD_LS
Time to shutdown for the low-side
°C
150
175
200
°C
41
46
52
V
10
µs
1. TTSD is the minimum threshold temperature between HS and LS
2. Valid for both HSD and LSD.
Table 12.
Symbol
Current sense (9 V < VCC < 18 V)
Parameter
Test conditions
Min.
Typ. Max. Unit
K0
IOUT/ISENSE
IOUT = 0.35 A; VSENSE = 0.32 V;
VCSD = 0 V; Tj = - 40 to 150 °C
645
840
1140
K1
IOUT/ISENSE
IOUT = 1 A; VSENSE = 0.98 V;
VCSD = 0 V; Tj = - 40 to 150 °C
700
820
955
K2
IOUT/ISENSE
IOUT = 2.5 A; VSENSE = 2.4 V;
VCSD = 0 V; Tj = - 40 to 150 °C
710
810
900
K3
IOUT/ISENSE
IOUT = 4 A; VSENSE = 4 V; VCSD = 0 V;
Tj = - 40 to 150 °C
690
790
900
dK0/K0(1)
Analog sense
current drift
IOUT = 0.35A; VSENSE = 0.32V;
VCSD = 0 V; Tj = - 40 to 150 °C
-18
18
%
dK1/K1(1)
Analog sense
current drift
IOUT = 1 A; VSENSE = 0.98 V;
VCSD = 0 V; Tj = - 40 to 150 °C
-13
13
%
dK2/K2(1)
Analog sense
current drift
IOUT = 2.5A; VSENSE = 2.4V;
VCSD = 0 V; Tj = - 40 to 150 °C
-13
13
%
dK3/K3(1)
Analog sense
current drift
IOUT = 4A; VSENSE = 4V; VCSD = 0 V;
Tj = - 40 to 150 °C
-13
13
%
Max analog sense
output voltage
IOUT = 2.5A; VCSD = 0 V;
RSENSE = 2 KΩ
VSENSE
Doc ID 17074 Rev 5
5
V
11/31
Electrical specifications
Table 12.
Symbol
VNH5180A-E
Current sense (9 V < VCC < 18 V) (continued)
Test conditions
Min.
Typ. Max. Unit
IOUT = 0 A; VSENSE = 0 V; VCSD = 5 V;
VIN = 0 V; Tj = - 40 to 150 °C
0
5
µA
VCSD = 0 V; VIN = 5 V;
Tj = - 40 to.150 °C
0
180
µA
VCSD = 5 V; VIN = 5 V; IOUT = 2.5 A;
Tj = - 40 to.150 °C
0
5
µA
Delay response time VIN = 5 V; VSENSE < 4 V, IOUT = 2.5 A,
tDSENSEH from falling edge of ISENSE = 90 % of ISENSEmax
(see Figure 8)
CS_DIS pin
50
µs
Delay response time VIN = 5 V; VSENSE < 4 V; IOUT = 2.5 A;
tDSENSEL from rising edge of ISENSE = 10 % of ISENSEmax
CS_DIS pin
(see Figure 8)
20
µs
ISENSE0
Parameter
Analog sense
leakage current
1. Analog sense current drift is deviation of factor K for a given device over (-40 °C to 150 °C and
9 V < VCC < 18 V) with respect to its value measured at TJ = 25 °C, VCC = 13 V.
Figure 4.
Definition of the delay times measurement
VINA
t
VINB
t
PWM
t
ILOAD
tDEL
tDEL
t
12/31
Doc ID 17074 Rev 5
VNH5180A-E
Figure 5.
Electrical specifications
Definition of the low-side switching times
PWM
t
VOUTA, B
90%
tf
Figure 6.
80%
20%
10%
tr
t
Definition of the high-side switching times
VINA
tD(off)
tD(on)
t
VOUTA
90%
10%
t
Doc ID 17074 Rev 5
13/31
Electrical specifications
Figure 7.
VNH5180A-E
Definition of dynamic cross conduction current during a PWM operation
INA = 1, INB = 0
PWM
t
IMOTOR
t
VOUTB
t
ICC
IRM
t
trr
Figure 8.
Definition of delay response time of sense current
INPUT
CS_DIS
LOAD CURRENT
SENSE CURRENT
tDSENSEH
14/31
Doc ID 17074 Rev 5
tDSENSEL
VNH5180A-E
Electrical specifications
Table 13.
Truth table in normal operating conditions
INA INB DIAGA/ENA DIAGB/ENB OUTA OUTB
1
H
1
CS
High Imp.
H
0
1
1
H
0
Brake to VCC
Clockwise (CW)
L
1
Operating mode
ISENSE = IOUT/K
Counterclockwise (CCW)
L
0
Table 14.
INA
L
High Imp.
Brake to GND
Truth table in fault conditions (detected on OUTA)
INB
DIAGA/ENA
DIAGB/ENB
OUTA
OUTB
1
H
0
L
1
CS (VCSD=0V)
High Imp.
1
1
0
OPEN
H
0
0
IOUTB/K
L
High Imp.
X
X
0
Fault Information
Note:
OPEN
Protection Action
In normal operating conditions the DIAGX/ENX pin is considered as an input pin by the
device. This pin must be externally pulled high.
Doc ID 17074 Rev 5
15/31
Electrical specifications
Table 15.
ISO 7637-2:
2004(E)
Test pulse
VNH5180A-E
Electrical transient requirements (part 1)
Test levels(1)
III
IV
1
-75V
-100V
2a
+37V
3a
Number of
pulses or
test times
Burst cycle/pulse
repetition time
Delays and
Impedance
Min.
Max.
5000 pulses
0.5s
5s
2 ms, 10Ω
+50V
5000 pulses
0.2s
5s
50µs, 2Ω
-100V
-150V
1h
90ms
100ms
0.1µs, 50Ω
3b
+75V
+100V
1h
90ms
100ms
0.1µs, 50Ω
4
-6V
-7V
1 pulse
100ms, 0.01Ω
5b(2)
+65V
+87V
1 pulse
400ms, 2Ω
1. The above test levels must be considered referred to VCC = 13.5 V except for pulse 5b.
2. Valid in case of external load dump clamp: 40V maximum referred to ground.
Table 16.
Electrical transient requirements (part 2)
Test level results(1)
ISO 7637-2:
2004(E)
Test pulse
III
IV
1
C
C
2a
C
C
3a
C
C
3b
C
C
4
C
C
5b(2)
C
C
1. The above test levels must be considered referred to VCC = 13.5 V except for pulse 5b.
2. Valid in case of external load dump clamp: 40V maximum referred to ground.
Table 17.
16/31
Electrical transient requirements (part 3)
Class
Contents
C
All functions of the device are performed as designed after exposure to disturbance.
E
One or more functions of the device are not performed as designed after exposure to
disturbance and cannot be returned to proper operation without replacing the device.
Doc ID 17074 Rev 5
VNH5180A-E
2.4
Electrical specifications
Waveforms
Figure 9.
Waveforms in full-bridge operation
NORMAL OPERATION (DIAGA/ENA=1, DIAGB/ENB=1)
LOAD CONNECTED BETWEEN OUTA, OUTB
DIAGA/ENA
DIAGB/ENB
INA
INB
PWM
OUTA
OUTB
IOUTA->OUTB
CS (*)
tDEL
CS_DIS
tDEL
(*) CS BEHAVIOUR DURING PWM MODE DEPENDS ON PWM FREQUENCY AND DUTY CYCLE
NORMAL OPERATION (DIAGA/ENA=1, DIAGB/ENB=0 and DIAGA/ENA=0, DIAGB/ENB=1)
LOAD CONNECTED BETWEEN OUTA, OUTB
DIAGA/ENA
DIAGB/ENB
INA
INB
PWM
OUTA
OUTB
IOUTA->OUTB
CS
CS_DIS
CURRENT LIMITATION/THERMAL SHUTDOWN or OUTA SHORTED TO GROUND
INA
INB
ILIM
IOUTA->OUTB
Tj =TTSD
TTSD_HSA
TTR_HSA
Tj < TTSD
TjHSA
Tj > TTR
DIAGA/ENA
DIAGB/ENB
CS
CS_DIS
current
limitation
normal operation
power limitation
OUTA shorted to ground
Doc ID 17074 Rev 5
normal operation
17/31
Electrical specifications
VNH5180A-E
Figure 10. Waveforms in full-bridge operation (continued)
OUTA shorted to VCC (resistive short) and undervoltage shutdown
CS_DIS
INA
INB
OUTA
OUTB
IOUTA->OUTB
ISD_LS
ILSA
TTSD_LS
Tj_LSA
DIAGB/ENB
DIAGA/ENA
CS
V<nominal
normal operation OUTA softly shorted to VCC
normal operation
undervoltage shutdown
OUTA shorted to VCC (pure short) and undervoltage shutdown
CS_DIS
INA
INB
OUTA
OUTB
IOUTA->OUTB
ISD_LS
ILSA
TTSD_LS
Tj_LSA
DIAGB/ENB
DIAGA/ENA
CS
V<nominal
normal operation OUTA hardly shorted to VCC
18/31
Doc ID 17074 Rev 5
normal operation
undervoltage shutdown
VNH5180A-E
3
Application information
Application information
In normal operating conditions the DIAGX/ENX pin is considered as an input pin by the
device. This pin must be externally pulled high.
PWM pin usage: In all cases, a “0” on the PWM pin turns off both LSA and LSB switches.
When PWM rises back to “1”, LSA or LSB turn on again depending on the input pin state.
Figure 11. Typical application circuit for DC to 20 kHz PWM operation short circuit
protection
VCC
Reg 5V
+ 5V
+5V
VCC
3.3K
3.3K
1K
DIAGA/ENA
1K
DIAGA/ENA
1K
1k
μC
HSA
HSB
PWM
OUTA
CS_DIS
1K
INA
10K
CS
OUTB
LSA
33nF
DIAGB/ENB
1K
LSB
INB
M
Vcc
1.5K
GND
GND
100K
S
G
b) N MOSFET
D
Note:
The value of the blocking capacitor (C) depends on the application conditions and defines
voltage and current ripple on supply line at PWM operation. Stored energy of the motor
inductance may fly back into the blocking capacitor, if the bridge driver goes into 3-state.
This causes a hazardous overvoltage if the capacitor is not big enough. As basic orientation,
500 µF per 10 A load current is recommended.
In case of a fault condition the DIAGX/ENX pin is considered as an output pin by the device.
The fault conditions are:
–
Overtemperature on one or both high-sides
–
Short to battery condition on the output (overcurrent detection on the low-side
Power MOSFET)
Possible origins of fault conditions may be:
OUTA is shorted to ground → overtemperature detection on high-side A
OUTA is shorted to VCC → low-side Power MOSFET overcurrent detection
When a fault condition is detected, the user can identify which power element is in fault by
monitoring the INA, INB, DIAGA/ENA and DIAGB/ENB pins.
Doc ID 17074 Rev 5
19/31
Application information
VNH5180A-E
In any case, when a fault is detected, the faulty leg of the bridge is latched off. To turn on the
respective output (OUTX) again, the input signal must rise from low to high level.
Figure 12. Behavior in fault condition (how a fault can be cleared)
Note:
In case of the fault condition is not removed, the procedure for unlatching and sending the
device in Stby mode is:
- Clear the fault in the device (toggle: INA if ENA = 0 or INB if ENB = 0)
- Pull low all inputs, PWM and Diag/EN pins within tDEL.
If the Diag/En pins are already low, PWM = 0, the fault can be cleared simply toggling the
input. The device enters in stby mode as soon as the fault is cleared.
3.1
Reverse battery protection
Three possible solutions can be considered:
–
A Schottky diode D connected to VCC pin
–
An N-channel MOSFET connected to the GND pin (see Figure 11: Typical
application circuit for DC to 20 kHz PWM operation short circuit protection)
–
A P-channel MOSFET connected to the VCC pin
The device sustains no more than -15 A in reverse battery conditions because of the two
Body diodes of the Power MOSFETs. Additionally, in reverse battery condition the I/Os of
VNH5180A-E is pulled down to the VCC line (approximately -1.5 V).
20/31
Doc ID 17074 Rev 5
VNH5180A-E
Application information
Series resistor must be inserted to limit the current sunk from the microcontroller I/Os. If
IRmax is the maximum target reverse current through microcontroller I/Os, series resistor is:
V
–V
IOs
CC
R = --------------------------------I
Rmax
Figure 13. Half-bridge configuration
VCC
INA
INB
DIAGA/ENA
DIAGB/ENB
PWM
INA
INB
DIAGA/ENA
DIAGB/ENB
PWM
OUTA
M
OUTB
GND
GND
Note:
OUTB
OUTA
The VNH5180A-E can be used as a high power half-bridge driver achieving an On
resistance per leg of 90 mΩ.
Figure 14. Multi-motors configuration
VCC
INA
INB
DIAGA/ENA
DIAGB/ENB
PWM
INA
INB
DIAGA/EN A
DIAGB/EN B
PWM
OUTA
OUTB
M2
GND
GND
M1
Note:
OUTB
OUTA
M3
The VNH5180A-E can easily be designed in multi-motors driving applications such as seat
positioning systems where only one motor must be driven at a time. DIAGX/ENX pins allow
to put unused half-bridges in high impedance.
Doc ID 17074 Rev 5
21/31
Package and PCB thermal data
VNH5180A-E
4
Package and PCB thermal data
4.1
PowerSSO-36 thermal data
Figure 15. PowerSSO-36™ PC board
Double layers: footprint
Double layers: 2cm2 of Cu
Double layers: 8cm2 of Cu
Note:
Board finish thickness 1.6 mm +/- 10 %, Board double layers, Board dimension 129 mm x 60 mm, Board Material FR4, Cu
thickness 0.070 mm (front and back side), Thermal vias spaced on a 1.2 mm x 1.2 mm grid, Vias pad clearance thickness
0.2 mm, Thermal via diameter 0.3 mm +/- 0.08 mm, Cu thickness on vias 0.025 mm.
22/31
Doc ID 17074 Rev 5
VNH5180A-E
Package and PCB thermal data
Figure 16. Chipset configuration
CHIP 1
RthA
RthAB
RthAC
CHIP 3
CHIP 2
RthB
RthBC
RthC
Figure 17. Auto and mutual Rthj-amb vs PCB copper area in open box free air
condition
80
RthA
RthB = RthC
RthAB = RthAC
RthBC
70
60
°C/W
50
40
30
20
10
0
0
4.1.1
1
2
3
4
5
6
cm 2 of Cu Area (refer to PCB layout)
7
8
9
Thermal calculation in clockwise and anti-clockwise operation in
steady-state mode
Table 18.
Thermal calculation in clockwise and anti-clockwise operation in steadystate mode
HSA HSB LSA LSB
TjHSAB
TjLSA
TjLSB
ON OFF OFF ON
PdHSA x RthHS + PdLSB PdHSA x RthHSLS +
x RthHSLS + Tamb
PdLSB x RthLSLS + Tamb
PdHSA x RthHSLS + PdLSB
x RthLS + Tamb
OFF ON
PdHSB x RthHS + PdLSA PdHSB x RthHSLS +
x RthHSLS + Tamb
PdLSA x RthLS + Tamb
PdHSB x RthHSLS + PdLSA
x RthLSLS + Tamb
ON OFF
Doc ID 17074 Rev 5
23/31
Package and PCB thermal data
4.1.2
VNH5180A-E
Thermal calculation in transient mode
Ths = Pdhs • Zhs + Zhsls • (PdlsA + PdlsB) + Tamb
TlsA = PdlsA • Zls + Pdhs • Zhsls + PdlsB • Zhsls + Tamb
TlsB = PdlsB • Zls + Pdhs • Zhsls + PdlsA • Zhsls + Tamb
Figure 18. Detailed chipset configuration
CHIP 1
Zts
Zhsls
Zhsls
CHIP 3
CHIP 2
Zls
Zlsls
Equation 1: pulse calculation formula
Z
THδ
= R
TH
⋅δ+Z
THtp
(1 – δ)
where
δ = tp ⁄ T
24/31
Doc ID 17074 Rev 5
Zls
VNH5180A-E
Package and PCB thermal data
Figure 19.
PowerSSO-36 HSD thermal impedance junction ambient single pulse
ZTH -HSD @ cu area
100
HSD-8 cm^2 Cu
HSD-2 cm^2 Cu
HSD-footprint
HsLsD-8 cm^2 Cu
HsLsD-2 cm^2 Cu
HsLsD-footprint
°C/W
10
1
0.1
0.001
0.01
0.1
tim e (sec)
1
10
100
1000
Figure 20. PowerSSO-36 LSD thermal impedance junction ambient single pulse
ZTH -LSD @ cu area
100
LSD-8 cm^2 Cu
LSD-2 cm^2 Cu
LSD-footprint
LsLsD-8 cm^2 Cu
LsLsD-2 cm^2 Cu
LsLsD-footprint
10
°C/W
Z ls
Z lsls
1
0.1
0.001
0.01
0.1
tim e (sec)
1
Doc ID 17074 Rev 5
10
100
1000
25/31
Package and PCB thermal data
VNH5180A-E
Figure 21. Thermal fitting model of an H-bridge in PowerSSO-36
Thermal parameters(1)
Table 19.
Area/island (cm2)
Footprint
R1 = R7 (°C/W)
0.4
R2 = R8 (°C/W)
3.5
8
R3 (°C/W)
8
R4 (°C/W)
30
16
11
R5 (°C/W)
40
30
14
R6 (°C/W)
36
34
21
R9 = R15 (°C/W)
0.1
R10 = R16 (°C/W)
5.2
R11 = R17 (°C/W)
32
14
14
R12 = R18 (°C/W)
49
21
21
R13 = R19 (°C/W)
52
36
24
R14 = R20 (°C/W)
50
40
33
80
77
75
R21 = R22 = R23 (°C/W)
C1 = C7 = C9 = C15 (W.s/°C)
0.0005
C2 = C8 (W.s/°C)
0.008
C3 (W.s/°C)
0.09
C4 (W.s/°C)
0.5
0.8
0.8
C5 (W.s/°C)
0.8
1.4
2
7
8
10
C6 (W.s/°C)
C10 = C16 (W.s/°C)
0.009
C11 = C17 (W.s/°C)
0.09
0.07
0.07
C12 = C18 (W.s/°C)
0.45
0.45
0.45
C13 = C19 (W.s/°C)
0.8
1.2
1.4
C14 = C20 (W.s/°C)
4
5
8
0.005
0.003
0.003
C21 = C22 = C23 (W.s/°C)
1. The blank space means that the value is the same as the previous one.
26/31
2
Doc ID 17074 Rev 5
VNH5180A-E
Package and packing information
5
Package and packing information
5.1
ECOPACK®
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
5.2
PowerSSO-36 TP package information
Figure 22. PowerSSO-36 TP package dimensions
Doc ID 17074 Rev 5
27/31
Package and packing information
Table 20.
VNH5180A-E
PowerSSO-36 TP mechanical data
Millimeters
Symbol
Min.
Typ.
Max.
A
2.15
-
2.47
A2
2.15
-
2.40
a1
0
-
0.1
b
0.18
-
0.36
c
0.23
-
0.32
D
10.10
-
10.50
E
7.4
-
7.6
e
-
0.5
-
e3
-
8.5
-
F
2.3
G
-
-
0.1
H
10.1
-
10.5
h
-
-
0.4
k
0 deg
L
0.6
M
N
28/31
8 deg
-
1
4.3
-
-
O
1.2
Q
0.8
S
2.9
T
3.65
U
1.0
10 deg
X1
1.85
2.35
Y1
3
3.5
X2
1.85
2.35
Y2
3
3.5
X3
4.7
-
5.2
Y3
3
-
3.5
Z1
0.4
Z2
0.4
Doc ID 17074 Rev 5
VNH5180A-E
5.3
Package and packing information
PowerSSO-36 TP packing information
Figure 23. PowerSSO-36 TP tube shipment (no suffix)
Base Qty
Bulk Qty
Tube length (±0.5)
A
B
C (±0.1)
C
B
49
1225
532
3.5
13.8
0.6
All dimensions are in mm.
A
Figure 24. PowerSSO-36 TP tape and reel shipment (suffix “TR”)
Reel dimensions
Base Qty
Bulk Qty
A (max)
B (min)
C (±0.2)
F
G (+2 / -0)
N (min)
T (max)
1000
1000
330
1.5
13
20.2
24.4
100
30.4
Tape dimensions
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width
Tape Hole Spacing
Component Spacing
Hole Diameter
Hole Diameter
Hole Position
Compartment Depth
Hole Spacing
W
P0 (±0.1)
P
D (±0.05)
D1 (min)
F (±0.1)
K (max)
P1 (±0.1)
24
4
12
1.55
1.5
11.5
2.85
2
End
All dimensions are in mm.
Start
Top
cover
tape
No components Components
500mm min
No components
500mm min
Empty components pockets
sealed with cover tape.
User direction of feed
Doc ID 17074 Rev 5
29/31
Revision history
6
VNH5180A-E
Revision history
Table 21.
Document revision history
Date
Revision
11-Feb-2010
1
Initial release.
2
Updated following tables:
– Table 7: Thermal data
– Table 8: Power section
– Table 12: Current sense (9 V < VCC < 18 V)
13-Oct-2010
3
Updated Chapter 3: Application information
Updated following tables:
– Table 18: Thermal calculation in clockwise and anti-clockwise
operation in steady-state mode
– Table 19: Thermal parameters
20-Oct-2010
4
Changed document status from target specification to definitive
datasheet
5
Updated Figure 1: Block diagram
Added Table 3: Suggested connections for unused and not
connected pins
Table 11: Protections and diagnostics:
– TTSD, TTR, THYST: added note
Updated Figure 9: Waveforms in full-bridge operation and
Figure 10: Waveforms in full-bridge operation (continued)
28-Sep-2010
22-Dec-2011
30/31
Changes
Doc ID 17074 Rev 5
VNH5180A-E
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