STMICROELECTRONICS VNH2SP30

VNH2SP30-E
AUTOMOTIVE FULLY INTEGRATED
H-BRIDGE MOTOR DRIVER
Table 1. General Features
Type
RDS(on)
VNH2SP30-E
19 mΩ max
(per leg)
■
Figure 1. Package
Iout
Vccmax
30 A
41 V
OUTPUT CURRENT: 30A
5V LOGIC LEVEL COMPATIBLE INPUTS
■ UNDERVOLTAGE AND OVERVOLTAGE
SHUT-DOWN
■ OVERVOLTAGE CLAMP
■ THERMAL SHUT DOWN
■ CROSS-CONDUCTION PROTECTION
■ LINEAR CURRENT LIMITER
■ VERY LOW STAND-BY POWER
CONSUMPTION
■ PWM OPERATION UP TO 20 KHz
■ PROTECTION AGAINST:
LOSS OF GROUND AND LOSS OF VCC
■ CURRENT SENSE OUTPUT PROPORTIONAL
TO MOTOR CURRENT
■ IN COMPLIANCE WITH THE 2002/95/EC
EUROPEAN DIRECTIVE
■
MultiPowerSO-30
The Low-Side switches are vertical MOSFETs
manufactured
using
STMicroelectronic’s
proprietary EHD (‘STripFET™’) process.The three
dice are assembled in MultiPowerSO-30 package
on electrically isolated leadframes. This package,
specifically designed for the harsh automotive
environment offers improved thermal performance
thanks to exposed die pads. Moreover, its fully
symmetrical mechanical design allows superior
manufacturability at board level. The input signals
IN A and IN B can directly interface to the
microcontroller to select the motor direction and
the brake condition. The DIAG A/ENA or DIAGB/
EN B, when connected to an external pull-up
resistor, enable one leg of the bridge. They also
provide a feedback digital diagnostic signal. The
normal condition operation is explained in the truth
table on page 14. The CS pin allows to monitor the
motor current by delivering a current proportional
to its value. The PWM, up to 20KHz, lets us to
control the speed of the motor in all possible
conditions. In all cases, a low level state on the
PWM pin will turn off both the LSA and LSB
switches. When PWM rises to a high level, LSA or
LSB turn on again depending on the input pin
state.
DESCRIPTION
The VNH2SP30-E is a full bridge motor driver
intended for a wide range of automotive
applications. The device incorporates a dual
monolithic High-Side drivers and two Low-Side
switches. The High-Side driver switch is designed
using STMicroelectronic’s well known and proven
proprietary VIPower™ M0 technology that allows
to efficiently integrate on the same die a true
Power MOSFET with an intelligent signal/
protection circuitry.
Table 2. Order Codes
Package
MultiPowerSO-30
Tube
VNH2SP30-E
Tape and Reel
VNH2SP30TR-E
Rev. 1
September 2004
1/26
VNH2SP30-E
Figure 2. Block Diagram
VCC
OV + UV
OVERTEMPERATURE A
OVERTEMPERATURE B
CLAMP HSA
HSA
CLAMP HSB
DRIVER
HSA
CURRENT
LIMITATION A
OUTA
CURRENT
LIMITATION B
1/K
1/K
CLAMP LSA
OUTB
CLAMP LSB
DRIVER
LSA
LSA
HSB
DRIVER
HSB
LOGIC
DRIVER
LSB
DIAGA/ENA INA
GNDA
CS
PWM INB DIAGB/ENB
LSB
GNDB
Figure 3. Configuration Diagram (Top View)
OUTA
Nc
VCC
Nc
1
OUTA
Heat Slug3
INA
ENA/DIAGA
Nc
Nc
OUTB
CS
ENB/DIAGB
INB
Nc
VCC
2/26
OUTA
Nc
GNDA
GNDA
GNDA
OUTA
Nc
VCC
VCC
Heat Slug1
PWM
Nc
OUTB
30
GNDB
GNDB
OUTB
Heat Slug2
15
GNDB
16
Nc
OUTB
VNH2SP30-E
Table 3. Pin Definitions And Functions
Pin No
1, 25, 30
2,4,7,12,14,17, 22, 24,29
3, 13, 23
6
5
8
9
11
10
15, 16, 21
26, 27, 28
18, 19, 20
Symbol
OUTA, Heat
Slug2
NC
VCC, Heat
Slug1
ENA/DIAGA
INA
PWM
CS
INB
ENB/DIAGB
OUTB, Heat
Slug3
GNDA
GNDB
Function
Source of High-Side Switch A / Drain of Low-Side Switch A
Not connected
Drain of High-Side Switches and Power Supply Voltage
Status of High-Side and Low-Side Switches A; Open Drain Output
Clockwise Input
PWM Input
Output of Current sense
Counter Clockwise Input
Status of High-Side and Low-Side Switches B; Open Drain Output
Source of High-Side Switch B / Drain of Low-Side Switch B
Source of Low-Side Switch A (*)
Source of Low-Side Switch B (*)
Note: (*) GNDA and GNDB must be externally connected together
Table 4. Pin Functions Description
Name
VCC
GNDA
GNDB
OUTA
OUTB
INA
INB
PWM
ENA/DIAGA
ENB/DIAGB
CS
Description
Battery connection.
Power grounds, must always be externally connected together.
Power connections to the motor.
Voltage controlled input pins with hysteresis, CMOS compatible. These two pins control the state of
the bridge in normal operation according to the truth table (brake to VCC, Brake to GND, clockwise and
counterclockwise).
Voltage controlled input pin with hysteresis, CMOS compatible.Gates of Low-Side FETS get
modulated by the PWM signal during their ON phase allowing speed control of the motor
Open drain bidirectional logic pins.These pins must be connected to an external pull up resistor. When
externally pulled low, they disable half-bridge A or B. In case of fault detection (thermal shutdown of
a High-Side FET or excessive ON state voltage drop across a Low-Side FET), these pins are pulled
low by the device (see truth table in fault condition).
Analog current sense output. This output sources a current proportional to the motor current. The
information can be read back as an analog voltage across an external resistor.
3/26
VNH2SP30-E
Table 5. Block Descriptions (see Block Diagram)
Name
Description
Allows the turn-on and the turn-off of the High Side and the Low Side
switches according to the truth table.
Shut-down the device outside the range [5.5V..16V] for the battery voltage.
Protect the High Side and the Low Side switches from the high voltage on
the battery line in all configuration for the motor.
Drive the gate of the concerned switch to allow a proper RDS(on) for the leg
of the bridge.
Limits the motor current, by reducing the High Side Switch gate-source
voltage when short-circuit to ground occurs.
In case of short-circuit with the increase of the junction’s temperature,
shuts-down the concerned High Side to prevent its degradation and to
protect the die.
Signalize an abnormal behavior of the switches in the half-bridge A or B by
pulling low the concerned ENx/DIAGx pin.
LOGIC CONTROL
OVERVOLTAGE + UNDERVOLTAGE
HIGH SIDE AND LOW SIDE CLAMP
VOLTAGE
HIGH SIDE AND LOW SIDE DRIVER
LINEAR CURRENT LIMITER
OVERTEMPERATURE PROTECTION
FAULT DETECTION
Table 6. Absolute Maximum Rating
Symbol
VCC
Imax
IR
IIN
IEN
Ipw
VCS
VESD
Tj
Tc
TSTG
Parameter
Supply Voltage
Maximum Output Current (continuous)
Reverse Output Current (continuous)
Input Current (INA and INB pins)
Enable Input Current (DIAGA/ENA and DIAGB/ENB pins)
PWM Input Current
Current Sense Maximum Voltage
Electrostatic Discharge (R=1.5kΩ, C=100pF)
Value
+ 41
30
-30
+/- 10
+/- 10
+/- 10
-3/+15
- CS pin
2
kV
- logic pins
4
kV
5
Internally Limited
-40 to 150
-55 to 150
kV
°C
°C
°C
- output pins: OUTA, OUTB, VCC
Junction Operating Temperature
Case Operating Temperature
Storage Temperature
Figure 4. Current and Voltage Conventions
IS
VCC
IINA
VCC
INA
IINB
IENB
VINA
VINB
IOUTA
OUTA
IN B
IENA
OUTB
DIAGA/ENA
CS
DIAGB/ENB
PWM
Ipw
GND A GNDB
VENA
GND
Vpw
IOUTB
IGND
VOUTA
ISENSE
VSENSE
VENB
4/26
Unit
V
A
A
mA
mA
mA
V
VOUTB
VNH2SP30-E
Table 7. Thermal Data
See MultiPowerSO-30 Thermal Data section (page )
ELECTRICAL CHARACTERISTICS
(VCC=9V up to 16V; -40°C<Tj<150°C; unless otherwise specified)
Table 8. Power
Symbol
Parameter
VCC
Operating supply voltage
Test Conditions
Min.
Typ.
Max.
Unit
16
V
30
µA
60
µA
INA or INB=5V, no PWM
10
mA
5.5
Off state:
INA=INB=PWM=0; Tj=25 °C;
VCC=13V
IS
Supply Current
12
INA=INB=PWM=0
On state:
RONHS
Static High-Side
resistance
IOUT=15A; Tj=25°C
14
mΩ
IOUT=15A; Tj= - 40 to 150°C
28
mΩ
RONLS
Static Low-Side
resistance
IOUT=15A; Tj=25°C
5
mΩ
IOUT=15A; Tj= - 40 to 150°C
10
mΩ
1.1
V
Tj=25°C; VOUTX=ENX=0V; VCC=13V
3
µA
Tj=125°C; VOUTX=ENX=0V; VCC=13V
5
µA
Vf
IL(off)
High Side Free-wheeling
Diode Forward Voltage
High Side Off State
Output Current (per
channel)
If=15A
0.8
Dynamic
IRM
Cross-conduction
IOUT=15A (see fig. 8)
0.7
A
Current
Table 9. Logic Inputs (INA, INB, ENA, ENB)
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
VIL
Input Low Level Voltage
Normal operation (DIAGX/ENX pin acts
as an input pin)
1.25
V
VIH
Input High Level Voltage
Normal operation (DIAGX/ENX pin acts
as an input pin)
3.25
V
VIHYST
Input Hysteresis Voltage
Normal operation (DIAGX/ENX pin acts
as an input pin)
0.5
V
IIN=1mA
5.5
6.3
7.5
V
IIN=-1mA
-1.0
-0.7
-0.3
V
VICL
Input Clamp Voltage
IINL
Input Current
VIN=1.25 V
IINH
Input Current
VIN=3.25 V
10
µA
Enable Output Low Level
Voltage
Fault operation (DIAGX/ENX pin acts as
an output pin); IEN=1mA
0.4
V
VDIAG
µA
1
5/26
VNH2SP30-E
ELECTRICAL CHARACTERISTICS (continued)
Table 10. PWM
Symbol
Vpwl
Ipwl
Vpwh
Ipwh
Vpwhhyst
Vpwcl
CINPWM
PWM
PWM
PWM
PWM
PWM
Parameter
Low Level Voltage
Pin Current
High Level Voltage
Pin Current
Hysteresis Voltage
PWM Clamp Voltage
PWM Pin Input
Capacitance
Test Conditions
Vpw=1.25V
Min
Typ
Max
1.25
1
3.25
Vpw=3.25V
10
Ipw = 1 mA
0.5
VCC+0.3
Ipw = -1 mA
-6.0
VCC+0.7 VCC+1.0
-4.5
VIN =2.5V
Unit
V
µA
V
µA
V
V
-3.0
V
25
pF
Table 11. Switching (VCC=13V, RLOAD=0.87Ω)
Symbol
f
td(on)
td(off)
tr
tf
tDEL
trr
Parameter
PWM Frequency
Turn-on Delay Time
Turn-off Delay Time
Rise Time
Fall Time
Delay Time During Change of
Operating Mode
High Side Free Wheeling
Diode Reverse Recovery Time
Test Conditions
Min
0
Input rise time < 1µs (see fig. 8)
Input rise time < 1µs (see fig. 8)
(see fig. 7)
(see fig. 7)
(see fig. 6)
300
(see fig. 9)
Typ
1
1.2
Max
20
250
250
1.6
2.4
Unit
kHz
µs
µs
µs
µs
600
1800
µs
110
ns
9V<VCC<16V;
toff(min)
PWM Minimum off time
-40°C<Tj<150°C;
6
µs
Max
5.5
Unit
V
IOUT =15A
Table 12. Protection And Diagnostic
Symbol
VUSD
VOV
ILIM
VCLP
TTSD
TTR
THYST
6/26
Parameter
Undervoltage Shut-down
Undervoltage Reset
Overvoltage Shut-down
High-Side Current Limitation
Total Clamp Voltage
(VCC to GND)
Thermal Shut-down
Temperature
Thermal Reset Temperature
Thermal Hysteresis
Test Conditions
Min
Typ
16
30
4.7
19
50
22
70
V
V
A
IOUT=15A
43
48
54
V
VIN = 3.25 V
150
175
200
°C
135
7
15
°C
°C
VNH2SP30-E
ELECTRICAL CHARACTERISTICS (continued)
Table 13. Current Sense (9V<VCC<16V)
Symbol
Parameter
K1
IOUT/ISENSE
K2
IOUT/ISENSE
Test Conditions
IOUT =30A; RSENSE=1.5kΩ
Tj= - 40 to 150°C
IOUT =8A; RSENSE=1.5kΩ
dK1 / K1 (*) Analog sense current drift
dK2 / K2 (*) Analog sense current drift
ISENSEO
Analog Sense Leakage
Current
Tj= - 40 to 150°C
IOUT =30A; RSENSE=1.5kΩ
Tj= - 40 to 150°C
IOUT >8A; RSENSE=1.5kΩ
Tj= - 40 to 150°C
IOUT =0A; VSENSE=0V;
Tj= - 40 to 150°C
Min
Typ
Max
9665
11370
13075
9096
11370
13644
Unit
-8
+8
%
-10
+10
%
0
65
µA
Note:(*) Analog sense current drift is deviation of factor K for a given device over (-40°C to 150°C and 9V<VCC<16V) with respect to it’s
value measured at T j=25°C, VCC=13V.
WAVEFORMS AND TRUTH TABLE
Table 14. Truth Table In Normal Operating Conditions
In normal operating conditions the DIAGX/ENX pin is
considered as an input pin by the device. This pin must be
externally pulled high.
PWM pin usage: in all cases, a “0” on the PWM pin will
turn-off both LSA and LSB switches. When PWM rises
back to “1”, LSA or LSB turn on again depending on the
input pin state.
INA
INB
DIAGA/ENA
DIAGB/ENB
OUTA
OUTB
CS
1
1
1
0
1
1
1
1
H
H
H
L
High Imp.
ISENSE=I OUT/K
0
1
1
1
L
H
ISENSE=I OUT/K
0
0
1
1
L
L
High Imp.
Operating mode
Brake to VCC
Clockwise (CW)
Counterclockwise
(CCW)
Brake to GND
7/26
VNH2SP30-E
Figure 5. Typical Application Circuit For Dc To 20khz PWM OperationShort Circuit Protection
VCC
Reg 5V
+5V
+ 5V
VCC
3.3K
3.3K
DIAGB/ENB
1K
1K
DIAGA/ENA
1K
HSA
HSB
PWM
µC
OUTA
OUTB
INA
1K
INB
LSA
CS
10K
33nF
1K
LSB
> 50uF
M
1.5K
GNDB
GNDA
S
100K
G
b) N MOSFET
D
In case of a fault condition the DIAGX/ENX pin is
considered as an output pin by the device.
The fault conditions are:
- overtemperature on one or both high sides (for example
if a short to ground occurs as it could be the case
described in line 1 and 2 in the table below);
- short to battery condition on the output (saturation
detection on the Low-Side Power MOSFET).
which power element is in fault by monitoring the IN A,
INB, DIAGA/ENA and DIAGB/ENB pins.
In any case, when a fault is detected, the faulty leg of the
bridge is latched off. To turn-on the respective output
(OUTX) again, the input signal must rise from low to high
level.
Possible origins of fault conditions may be:
OUTA is shorted to ground ---> overtemperature
detection on high side A.
OUTA is shorted to VCC ---> Low-Side Power MOSFET
saturation detection.
When a fault condition is detected, the user can know
Table 15. Truth Table In Fault Conditions (Detected On OUTA)
INA
INB
DIAGA/ENA
DIAGB/ENB
OUTA
OUTB
CS
1
1
0
1
OPEN
H
High Imp.
1
0
0
1
OPEN
L
High Imp.
0
1
0
1
OPEN
H
IOUTB/K
0
0
0
1
OPEN
L
High Imp.
X
X
0
0
OPEN
OPEN
High Imp.
X
1
0
1
OPEN
H
IOUTB/K
X
0
0
1
OPEN
L
High Imp.
Fault Information
8/26
Protection Action
VNH2SP30-E
Table 16. Electrical Transient Requirements
ISO T/R
7637/1
Test Pulse
1
2
3a
3b
4
5
ISO T/R
7637/1
Test Pulse
1
2
3a
3b
4
5
Class
C
E
Test Level
Test Level
Test Level
Test Level
Test Levels
I
II
III
IV
Delays and Impedance
-25V
+25V
-25V
+25V
-4V
+26.5V
-50V
+50V
-50V
+50V
-5V
+46.5V
-75V
+75V
-100V
+75V
-6V
+66.5V
-100V
+100V
-150V
+100V
-7V
+86.5V
2ms, 10Ω
0.2ms, 10Ω
0.1µs, 50Ω
0.1µs, 50Ω
100ms, 0.01Ω
400ms, 2Ω
Test Levels Result
Test Levels Result
Test Levels Result
Test Levels Result
I
II
III
IV
C
C
C
C
C
C
C
C
C
C
C
E
C
C
C
C
C
E
C
C
C
C
C
E
Contents
All functions of the device are performed as designed after exposure to disturbance.
One or more functions of the device are not performed as designed after exposure to disturbance
and cannot be returned to proper operation without replacing the device.
Reverse Battery Protection
Three possible solutions can be thought of:
a) a Schottky diode D connected to V CC pin
b) a N-channel MOSFET connected to the GND
pin (see Typical Application Circuit on page 8)
c) a P-channel MOSFET connected to the VCC pin
The device sustains no more than -30A in reverse
battery conditions because of the two Body diodes
of the Power MOSFETs. Additionally, in reverse
battery condition the I/Os of VNH2SP30-E will be
pulled down to the VCC line (approximately -1.5V).
Series resistor must be inserted to limit the current
sunk from the microcontroller I/Os. If IRmax is the
maximum target reverse current through µC I/Os,
series resistor is:
V
–V
IOs
CC
R = --------------------------------I
Rmax
9/26
VNH2SP30-E
Figure 6. Definition Of The Delay Times Measurement
VINA,
t
VINB
t
PWM
t
ILOAD
tDEL
tDEL
t
Figure 7. Definition Of The Low Side Switching Times
PWM
t
VOUTA, B
90%
tf
10/26
80%
20%
10%
tr
t
VNH2SP30-E
Figure 8. Definition Of The High Side Switching Times
VINA,
tD(on)
tD(off)
t
VOUTA
90%
10%
t
Figure 9. Definition Of Dynamic Cross Conduction Current During A Pwm Operation
IN A=1, IN B=0
PWM
t
IMOTOR
t
VOUTB
t
ICC
IRM
t
trr
11/26
VNH2SP30-E
Figure 10. Waveforms in full bridge operation
NORMAL OPERATION (DIAGA/ENA=1, DIAGB/ENB=1)
LOAD CONNECTED BETWEEN OUTA, OUTB
DIAGA/ENA
DIAGB/ENB
INA
INB
PWM
OUTA
OUTB
IOUTA->OUTB
CS (*)
tDEL
tDEL
(*) CS BEHAVIOUR DURING PWM MODE WILL DEPEND ON PWM FREQUENCY AND DUTY CYCLE
NORMAL OPERATION (DIAGA/ENA=1, DIAGB/ENB=0 and DIAGA/ENA=0, DIAGB/ENB=1)
LOAD CONNECTED BETWEEN OUTA, OUTB
DIAGA/ENA
DIAGB/ENB
INA
INB
PWM
OUTA
OUTB
IOUTA->OUTB
CS
CURRENT LIMITATION/THERMAL SHUTDOWN or OUTA SHORTED TO GROUND
INA
INB
ILIM
IOUTA->OUTB
TTSD
TTR
Tj > TTR
Tj
DIAGA/ENA
DIAGB/ENB
CS
normal operation
12/26
OUTA shorted to ground
normal operation
VNH2SP30-E
Figure 11. Waveforms In Full Bridge Operation (continued)
OUTA shorted to VCC and undervoltage shutdown
INA
INB
undefined
OUTA
OUTB
undefined
IOUTA->OUTB
DIAGB/ENB
DIAGA/ENA
CS
V<nominal
normal operation
OUTA shorted to VCC
normal operation
undervoltage shutdown
13/26
VNH2SP30-E
Figure 12. Half-bridge Configuration
The VNH2SP30-E can be used as a high power half-bridge driver achieving an On resistance
per leg of 9.5mΩ. Suggested configuration is the following:
VCC
INA
INB
DIAGA/ENA
DIAGB/ENB
PWM
INA
INB
DIAGA/ENA
DIAGB/ENB
PWM
OUTA
M
OUTB
GNDA
GNDA
GNDB
OUTB
OUTA
GNDB
Figure 13. Multi-motors Configuration
The VNH2SP30-E can easily be designed in multi-motors driving applications such as seat
positioning systems where only one motor must be driven at a time. DIAG X/EN X pins allow
to put unused half-bridges in high impedance. Suggested configuration is the following:
VCC
INA
INB
DIAGA/ENA
DIAGB/ENB
PWM
INA
INB
DIAGA/ENA
DIAGB/ENB
PWM
OUTA
OUTB
GNDA
GNDB
M1
14/26
M2
OUTB
OUTA
GNDA
GNDB
M3
VNH2SP30-E
Figure 17. Off State Supply Current
Figure 14. On State Supply Current
Is (mA)
Is (µA)
6
50
5.5
45
Vcc=13V
INA or INB=5V
5
Vcc=13V
40
4.5
35
4
3.5
30
3
25
2.5
20
2
15
1.5
10
1
5
0.5
0
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
Tc (°C)
50
75
100
125
150
175
125
150
175
150
175
Tc (°C)
Figure 18. Input Clamp Voltage
Figure 15. High Level Input Current
Iinh (µA)
Vicl (V)
5
8
4.5
7.75
Vin=3.25V
Iin =1mA
7.5
4
7.25
3.5
7
3
6.75
2.5
6.5
2
6.25
6
1.5
5.75
1
5.5
0.5
5.25
0
5
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
Tc (°C)
50
75
100
Tc (°C)
Figure 16. Input High Level Voltage
Figure 19. Input Low Level Voltage
Vih (V)
Vil (V)
3
3
2.9
2.75
2.8
2.5
2.7
2.25
2.6
2.5
2
2.4
1.75
2.3
1.5
2.2
1.25
2.1
2
1
-50
-25
0
25
50
75
Tc (°C)
100
125
150
175
-50
-25
0
25
50
75
100
125
Tc (°C)
15/26
VNH2SP30-E
Figure 20. Input Hysteresis Voltage
Figure 23. High Level Enable Pin Current
Vihyst (V)
Ienh (µA)
2
8
1.75
7
Vcc=13V
Ven=3.25V
1.5
6
1.25
5
1
4
0.75
3
0.5
2
0.25
1
0
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
Tc (°C)
50
75
100
125
150
175
Tc (°C)
Figure 21. Delay Time during change of
operation mode
Figure 24. Enable Clamp Voltage
tdel (µs)
Vencl (V)
1000
-0.2
900
-0.3
800
Ien=-1mA
-0.4
700
600
-0.5
500
-0.6
400
-0.7
300
-0.8
200
-0.9
100
0
-1
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
Tc (°C)
75
100
125
150
175
Tc (°C)
Figure 22. High Level Enable Voltage
Figure 25. Low Level Enable Voltage
Venh (V)
Venl (V)
3.6
3
3.4
2.8
Vcc=9V
Vcc=9V
3.2
2.6
3
2.4
2.8
2.2
2.6
2
2.4
1.8
2.2
1.6
2
1.4
1.8
1.2
1.6
1
-50
-25
0
25
50
75
Tc (°C)
16/26
50
100
125
150
175
-50
-25
0
25
50
75
Tc (°C)
100
125
150
175
VNH2SP30-E
Figure 26. PWM High Level Voltage
Figure 29. PWM Low Level Voltage
Vpwh (V)
Vpwl (V)
5
2.6
4.5
2.4
Vcc=9V
Vcc=9V
4
2.2
3.5
2
3
1.8
2.5
2
1.6
1.5
1.4
1
1.2
0.5
0
1
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
Tc (°C)
50
75
100
125
150
175
Tc (°C)
Figure 27. PWM High Level Current
Figure 30. Overvoltage Shutdown
Ipwh (µA)
Vov (V)
8
30
7
27.5
Vcc=9V
Vpw=3.25V
6
25
5
22.5
4
20
3
17.5
2
15
1
12.5
0
10
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
Tc (°C)
50
75
100
125
150
175
100
125
150
175
Tc (°C)
Figure 28. Undervoltage Shutdown
Figure 31. Current Limitation
Vusd(V)
Ilim (A)
8
80
75
7
70
6
65
5
60
4
55
50
3
45
2
40
1
35
0
30
-50
-25
0
25
50
75
Tc (°C)
100
125
150
175
-50
-25
0
25
50
75
Tc (°C)
17/26
VNH2SP30-E
Figure 32. On State High Side Resistance Vs.
Tcase
Figure 35. On State Low Side Resistance Vs.
Tcase
Ronhs (mOhm)
Ronls (mOhm)
40
40
35
35
Vcc=9V; 16V
Iout=15A
30
Iload=12A
Vcc=9V; 13V; 18V
30
25
25
20
20
15
15
10
10
5
5
0
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
Tc (°C)
50
75
100
125
150
175
125
150
175
Tc (ºC)
Figure 33. Turn-on Delay Time
Figure 36. Turn-off Delay Time
td(on) (µs)
td(off) (µs)
260
200
240
190
220
180
200
170
180
160
160
150
140
140
120
130
100
120
80
110
60
100
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
Tc (°C)
50
75
100
Tc (°C)
Figure 34. Output Voltage Rise Time
Figure 37. Output Voltage Fall Time
tr (µs)
tf (µs)
2
8
1.8
7
1.6
6
1.4
5
1.2
4
1
3
0.8
0.6
2
0.4
1
0.2
0
-50
-25
0
25
50
75
Tc (°C)
18/26
100
125
150
175
-50
-25
0
25
50
75
Tc (°C)
100
125
150
175
VNH2SP30-E
MultiPowerSO-30™ Thermal Data
Figure 38. MultiPowerSO-30™ PC Board
Layout condition of Rth and Zth measurements (PCB FR4 area= 58mm x 58mm, PCB thickness=2mm,
Cu thickness=35µm, Copper areas: from minimum pad lay-out to 16cm2).
Figure 39. Chipset Configuration
HIGH SIDE
CHIP
HSAB
LOW SIDE
CHIP A
LOW SIDE
CHIP B
LSA
LSB
Figure 40. Auto and mutual Rthj-amb Vs PCB copper area in open box free air condition (according
to page 20 definitions)
45
RthHS
RthLS
RthHSLS
RthLSLS
40
35
30
25
20
°C/W
15
10
5
0
0
5
10
15
cm2 of Cu Area (refer to PCB layout)
20
19/26
VNH2SP30-E
Table 17. Thermal Calculation In Clockwise And Anti-clockwise Operation In Steady-state Mode
HSA
HSB
LSA
LSB
ON
OFF
OFF
ON
OFF
ON
ON
OFF
Thermal
Resistances
TjHSAB
PdHSA x RthHS + PdLSB x
RthHSLS + Tamb
PdHSB x RthHS + PdLSA x
RthHSLS + Tamb
Definition
(values
TjLSA
PdHSA x RthHSLS + PdLSB x
RthLSLS + Tamb
PdHSB x RthHSLS + PdLSA x
RthLS + Tamb
TjLSB
PdHSA x RthHSLS + PdLSB x
RthLS + Tamb
PdHSB x RthHSLS + PdLSA x
RthLSLS + Tamb
Single Pulse Thermal Impedance Definition
according to the PCB heatsink area)
(values according to the PCB heatsink area)
RthHS = RthHSA = RthHSB = High Side Chip
ZthHS = High Side Chip Thermal Impedance
Thermal Resistance Junction to Ambient (HS A or
Junction to Ambient
HSB in ON state)
ZthLS = ZthLSA = ZthLSB = Low Side Chip Thermal
RthLS = R thLSA = R thLSB = Low Side Chip Thermal
Impedance Junction to Ambient
Resistance Junction to Ambient
ZthHSLS = ZthHSABLSA = ZthHSABLSB = Mutual
RthHSLS = RthHSALSB = RthHSBLSA = Mutual
Thermal Impedance Junction to Ambient between
Thermal Resistance Junction to Ambient between
High Side and Low Side Chips
High Side and Low Side Chips
ZthLSLS = ZthLSALSB = Mutual Thermal Impedance
Junction to Ambient between Low Side Chips
RthLSLS = RthLSALSB = Mutual Thermal Resistance
Junction to Ambient between Low Side Chips
Thermal Calculation In Transient Mode (*)
Pulse Calculation Formula
TjHSAB = ZthHS x PdHSAB + ZthHSLS x (PdLSA +
Z THδ
PdLSB) + Tamb
where
=
R TH ⋅ δ + Z THtp ( 1 – δ )
δ = tp ⁄ T
TjLSA = ZthHSLS x PdHSAB + ZthLS x PdLSA + ZthLSLS
x PdLSB + T amb
TjLSB = ZthHSLS x PdHSAB + ZthLSLS x PdLSA + ZthLS
x PdLSB + T amb
20/26
(*) Calculation is valid in any dynamic operating
condition. Pd values set by user.
VNH2SP30-E
Figure 41. MultiPowerSO-30 HSD Thermal Impedance Junction Ambient Single Pulse
100
Footprint
4 cm2
8 cm2
16 cm2
ZthHS
Footprint
4 cm2
8 cm2
10
16 cm2
°C/W
ZthHSLS
1
0 .1
0 .0 0 1
0 .0 1
0 .1
ti m e ( se c )
1
10
10 0
100 0
Figure 42. MultiPowerSo-30 LSD Thermal Impedance Junction Ambient Single Pulse
100
Footprint
4 cm2
8 cm2
16 cm2
ZthLS
Footprint
4 cm2
8 cm2
16 cm2
10
°C/W
ZthLSLS
1
0 .1
0 .0 0 1
0 .0 1
0 .1
t i m e ( se c )
1
10
100
1000
21/26
VNH2SP30-E
Figure 43. Thermal fitting model of an H-Bridge in MultiPowerSO-30
Table 18. Thermal Parameter (*)
Area/island (cm2)
R1=R7 (°C/W)
R2=R8 (°C/W)
R3 (°C/W)
R4 (°C/W)
R5 (°C/W)
R6 (°C/W)
R9=R15 (°C/W)
R10=R16 (°C/W)
R11=R17 (°C/W)
R12=R18 (°C/W)
R13=R19 (°C/W)
R14=R20 (°C/W)
R21=R22=R23 (°C/W)
C1=C7 (W.s/°C)
C2=C8 (W.s/°C)
C3=C11=C17 (W.s/°C)
C4=C13=C19 (W.s/°C)
C5 (W.s/°C)
C6 (W.s/°C)
C9=C15 (W.s/°C)
C10=C16 (W.s/°C)
C12=C18 (W.s/°C)
C14=C20 (W.s/°C)
Footprint
0.05
0.3
0.5
1.3
1.4
44.7
0.2
0.4
0.8
1.5
20
46.9
115
0.005
0.008
0.01
0.3
0.6
5
0.003
0.006
0.075
2.5
Note: (*) The blank space means that the value is the same as the previous one.
22/26
4
8
16
39.1
31.6
23.7
36.1
30.4
20.8
7
9
11
3.5
4.5
5.5
VNH2SP30-E
PACKAGE MECHANICAL
Table 19. MultiPowerSO-30 Mechanical Data
Symbol
millimeters
Min.
Typ
A
A2
Max.
2.35
1.85
2.25
A3
0
0.1
B
0.42
0.58
C
0.23
D
17.1
E
18.85
E1
15.9
e
0.32
17.2
17.3
19.15
16
16.1
1
F1
5.55
6.05
F2
4.6
5.1
F3
9.6
10.1
L
0.8
1.15
N
S
10deg
0deg
7deg
Figure 44. MultiPowerSO-30 Package Dimensions
23/26
VNH2SP30-E
Figure 45. MultiPowerSO-30 Suggested Pad Layout
24/26
VNH2SP30-E
REVISION HISTORY
Date
Revision
Sep. 2004
1
- First issue.
Description of Changes
25/26
VNH2SP30-E
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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
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26/26