VNH3ASP30-E AUTOMOTIVE FULLY INTEGRATED H-BRIDGE MOTOR DRIVER TARGET SPECIFICATION Table 1. General Features TYPE VNH3ASP30-E ■ RDS(on) 42 mΩ max (per leg) Figure 1. Package IOUT Vccmax 30 A 41 V OUTPUT CURRENT: 30A 5V LOGIC LEVEL COMPATIBLE INPUTS UNDERVOLTAGE AND OVERVOLTAGE SHUT-DOWN ■ OVERVOLTAGE CLAMP ■ THERMAL SHUT DOWN ■ CROSS-CONDUCTION PROTECTION ■ LINEAR CURRENT LIMITER ■ VERY LOW STAND-BY POWER CONSUMPTION ■ PWM OPERATION UP TO 20 KHz ■ PROTECTION AGAINST: LOSS OF GROUND AND LOSS OF VCC ■ CURRENT SENSE OUTPUT PROPORTIONAL TO MOTOR CURRENT ■ IN COMPLIANCE WITH THE 2002/95/EC EUROPEAN DIRECTIVE ■ ■ MultiPowerSO-30 The Low-Side switches are vertical MOSFETs manufactured using STMicroelectronic’s proprietary EHD (‘STripFET™’) process. The three dice are assembled in MultiPowerSO-30 package on electrically isolated leadframes. This package, specifically designed for the harsh automotive environment offers improved thermal performance thanks to exposed die pads. Moreover, its fully symmetrical mechanical design allows superior manufacturability at board level. The input signals IN A and INB can directly interface to the microcontroller to select the motor direction and the brake condition. The DIAG A/ENA or DIAGB/ENB, when connected to an external pull-up resistor, enable one leg of the bridge. They also provide a feedback digital diagnostic signal. The normal condition operation is explained in the truth table on page 7. The CS pin allows to monitor the motor current by delivering a current proportional to its value. The PWM, up to 20KHz, lets us to control the speed of the motor in all possible conditions. In all cases, a low level state on the PWM pin will turn off both the LSA and LSB switches. When PWM rises to a high level, LSA or LSB turn on again depending on the input pin state. DESCRIPTION The VNH3ASP30-E is a full bridge motor driver intended for a wide range of automotive applications. The device incorporates a dual monolithic High-Side drivers and two Low-Side switches. The High-Side driver switch is designed using STMicroelectronic’s well known and proven proprietary VIPower™ M0 technology that allows to efficiently integrate on the same die a true Power MOSFET with an intelligent signal/ protection circuitry. Table 2. Order Codes Package MultiPowerSO-30 Tube VNH3ASP30-E Tape and Reel VNH3ASP30TR-E Rev. 1 September 2004 1/18 VNH3ASP30-E Figure 2. Block Diagram VCC OV + UV OVERTEMPERATURE A OVERTEMPERATURE B CLAMP HSA HSA CLAMP HSB DRIVER HSA CURRENT LIMITATION A CURRENT LIMITATION B OUTA 1/K 1/K CLAMP LSA OUTB CLAMP LSB DRIVER LSA LSA HSB DRIVER HSB LOGIC DRIVER LSB DIAGA/ENA INA GNDA CS LSB PWM INB DIAGB/ENB GNDB Figure 3. Configuration Diagram (Top View) OUTA 1 30 Nc VCC Nc GNDA OUTA Heat Slug3 Nc GNDA INA ENA/DIAGA Nc PWM GNDA OUTA Nc VCC CS ENB/DIAGB INB Nc VCC Nc OUTB 2/18 OUTA VCC Heat Slug1 Nc OUTB OUTB Heat Slug2 15 16 GNDB GNDB GNDB Nc OUTB VNH3ASP30-E Table 3. Pin Definitions And Functions Pin No 1, 25, 30 2,4,7,12,14,17, 22, 24,29 3, 13, 23 6 5 8 9 11 10 15, 16, 21 26, 27, 28 18, 19, 20 Symbol OUTA, Heat Slug2 NC VCC, Heat Slug1 ENA/DIAGA INA PWM CS INB ENB/DIAGB OUTB, Heat Slug3 GNDA GNDB Function Source of High-Side Switch A / Drain of Low-Side Switch A Not connected Drain of High-Side Switches and Power Supply Voltage Status of High-Side and Low-Side Switches A; Open Drain Output Clockwise Input PWM Input Output of Current sense Counter Clockwise Input Status of High-Side and Low-Side Switches B; Open Drain Output Source of High-Side Switch B / Drain of Low-Side Switch B Source of Low-Side Switch A (*) Source of Low-Side Switch B (*) Note: (*) GNDA and GNDB must be externally connected together. Table 4. Pin Functions Description Name VCC GNDA GNDB OUTA OUTB INA INB PWM ENA/DIAGA ENB/DIAGB CS Description Battery connection. Power grounds, must always be externally connected together. Power connections to the motor. Voltage controlled input pins with hysteresis, CMOS compatible. These two pins control the state of the bridge in normal operation according to the truth table (brake to VCC, Brake to GND, clockwise and counterclockwise). Voltage controlled input pin with hysteresis, CMOS compatible.Gates of Low-Side FETS get modulated by the PWM signal during their ON phase allowing speed control of the motor Open drain bidirectional logic pins.These pins must be connected to an external pull up resistor. When externally pulled low, they disable half-bridge A or B. In case of fault detection (thermal shutdown of a High-Side FET or excessive ON state voltage drop across a Low-Side FET), these pins are pulled low by the device (see truth table in fault condition). Analog current sense output. This output sources a current proportional to the motor current. The information can be read back as an analog voltage across an external resistor. Table 5. Block Descriptions (see Block Diagram) Name LOGIC CONTROL OVERVOLTAGE + UNDERVOLTAGE HIGH SIDE AND LOW SIDE CLAMP VOLTAGE HIGH SIDE AND LOW SIDE DRIVER LINEAR CURRENT LIMITER OVERTEMPERATURE PROTECTION FAULT DETECTION Description Allows the turn-on and the turn-off of the High Side and the Low Side switches according to the truth table. Shut-down the device outside the range [5.5V..16V] for the battery voltage. Protect the High Side and the Low Side switches from the high voltage on the battery line in all configuration for the motor. Drive the gate of the concerned switch to allow a proper RDS(on) for the leg of the bridge. Limits the motor current, by reducing the High Side Switch gate-source voltage when short-circuit to ground occurs. In case of short-circuit with the increase of the junction’s temperature, shuts-down the concerned High Side to prevent its degradation and to protect the die. Signalize an abnormal behavior of the switches in the half-bridge A or B by pulling low the concerned ENx/DIAGx pin. 3/18 VNH3ASP30-E Table 6. Absolute Maximum Rating Symbol VCC Imax IR IIN IEN Ipw VCS Parameter Supply Voltage Maximum Output Current (continuous) Reverse Output Current (continuous) Input Current (INA and INB pins) Enable Input Current (DIAGA/ENA and DIAGB/ENB pins) PWM Input Current Current Sense Maximum Voltage Electrostatic Discharge (R=1.5kΩ, C=100pF) VESD Value + 41 30 -30 +/- 10 +/- 10 +/- 10 -3/+15 - CS pin 2 kV - logic pins 4 kV 5 Internally Limited -40 to 150 -55 to 150 kV °C °C °C - output pins: OUTA, OUTB, VCC Junction Operating Temperature Case Operating Temperature Storage Temperature Tj Tc TSTG Unit V A A mA mA mA V Figure 4. Current and Voltage Conventions IS VCC IINA IINB IENA IENB VCC INA IOUTA OUTA INB OUTB CS DIAGA/ENA VOUTA VOUTB VSENSE DIAGB/ENB PWM IOUTB ISENSE GNDA GNDB Ipw GND VINA VINB VENA VENB Vpw IGND Table 7. Thermal Data Symbol Rthj-case Rthj-amb (*) Parameter Thermal resistance junction-case (Per leg) Thermal resistance junction-ambient (MAX) (MAX) Value 1.0 20 Note: (*) When mounted using the recommended pad size on FR-4 board (see MultiPowerSO-30 Mechanical data). 4/18 Unit °C/W °C/W VNH3ASP30-E ELECTRICAL CHARACTERISTICS (VCC=9V up to 16V; -40°C<Tj<150°C; unless otherwise specified) Table 8. Power Symbol VCC Parameter Operating supply voltage Test Conditions Min 5.5 Typ Max 16 Unit V Off state: INA=INB=PWM=0; Tj=25 °C; VCC=13V IS Supply Current 12 INA=INB=PWM=0 30 µA TBD µA On state: INA or INB=5V, no PWM RONHS Static High-Side resistance RONLS Static Low-Side resistance Vf High Side Free-wheeling Diode Forward Voltage 10 mA INA or INB=5V; PWM=20kHz IOUT=12A; Tj=25°C TBD 30 mA mΩ IOUT=12A; Tj= - 40 to 150°C IOUT=12A; Tj=25°C 60 12 mΩ mΩ IOUT=12A; Tj= - 40 to 150°C 24 mΩ 1.1 V 3 µA 5 µA If=12A 0.8 Tj=25°C; VOUTX=ENX=0V; IL(off) High Side Off State Output Current (per channel) VCC=13V Tj=125°C; VOUTX=ENX=0V; VCC=13V IRM Dynamic Cross-conduction Current IOUT=12A (see fig. 9) 1.7 A Table 9. Logic Inputs (INA, INB, ENA, ENB) Symbol Parameter VIL Input Low Level Voltage VIH Input High Level Voltage VIHYST Input Hysteresis Voltage VICL Input Clamp Voltage IINL IINH Input Current Input Current Enable Output Low Level Voltage VDIAG Test Conditions Normal operation (DIAGX/ENX pin acts as an input pin) Normal operation (DIAGX/ENX pin acts as an input pin) Normal operation (DIAGX/ENX pin acts as an input pin) IIN=1mA Min Typ Max Unit 1.25 V 5.5 6.3 7.5 V IIN=-1mA VIN=1.25 V VIN=3.25 V Fault operation (DIAGX/ENX pin acts as an output pin); IEN=1mA -1.0 1 -0.7 -0.3 10 V µA µA 0.4 V 3.25 V 0.5 V 5/18 VNH3ASP30-E ELECTRICAL CHARACTERISTICS (continued) Table 10. PWM Symbol Vpwl Ipwl Vpwh Ipwh Vpwhhyst Vpwcl CINPWM PWM PWM PWM PWM PWM Parameter Low Level Voltage Pin Current High Level Voltage Pin Current Hysteresis Voltage PWM Clamp Voltage PWM Pin Input Capacitance Test Conditions Min Vpw=1.25V Vpw=3.25V Ipw = 1 mA Typ Max 1.25 1 3.25 10 0.5 VCC+0.3 VCC+0.7 VCC+1.0 Ipw = -1 mA VIN =2.5V -6.0 -4.5 -3.0 25 Unit V µA V µA V V V pF Table 11. Switching (VCC=13V, RLOAD=1Ω) Symbol f td(on) td(off) tr tf tDEL trr Parameter PWM Frequency Turn-on Delay Time Turn-off Delay Time Rise Time Fall Time Delay Time During Change of Operating Mode High Side Free Wheeling Diode Reverse Recovery Time Test Conditions Min 0 Input rise time < 1µs (see fig. 8) Input rise time < 1µs (see fig. 8) (see fig. 7) (see fig. 7) (see fig. 6) 300 (see fig. 9) Typ 1 1 Max 20 250 250 2 2 Unit kHz µs µs µs µs 600 1800 µs 110 ns Table 12. Protection And Diagnostic Symbol VUSD VOV ILIM VCLP TTSD TTR THYST 6/18 Parameter Undervoltage Shut-down Undervoltage Reset Overvoltage Shut-down High-Side Current Limitation Total Clamp Voltage (VCC to GND) Thermal Shut-down Temperature Thermal Reset Temperature Thermal Hysteresis Test Conditions Min Typ Max 5.5 Unit V 16 30 4.7 19 45 22 60 V V A IOUT=12A 43 48 54 V VIN = 3.25 V 150 175 200 °C 135 7 15 °C °C VNH3ASP30-E ELECTRICAL CHARACTERISTICS (continued) Table 13. Current Sense (9V<VCC<16V) Symbol Parameter K1 IOUT /ISENSE K2 IOUT /ISENSE Test Conditions IOUT=30A; RSENSE=700Ω Tj= - 40 to 150°C IOUT=8A; RSENSE=700Ω dK1 / K1 (*) Analog sense current drift dK2 / K2 (*) Analog sense current drift Tj= - 40 to 150°C IOUT=30A; RSENSE=700Ω Tj= - 40 to 150°C IOUT >8A; RSENSE=700Ω Tj= - 40 to 150°C IOUT=0A; VSENSE=0V; Analog Sense Leakage Current ISENSEO Tj= - 40 to 150°C Min Typ Max 4000 4700 5400 3750 4700 5650 Unit -8 +8 % -10 +10 % 0 70 µA Note:(*) Analog sense current drift is deviation of factor K for a given device over (-40°C to 150°C and 9V<VCC<16V) with respect to it’s value measured at T j=25°C, VCC=13V. WAVEFORMS AND TRUTH TABLE Table 14. Truth Table In Normal Operating Conditions In normal operating conditions the DIAGX/ENX pin is considered as an input pin by the device. This pin must be externally pulled high. PWM pin usage: In all cases, a “0” on the PWM pin will turn-off both LSA and LSB switches. When PWM rises back to “1”, LSA or LSB turn on again depending on the input pin state. INA INB DIAGA/ENA DIAGB/ENB OUTA OUTB CS 1 1 1 0 1 1 1 1 H H H L High Imp. ISENSE=I OUT/K 0 1 1 1 L H ISENSE=I OUT/K 0 0 1 1 L L High Imp. Operating mode Brake to VCC Clockwise (CW) Counterclockwise (CCW) Brake to GND 7/18 VNH3ASP30-E Figure 5. Typical Application Circuit For Dc To 20KHz PWM Operation VCC Reg 5V + 5V VCC 3.3K 1K DIAGA/ENA 1K HSA HSB PWM µC OUTA 1K INA 10K CS OUTB LSA 33nF LSB M 1.5K S 100K G b) N MOSFET D In case of a fault condition the DIAGX/ENX pin is considered as an output pin by the device. The fault conditions are: - overtemperature on one or both high sides (for example if a short to ground occurs as it could be the case described in line 1 and 2 in the table below); - short to battery condition on the output (saturation detection on the Low-Side Power MOSFET). Possible origins of fault conditions may be: OUTA is shorted to ground ---> overtemperature detection on high side A. OUTA is shorted to VCC ---> Low-Side Power MOSFET saturation detection. When a fault condition is detected, the user can know which power element is in fault by monitoring the IN A, INB, DIAGA/ENA and DIAGB/ENB pins. In any case, when a fault is detected, the faulty leg of the bridge is latched off. To turn-on the respective output (OUTX) again, the input signal must rise from low to high level. Table 15. Truth Table In Fault Conditions (detected on OUTA) INA INB DIAGA/ENA DIAGB/ENB OUTA OUTB CS 1 1 0 1 OPEN H High Imp. 1 0 0 1 OPEN L High Imp. 0 1 0 1 OPEN H IOUTB/K 0 0 0 1 OPEN L High Imp. X X 0 0 OPEN OPEN High Imp. X 1 0 1 OPEN H IOUTB/K X 0 0 1 OPEN L High Imp. Fault Information 8/18 Protection Action VNH3ASP30-E Table 16. Electrical Transient Requirements ISO T/R 7637/1 Test Pulse 1 2 3a 3b 4 5 ISO T/R 7637/1 Test Pulse 1 2 3a 3b 4 5 Class C E Test Level Test Level Test Level Test Level Test Levels I II III IV Delays and Impedance -25V +25V -25V +25V -4V +26.5V -50V +50V -50V +50V -5V +46.5V -75V +75V -100V +75V -6V +66.5V -100V +100V -150V +100V -7V +86.5V 2ms, 10Ω 0.2ms, 10Ω 0.1µs, 50Ω 0.1µs, 50Ω 100ms, 0.01Ω 400ms, 2Ω Test Levels Result Test Levels Result Test Levels Result Test Levels Result I II III IV C C C C C C C C C C C E C C C C C E C C C C C E Contents All functions of the device are performed as designed after exposure to disturbance. One or more functions of the device are not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device. Reverse Battery Protection Three possible solutions can be thought of: a) a Schottky diode D connected to V CC pin b) a N-channel MOSFET connected to the GND pin (see Typical Application Circuit on fig. 5) c) a P-channel MOSFET connected to the V CC pin. The device sustains no more than -30A in reverse battery conditions because of the two Body diodes of the Power MOSFETs. Additionally, in reverse battery condition the I/Os of VNH3ASP30 will be pulled down to the VCC line (approximately -1.5V). Series resistor must be inserted to limit the current sunk from the microcontroller I/Os. If IRmax is the maximum target reverse current through µC I/Os, series resistor is: V –V IOs CC R = --------------------------------I Rmax 9/18 VNH3ASP30-E Figure 6. Definition Of The Delay Times Measurement VINA, t VINB t PWM t ILOAD tDEL tDEL t Figure 7. Definition Of The Low Side Switching Times PWM t VOUTA, B 90% tf 10/18 80% 20% 10% tr t VNH3ASP30-E Figure 8. Definition Of The High Side Switching Times VINA, tD(on) tD(off) t VOUTA 90% 10% t Figure 9. Definition Of Dynamic Cross Conduction Current During A PWM Operation IN A=1, IN B=0 PWM t IMOTOR t VOUTB t ICC IRM t trr 11/18 VNH3ASP30-E Figure 10. Waveforms in full bridge operation NORMAL OPERATION (DIAGA/ENA=1, DIAGB/ENB=1) LOAD CONNECTED BETWEEN OUTA, OUTB DIAGA/ENA DIAGB/ENB INA INB PWM OUTA OUTB IOUTA->OUTB CS (*) tDEL tDEL (*) CS BEHAVIOUR DURING PWM MODE WILL DEPEND ON PWM FREQUENCY AND DUTY CYCLE NORMAL OPERATION (DIAGA/ENA=1, DIAGB/ENB=0 and DIAGA/ENA=0, DIAGB/ENB=1) LOAD CONNECTED BETWEEN OUTA, OUTB DIAGA/ENA DIAGB/ENB INA INB PWM OUTA OUTB IOUTA->OUTB CS CURRENT LIMITATION/THERMAL SHUTDOWN or OUTA SHORTED TO GROUND INA INB ILIM IOUTA->OUTB TTSD TTR Tj > TTR Tj DIAGA/ENA DIAGB/ENB CS normal operation 12/18 OUTA shorted to ground normal operation VNH3ASP30-E Figure 11. Waveforms In Full Bridge Operation (continued) OUTA shorted to VCC and undervoltage shutdown INA INB undefined OUTA OUTB undefined IOUTA->OUTB DIAGB/ENB DIAGA/ENA CS V<nominal normal operation OUTA shorted to VCC normal operation undervoltage shutdown 13/18 VNH3ASP30-E Figure 12. Half-bridge Configuration The VNH3ASP30-E can be used as a high power half-bridge driver achieving an ON resistance per leg of 22.5mΩ. Suggested configuration is the following: VCC INA INB DIAGA/ENA DIAGB/ENB PWM INA INB DIAGA/ENA DIAGB/ENB PWM OUTA M OUTB GNDA GNDA GNDB OUTB OUTA GNDB Figure 13. Multi-motors Configuration The VNH3ASP30-E can easily be designed in multi-motors driving applications such as seat positioning systems where only one motor must be driven at a time. DIAG X/EN X pins allow to put unused half-bridges in high impedance. Suggested configuration is the following: VCC INA INB DIAGA/ENA DIAGB/ENB PWM INA INB DIAGA/ENA DIAGB/ENB PWM OUTA OUTB GNDA GNDB M1 14/18 M2 OUTB OUTA GNDA GNDB M3 VNH3ASP30-E PACKAGE MECHANICAL Table 17. MultiPowerSO-30 Mechanical Data Symbol millimeters Min. Typ A A2 Max. 2.35 1.85 2.25 A3 0 0.1 B 0.42 0.58 C 0.23 D 17.1 E 18.85 E1 15.9 e 0.32 17.2 17.3 19.15 16 16.1 1 F1 5.55 6.05 F2 4.6 5.1 F3 9.6 10.1 L 0.8 1.15 N S 10deg 0deg 7deg Figure 14. MultiPowerSO-30 Package Dimensions 15/18 VNH3ASP30-E Figure 15. MultiPowerSO-30 Suggested Pad Layout 16/18 VNH3ASP30-E REVISION HISTORY Date Revision Sep. 2004 1 - First issue. Description of Changes 17/18 VNH3ASP30-E Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2004 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 18/18