STL10N60M2 - STMicroelectronics

STL10N60M2
N-channel 600 V, 0.580 Ω typ., 5.5 A MDmesh II Plus™ low Qg
Power MOSFET in a PowerFLAT™ 5x6 HV package
Datasheet - production data
Features
Order code
VDS @
TJmax
RDS(on) max
ID
STL10N60M2
650 V
0.660 Ω
5.5 A
• Extremely low gate charge
1
2
• Lower RDS(on) x area vs previous generation
3
4
• Low gate input resistance
PowerFLAT™ 5x6 HV
• 100% avalanche tested
• Zener-protected
Applications
Figure 1. Internal schematic diagram
D(5, 6, 7, 8)
• Switching applications
8
7
5
6
Description
G(4)
1
2
3
4
Top View
This device is an N-channel Power MOSFET
developed using a new generation of MDmesh™
technology: MDmesh II Plus™ low Qg. This
revolutionary Power MOSFET associates a
vertical structure to the company's strip layout to
yield one of the world's lowest on-resistance and
gate charge. It is therefore suitable for the most
demanding high efficiency converters.
S(1, 2, 3)
AM15540v3
Table 1. Device summary
Order code
Marking
Package
Packaging
STL10N60M2
10N60M2
PowerFLAT™ 5x6 HV
Tape and reel
March 2014
This is information on a product in full production.
DocID025439 Rev 2
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www.st.com
Contents
STL10N60M2
Contents
1
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Electrical characteristics (curves)
............................ 6
3
Test circuits
4
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5
Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
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.............................................. 8
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STL10N60M2
1
Electrical ratings
Electrical ratings
Table 2. Absolute maximum ratings
Symbol
Parameter
Value
Unit
Gate-source voltage
± 25
V
ID
(1)
Drain current (continuous) at TC = 25 °C
5.5
A
ID
(1)
Drain current (continuous) at TC = 100 °C
3.5
A
IDM (2)
Drain current (pulsed)
22
A
PTOT(2)
Total dissipation at TC = 25 °C
48
W
IAR
Avalanche current, repetitive or notrepetitive (pulse width limited by Tj max)
1.5
A
EAS
Single pulse avalanche energy
(starting Tj = 25 °C, ID = IAR, VDD = 50 V)
110
mJ
Peak diode recovery voltage slope
15
V/ns
MOSFET dv/dt ruggedness
50
V/ns
- 55 to 150
°C
150
°C
Value
Unit
Thermal resistance junction-case max
2.6
°C/W
Rthj-amb(1) Thermal resistance junction-amb max
59
°C/W
VGS
dv/dt (3)
dv/dt
(4)
Tstg
Tj
Storage temperature
Max. operating junction temperature
1. The value is limited by package
2. Pulse width limited by safe operating area
3. ISD ≤ 5.5 A, di/dt ≤ 400 A/µs, VDSpeak ≤ V(BR)DSS, VDD = 80% V(BR)DSS
4. VDS ≤ 480 V
Table 3. Thermal data
Symbol
Rthj-case
Parameter
1. When mounted on 1inch² FR-4 board, 2 oz Cu
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Electrical characteristics
2
STL10N60M2
Electrical characteristics
(TC = 25 °C unless otherwise specified)
Table 4. On /off states
Symbol
V(BR)DSS
Parameter
Drain-source
breakdown voltage
Test conditions
ID = 1 mA, VGS = 0
IDSS
VDS = 600 V
Zero gate voltage
drain current (VGS = 0) VDS = 600 V, TC= 125 °C
IGSS
Gate-body leakage
current (VDS = 0)
Min.
Typ.
Gate threshold voltage VDS = VGS, ID = 250 µA
RDS(on)
Static drain-source onVGS = 10 V, ID = 2.5 A
resistance
Unit
600
V
1
µA
100
µA
100
nA
3
4
V
0.580
0.660
Ω
Min.
Typ.
Max.
Unit
-
400
-
pF
-
22
-
pF
-
0.84
-
pF
VGS = ± 25 V
VGS(th)
Max.
2
Table 5. Dynamic
Symbol
Parameter
Test conditions
Ciss
Input capacitance
Coss
Output capacitance
Crss
Reverse transfer
capacitance
Coss eq.(1)
Output equivalent
capacitance
VDS = 0 to 480 V, VGS = 0
-
83
-
pF
RG
Intrinsic gate
resistance
f = 1 MHz open drain
-
6.4
-
Ω
Qg
Total gate charge
-
13.5
-
nC
Qgs
Gate-source charge
-
2.1
-
nC
Qgd
Gate-drain charge
VDD = 480 V, ID = 7.5 A,
VGS = 10 V
(see Figure 15)
-
7.2
-
nC
VDS = 100 V, f = 1 MHz,
VGS = 0
1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS
increases from 0 to 80% VDS.
Table 6. Switching times
Symbol
td(on)
tr
td(off)
tf
4/16
Parameter
Test conditions
Turn-on delay time
Rise time
Turn-on delay time
VDD = 300 V, ID = 3.75 A,
RG = 4.7 Ω, VGS = 10 V
(see Figure 19)
Fall time
DocID025439 Rev 2
Min.
Typ.
Max
Unit
-
8.8
-
ns
-
8
-
ns
-
32.5
-
ns
-
13.2
-
ns
STL10N60M2
Electrical characteristics
Table 7. Source drain diode
Symbol
Parameter
Test conditions
Min.
Typ.
Max. Unit
Source-drain current
-
5.5
A
ISDM
(1)
Source-drain current (pulsed)
-
22
A
VSD
(2)
Forward on voltage
ISD = 7.5 A, VGS = 0
-
1.6
V
trr
Reverse recovery time
-
270
ns
Qrr
Reverse recovery charge
-
2
µC
IRRM
Reverse recovery current
ISD = 7.5 A, di/dt = 100 A/µs
VDD = 60 V
(see Figure 16)
-
14.4
A
-
376
ns
-
2.8
µC
-
15
A
ISD
trr
Reverse recovery time
Qrr
Reverse recovery charge
IRRM
Reverse recovery current
VDD = 60 V
di/dt = 100 A/µs, ISD = 7.5 A
Tj=150 °C (see Figure 16)
1. Pulse width limited by safe operating area.
2. Pulsed: pulse duration = 300 µs, duty cycle 1.5%
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Electrical characteristics
2.1
STL10N60M2
Electrical characteristics (curves)
Figure 2. Safe operating area
Figure 3. Thermal impedance
AM16157v1
ID
(A)
K
ZthPowerFlat_5x6_19
d=0.5
0.2
10µs
D
S(
on
)
O
Li per
m at
ite io
d ni
by n
m this
ax a
R rea
is
10
1
0.1
10 -1
0.05
0.02
0.01
100µs
1ms
10ms
10 -2
Single pulse
0.1
Tj=150°C
Tc=25°C
Single pulse
0.01
0.1
10
1
100
10 -3
10-6
VDS(V)
Figure 4. Output characteristics
10-4
10 -2
10-3
10 -1
10 tp(s)
Figure 5. Transfer characteristics
AM15823v1
ID
(A)
14
10-5
VGS=7, 8, 9, 10V
AM15824v1
ID (A)
VDS=18V
14
6V
12
12
10
10
8
8
6
6
5V
4
4
2
2
4V
0
5
0
15
10
20
Figure 6. Gate charge vs gate-source voltage
AM15825v1
VDS
VGS
(V)
(V)
VDD=480V
ID=7.5A
12 VDS
500
10
0
0
VDS(V)
400
8
2
4
10
8
6
VGS(V)
Figure 7. Static drain-source on-resistance
AM16158v1
RDS(on)
(Ω)
VGS=10V
0.610
0.600
0.590
300
6
0.580
200
4
0.570
100
2
0
0
6/16
2
4
6
8
10
12
0
Qg(nC)
0.560
0.550
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0
1
2
3
4
5
ID(A)
STL10N60M2
Electrical characteristics
Figure 8. Capacitance variations
Figure 9. Output capacitance stored energy
AM15827v1
C
(pF)
AM15832v1
Eoss(µJ)
1000
3
Ciss
100
2
Coss
10
0.1
0.1
1
Crss
1
1
10
100
Figure 10. Normalized gate threshold voltage vs
temperature
AM15915v1
VGS(th)
(norm)
0
0
VDS(V)
ID = 250 µA
100 200
400
500
600 VDS(V)
Figure 11. Normalized on-resistance vs
temperature
AM15916v1
RDS(on)
(norm)
ID= 2.5 A
VGS= 10 V
2.3
1.10
300
2.1
1.9
1.00
1.7
1.5
0.90
1.3
1.1
0.80
0.9
0.7
0.70
-50 -25
0
25
50
75 100
TJ(°C)
Figure 12. Normalized V(BR)DSS vs temperature
0.5
-50 -25
0
25
50
75 100
TJ(°C)
Figure 13. Source-drain diode forward
characteristics
AM15917v1
V(BR)DSS
AM15830v1
VSD (V)
(norm)
ID=1mA
1.11
1.4
1.09
1.2
1.07
TJ=-50°C
1
1.05
1.03
0.8
1.01
0.6
0.99
TJ=25°C
TJ=150°C
0.4
0.97
0.95
0.93
-50 -25
0.2
0
0
25
50
75 100
TJ(°C)
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0
1
2
3
4
5
6
7
ISD(A)
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16
Test circuits
3
STL10N60M2
Test circuits
Figure 14. Switching times test circuit for
resistive load
Figure 15. Gate charge test circuit
VDD
12V
47kΩ
1kΩ
100nF
3.3
μF
2200
RL
μF
IG=CONST
VDD
VGS
100Ω
Vi=20V=VGMAX
VD
RG
2200
μF
D.U.T.
D.U.T.
VG
2.7kΩ
PW
47kΩ
1kΩ
PW
AM01468v1
Figure 16. Test circuit for inductive load
switching and diode recovery times
A
A
AM01469v1
Figure 17. Unclamped inductive load test circuit
L
A
D
G
D.U.T.
FAST
DIODE
B
B
VD
L=100μH
S
3.3
μF
B
25 Ω
1000
μF
D
VDD
2200
μF
3.3
μF
VDD
ID
G
RG
S
Vi
D.U.T.
Pw
AM01470v1
AM01471v1
Figure 18. Unclamped inductive waveform
Figure 19. Switching time waveform
ton
V(BR)DSS
tdon
VD
toff
tr
tdoff
tf
90%
90%
IDM
10%
ID
VDD
10%
0
VDD
VDS
90%
VGS
AM01472v1
8/16
0
DocID025439 Rev 2
10%
AM01473v1
STL10N60M2
4
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
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Package mechanical data
STL10N60M2
Figure 20. PowerFLAT™ 5x6 HV drawing
8368143_Rev_B
10/16
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STL10N60M2
Package mechanical data
Table 8. PowerFLAT™ 5x6 HV mechanical data
mm
Dim.
Min.
Typ.
Max.
A
0.80
1.00
A1
0.02
0.05
A2
0.25
b
0.30
0.50
D
5.00
5.20
5.40
E
5.95
6.15
6.35
D2
4.30
4.40
4.50
E2
3.10
3.20
3.30
e
1.27
L
0.50
0.55
0.60
K
1.90
2.00
2.10
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Package mechanical data
STL10N60M2
Figure 21. PowerFLAT™ 5x6 HV recommended footprint (dimensions are in mm)
8368143_Rev_B_footprint
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STL10N60M2
Packaging mechanical data
Figure 22. PowerFLAT™ 5x6 tape(a)
P0
4.0±0.1 (II)
P2
2.0±0.1 (I)
T
(0.30 ±0.05)
E1
1.75±0.1
Y
0.
20
Do
Ø1.55±0.05
W(12.00±0.3)
R
F(5.50±0.1)(III)
C
L
EF
D1
Ø1.5 MIN.
Bo (5.30±0.1)
5
Packaging mechanical data
REF
.R0
.50
Y
P1(8.00±0.1)
Ao(6.30±0.1)
Ko (1.20±0.1)
SECTION Y-Y
(I) Measured from centerline of sprocket hole
to centerline of pocket.
Base and bulk quantity 3000 pcs
(II) Cumulative tolerance of 10 sprocket
holes is ± 0.20 .
(III) Measured from centerline of sprocket
hole to centerline of pocket.
8234350_Tape_rev_C
Figure 23. PowerFLAT™ 5x6 package orientation in carrier tape.
Pin 1
identification
a. All dimensions are in millimeters.
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Packaging mechanical data
STL10N60M2
Figure 24. PowerFLAT™ 5x6 reel
R0.60
W3
11.9/15.4
PART NO.
1.90
2.50
R25.00
ØN
178(±2.0)
ATTENTION
OBSERVE PRECAUTIONS
FOR HANDLING ELECTROSTATIC
SENSITIVE DEVICES
W2
18.4 (max)
A
330 (+0/-4.0)
4.00
2.50
77
ESD LOGO
W1
12.4 (+2/-0)
06
PS
ØA
128
2.20
R1.10
Ø21.2
All dimensions are in millimeters
13.00
CORE DETAIL
8234350_Reel_rev_C
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6
Revision history
Revision history
Table 9. Document revision history
Date
Revision
Changes
28-Oct-2013
1
First release.
26-Mar-2014
2
Document status promoted from preliminary to production data.
Minor text changes.
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STL10N60M2
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