STM32F358xC datasheet

STM32F358xC
ARM®-based Cortex®-M4 32b MCU+FPU, up to 256KB Flash+
48KB SRAM, 4 ADCs, 2 DAC ch., 7 comp., 4 PGA, timers, 1.8 V
Datasheet - production data
Features
• Core: ARM® Cortex®-M4 32-bit CPU with FPU
(72 MHz max), single-cycle multiplication and
HW division, 90 DMIPS (from CCM), DSP
instruction and MPU (memory protection unit).
• Operating conditions:
– VDD: 1.8V +/- 8%
– VDDA voltage range: 1.65 to 3.6 V
• Memories
– 256 Kbytes of Flash memory
– Up to 40 Kbytes of SRAM, with HW parity
check implemented on the first 16 Kbytes.
– Routine bootster: 8 Kbytes of SRAM on
instruction and data bus, with HW parity
check (CCM: Core Coupled Memory)
• CRC calculation unit
• Reset and supply management
– Low-power modes: Sleep, and Stop
– VBAT supply for RTC and backup registers
• Clock management
– 4 to 32 MHz crystal oscillator
– 32 kHz oscillator for RTC with calibration
– Internal 8 MHz RC with x 16 PLL option
– Internal 40 kHz oscillator
• Up to 86 fast I/Os
– All mappable on external interrupt vectors
– Several 5 V-tolerant
• Interconnect matrix
• 12-channel DMA controller
• Up to four ADC 0.20 µS (up to 38 channels)
with selectable resolution of 12/10/8/6 bits, 0 to
3.6 V conversion range, separate analog
supply from 1.8 to 3.6 V
• Up to two 12-bit DAC channels with analog
supply from 2.4 to 3.6 V
LQFP48 (7 × 7 mm)
LQFP64 (10 × 10 mm)
LQFP100 (14 × 14 mm)
• Up to 24 capacitive sensing channels
supporting touchkey, linear and rotary touch
sensors
• Up to 13 timers
– One 32-bit timer and two 16-bit timers with
up to 4 IC/OC/PWM or pulse counter and
quadrature (incremental) encoder input
– Up to two 16-bit 6-channel advancedcontrol timers, with up to 6 PWM channels,
deadtime generation and emergency stop
– One 16-bit timer with 2 IC/OCs, 1
OCN/PWM, deadtime generation and
emergency stop
– Two 16-bit timers with IC/OC/OCN/PWM,
deadtime generation and emergency stop
– 2 watchdog timers (independent, window)
– SysTick timer: 24-bit downcounter
– Up to two 16-bit basic timers to drive the
DAC
• Calendar RTC with Alarm, periodic wakeup
from Stop
• Communication interfaces
– CAN interface (2.0B Active)
– Two I2C Fast mode plus (1 Mbit/s) with 20
mA current sink, SMBus/PMBus, wakeup
from STOP
– Up to five USART/UARTs (ISO 7816
interface, LIN, IrDA, modem control)
– Up to three SPIs, two with multiplexed I2S
interface, 4 to 16 programmable bit frames
– Infrared Transmitter
• Cortex®-M4 with FPU ETM, Serial wire debug,
JTAG
• 96-bit unique ID
• Seven fast rail-to-rail analog comparators with
analog supply from 1.65 to 3.6 V
• Up to four operational amplifiers that can be
used in PGA mode, all terminal accessible with
analog supply from 2.4 to 3.6 V
April 2015
This is information on a product in full production.
Table 1. Device summary
Reference
STM32F358xC
DocID025540 Rev 4
Part number
STM32F358CC, STM32F358RC, STM32F358VC
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www.st.com
Contents
STM32F358xC
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1
ARM® Cortex®-M4 core with FPU with embedded Flash and SRAM . . . 12
3.2
Memory protection unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3
Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.4
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.5
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.6
Cyclic redundancy check (CRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.7
Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.7.1
Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.7.2
Power supply supervision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.7.3
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.8
Interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.9
Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.10
General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.11
Direct memory access (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.12
Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.12.1
3.13
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Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 18
Fast analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.13.1
Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.13.2
Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.13.3
VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.13.4
OPAMP reference voltage (VOPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.14
Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.15
Operational amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.16
Fast comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.17
Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.17.1
Advanced timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.17.2
General-purpose timers (TIM2, TIM3, TIM4, TIM15, TIM16, TIM17) . . 22
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STM32F358xC
Contents
3.17.3
Basic timers (TIM6, TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.17.4
Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.17.5
Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.17.6
SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.18
Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 23
3.19
Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.20
Universal synchronous/asynchronous receiver transmitter (USART) . . . 25
3.21
Universal asynchronous receiver transmitter (UART) . . . . . . . . . . . . . . . 25
3.22
Serial peripheral interface (SPI)/Inter-integrated sound interfaces (I2S) . 25
3.23
Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.24
Infrared Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.25
Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.26
Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.26.1
Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.26.2
Embedded trace macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4
Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.1.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.1.2
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.1.3
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.1.4
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.1.5
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.1.6
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.1.7
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.3.1
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.3.2
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 57
6.3.3
Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.3.4
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6.3.5
Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
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STM32F358xC
6.3.6
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
6.3.7
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.3.8
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
6.3.9
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.3.10
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.3.11
Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
6.3.12
I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.3.13
I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
6.3.14
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
6.3.15
NPOR pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
6.3.16
Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
6.3.17
Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
6.3.18
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
6.3.19
DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
6.3.20
Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
6.3.21
Operational amplifier characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 115
6.3.22
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
6.3.23
VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
7.1
LQFP100 – 14 x 14 mm, low-profile quad flat package
information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
7.2
LQFP64 – 10 x 10 mm, low-profile quad flat package
information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
7.3
LQFP48 – 7 x 7 mm, low-profile quad flat package
information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
7.4
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
7.4.1
Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
7.4.2
Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 129
8
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
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List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
STM32F358xC family device features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . 10
External analog supply values for analog peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
STM32F358xC peripheral interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
STM32F358xC I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
USART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
STM32F358xC SPI/I2S implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Capacitive sensing GPIOs available on STM32F358xC devices . . . . . . . . . . . . . . . . . . . . 28
No. of capacitive sensing channels available on
STM32F358xC devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
STM32F358xC pin definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Alternate functions for port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Alternate functions for port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Alternate functions for port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Alternate functions for port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Alternate functions for port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Alternate functions for port F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
STM32F358xC memory map and peripheral register boundary
addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Typical and maximum current consumption from VDD supply
at VDD = 1.8 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Typical and maximum current consumption from the VDDA supply . . . . . . . . . . . . . . . . . . 60
Typical and maximum VDD consumption in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Typical and maximum VDDA consumption in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Typical and maximum current consumption from VBAT supply. . . . . . . . . . . . . . . . . . . . . . 61
Typical current consumption in Run mode, code with data processing
running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Typical current consumption in Sleep mode, code running from Flash or RAM . . . . . . . . . 64
Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
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List of tables
Table 45.
Table 46.
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
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STM32F358xC
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
NPOR pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
IWDG min/max timeout period at 40 kHz (LSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
WWDG min-max timeout value @72 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
I2C timings specification (see I2C specification, rev.03, June 2007) . . . . . . . . . . . . . . . . . 91
I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Maximum ADC RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
ADC accuracy - limited test conditions 100-pin packages . . . . . . . . . . . . . . . . . . . . . . . . 102
ADC accuracy, 100-pin packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
ADC accuracy - limited test conditions 64-pin packages . . . . . . . . . . . . . . . . . . . . . . . . . 106
ADC accuracy, 64-pin packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
ADC accuracy at 1MSPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Operational amplifier characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
LQPF100 – 14 x 14 mm, low-profile quad flat package mechanical data. . . . . . . . . . . . . 119
LQFP64 – 10 x 10 mm, low-profile quad flat package mechanical data. . . . . . . . . . . . . . 122
LQFP48 – 7 x 7 mm, low-profile quad flat package mechanical data. . . . . . . . . . . . . . . . 125
Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
DocID025540 Rev 4
STM32F358xC
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
STM32F358xC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Infrared transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
STM32F358xC LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
STM32F358xC LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
STM32F358xC LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
STM32F358xC memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Typical VBAT current consumption (LSE and RTC ON/LSEDRV[1:0] = ’00’) . . . . . . . . . . . 62
High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
HSI oscillator accuracy characterization results for soldered parts . . . . . . . . . . . . . . . . . . 76
TC and TTa I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Five volt tolerant (FT and FTf) I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
ADC typical current consumption on VDDA pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
ADC typical current consumption on VREF+ pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Maximum VREFINT scaler startup time from power down . . . . . . . . . . . . . . . . . . . . . . . . 114
OPAMP Voltage Noise versus Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
LQFP100 – 14 x 14 mm, low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . 119
LQFP100 – 14 x 14 mm, low-profile quad flat package recommended footprint . . . . . . . 120
LQFP100 – 14 x 14 mm, low-profile quad flat package top view example . . . . . . . . . . . . 121
LQFP64 – 10 x 10 mm, low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . 122
LQFP64 – 10 x 10 mm, low-profile quad flat package recommended footprint . . . . . . . . 123
LQFP64 – 10 x 10 mm, low-profile quad flat package top view example . . . . . . . . . . . . . 124
LQFP48 – 7 x 7 mm, low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . 125
LQFP48 - 7 x 7 mm, low-profile quad flat package recommended footprint. . . . . . . . . . . 126
LQFP48 - 7 x 7 mm, low-profile quad flat package top view example . . . . . . . . . . . . . . . 127
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7
Introduction
1
STM32F358xC
Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32F358xC microcontrollers.
This STM32F358xC datasheet should be read in conjunction with the STM32F303xx,
STM32F358xC and STM32F328x4/6/8 (RM0316) reference manual. The reference manual
is available from the STMicroelectronics website www.st.com.
For information on the Cortex®-M4 core with FPU please refer to:
8/134
•
Cortex®-M4 with FPU Technical Reference Manual, available from ARM website
www.arm.com.
•
STM32F3xxx and STM32F4xxx Cortex®-M4 programming manual (PM0214)
available from our website www.st.com.
DocID025540 Rev 4
STM32F358xC
2
Description
Description
The STM32F358xC family is based on the high-performance ARM® Cortex®-M4 32-bit
RISC core with FPU operating at a frequency of up to 72 MHz, and embedding a floating
point unit (FPU), a memory protection unit (MPU) and an embedded trace macrocell (ETM).
The family incorporates high-speed embedded memories (up to 256 Kbytes of Flash
memory, up to 48 Kbytes of SRAM) and an extensive range of enhanced I/Os and
peripherals connected to two APB buses.
The devices offer up to four fast 12-bit ADCs (5 Msps), up to seven comparators, up to four
operational amplifiers, up to two DAC channels, a low-power RTC, up to five generalpurpose 16-bit timers, one general-purpose 32-bit timer, and two timers dedicated to motor
control. They also feature standard and advanced communication interfaces: up to two I2Cs,
up to three SPIs (two SPIs are with multiplexed full-duplex I2Ss on STM32F358xC devices),
three USARTs, up to two UARTs, and CAN. To achieve audio class accuracy, the I2S
peripherals can be clocked via an external PLL.
The STM32F358xC family operates in the -40 to +85 °C and -40 to +105 °C temperature
ranges. A comprehensive set of power-saving mode allows the design of low-power
applications.
The STM32F358xC family offers devices in three packages ranging from 48 pins to 100
pins.
The set of included peripherals changes with the device chosen.
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51
Description
STM32F358xC
Table 2. STM32F358xC family device features and peripheral counts
STM32F
358Cx
STM32F
358Rx
STM32F
358Vx
Flash (Kbytes)
256
256
256
SRAM (Kbytes) on data bus
40
40
40
Peripheral
CCM (Core Coupled Memory) RAM (Kbytes)
Timers
PWM channels
8
Advanced control
2 (16-bit)
General purpose
5 (16-bit)
1 (32-bit)
Basic
2 (16-bit)
(all)(1)
PWM channels (except complementary)
31
33
22
24
SPI(I2S)(2)
Comm. interfaces
GPIOs
3(2)
I2C
2
USART
3
UART
2
CAN
1
Normal
I/Os
(TC, TTa)
19
26
44
5 volts
Tolerant
I/Os
(FT, FTf)
17
25
42
DMA channels
12
12-bit ADCs
4
Number of channels
14
21
12-bit DAC channels
2
Analog comparator
7
Operational amplifiers
4
CPU frequency
72 MHz
Operating voltage
VDD = 1.8 V +/- 8%, VDDA = 1.65 V to 3.6 V
Ambient operating temperature: - 40 to 85 °C /
- 40 to 105 °C
Junction temperature: - 40 to 125 °C
Operating temperature
Packages
LQFP48
LQFP64
1. This total number considers also the PWMs generated on the complementary output channels.
2. The SPI interfaces can work in an exclusive way in either the SPI mode or the I2S audio mode.
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38
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LQFP100
STM32F358xC
Description
Figure 1. STM32F358xC block diagram
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DocID025540 Rev 4
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51
Functional overview
STM32F358xC
3
Functional overview
3.1
ARM® Cortex®-M4 core with FPU with embedded Flash and
SRAM
The ARM® Cortex®-M4 processor with FPU is the latest generation of ARM processors for
embedded systems. It was developed to provide a low-cost platform that meets the needs of
MCU implementation, with a reduced pin count and low-power consumption, while
delivering outstanding computational performance and an advanced response to interrupts.
The ARM® Cortex®-M4 32-bit RISC processor with FPU features exceptional codeefficiency, delivering the high-performance expected from an ARM core in the memory size
usually associated with 8- and 16-bit devices.
The processor supports a set of DSP instructions which allow efficient signal processing and
complex algorithm execution.
Its single precision FPU speeds up software development by using metalanguage
development tools, while avoiding saturation.
With its embedded ARM core, the STM32F358xC family is compatible with all ARM tools
and software.
Figure 1 shows the general block diagram of the STM32F358xC family devices.
3.2
Memory protection unit (MPU)
The memory protection unit (MPU) is used to separate the processing of tasks from the data
protection. The MPU can manage up to 8 protection areas that can all be further divided up
into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 gigabytes
of addressable memory.
The memory protection unit is especially helpful for applications where some critical or
certified code has to be protected against the misbehavior of other tasks. It is usually
managed by an RTOS (real-time operating system). If a program accesses a memory
location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS
environment, the kernel can dynamically update the MPU area setting, based on the
process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
3.3
Embedded Flash memory
All STM32F358xC devices feature up to 256 Kbytes of embedded Flash memory available
for storing programs and data. The Flash memory access time is adjusted to the CPU clock
frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 48 MHz and 2 wait states
above).
3.4
Embedded SRAM
STM32F358xC devices feature up to 48 Kbytes of embedded SRAM with hardware parity
12/134
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STM32F358xC
Functional overview
check. The memory can be accessed in read/write at CPU clock speed with 0 wait states,
allowing the CPU to achieve 90 Dhrystone Mips at 72 MHz (when running code from the
CCM (Core Coupled Memory) RAM).
•
8 Kbytes of CCM RAM on STM32F303xx devices mapped on both instruction and data
bus, used to execute critical routines or to access data (parity check on all of CCM
RAM).
•
3.5
40 Kbytes of SRAM mapped on the data bus (parity check on first 16 Kbytes of SRAM).
Boot modes
At startup, Boot0 pin and Boot1 option bit are used to select one of three boot options:
•
Boot from user Flash
•
Boot from system memory
•
Boot from embedded SRAM
The boot loader is located in system memory. It is used to reprogram the Flash memory by
using USART1 (PA9/PA10) or USART2 (PD5/PD6) or I2C1 (PB6/PB7).
3.6
Cyclic redundancy check (CRC)
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
configurable generator polynomial value and size.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at
linktime and stored at a given memory location.
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51
Functional overview
STM32F358xC
3.7
Power management
3.7.1
Power supply schemes
•
VSS, VDD = 1.8 V+/- 8%: external power supply for I/Os and core. It is provided
externally through VDD pins.
•
VSSA, VDDA = 1.65 to 3.6 V: external analog power supply for ADC, DACs, comparators
operational amplifiers, reset blocks, RCs and PLL. The minimum voltage to be applied
to VDDA differs from one analog peripheral to another. Table 3 provides the summary of
the VDDA ranges for analog peripherals. The VDDA voltage level must be always
greater or equal to the VDD voltage level and must be provided first.
•
VBAT= 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup
registers (through power switch which is guaranteed in the full range of VDD) when
VDD is not present.
Table 3. External analog supply values for analog peripherals
3.7.2
Analog peripheral
Minimum VDDA supply
Maximum VDDA supply
ADC
1.8 V
3.6 V
COMP
1.65 V
3.6 V
DAC / OPAMP
2.4 V
3.6V
Power supply supervision
The device power on reset is controlled through the external NPOR pin. The device remains
in reset state when NPOR pin is held low.
To guarantee a proper power-on reset, the NPOR pin must be held low when VDDA is
applied. Then, when VDD is stable, the reset state can be exited by:
3.7.3
•
either putting the NPOR pin in high impedance. NPOR pin has an internal pull up.
•
or forcing the pin to high level by connecting it to VDDA.
Low-power modes
The STM32F358xC devices support two low-power modes to achieve the best compromise
between low-power consumption, short startup time and available wakeup sources:
•
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
•
Stop mode
Stop mode achieves the lowest power consumption while retaining the content of
SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC
and the HSE crystal oscillators are disabled.
The device can be woken up from Stop mode by any of the EXTI line. The EXTI line
source can be one of the 16 external lines, the RTC alarm, COMPx, I2Cx or U(S)ARTx.
Note:
14/134
The RTC, the IWDG and the corresponding clock sources are not stopped by entering Stop
mode.
DocID025540 Rev 4
STM32F358xC
3.8
Functional overview
Interconnect matrix
Several peripherals have direct connections between them. This allows autonomous
communication between peripherals, saving CPU resources thus power supply
consumption. In addition, these hardware connections allow fast and predictable latency.
Table 4. STM32F358xC peripheral interconnect matrix
Interconnect source
Interconnect action
TIMx
Timers synchronization or chaining
ADCx
DAC1
Conversion triggers
DMA
Memory to memory transfer trigger
Compx
Comparator output blanking
COMPx
TIMx
Timer input: OCREF_CLR input, input capture
ADCx
TIMx
Timer triggered by analog watchdog
GPIO
RTCCLK
HSE/32
MC0
TIM16
Clock source used as input channel for HSI and
LSI calibration
CSS
CPU (hard fault)
COMPx
PVD
GPIO
TIM1, TIM8,
TIM15, 16, 17
Timer break
TIMx
External trigger, timer break
GPIO
ADCx
DAC1
Conversion external trigger
DAC1
COMPx
Comparator inverting input
TIMx
Note:
Interconnect
destination
For more details about the interconnect actions, please refer to the corresponding sections
in the reference manual RM0316.
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51
Functional overview
3.9
STM32F358xC
Clocks and startup
System clock selection is performed on startup, however the internal RC 8 MHz oscillator is
selected as default CPU clock on reset. An external 4-32 MHz clock can be selected, in
which case it is monitored for failure. If failure is detected, the system automatically switches
back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full
interrupt management of the PLL clock entry is available when necessary (for example with
failure of an indirectly used external oscillator).
Several prescalers allow to configure the AHB frequency, the high speed APB (APB2) and
the low speed APB (APB1) domains. The maximum frequency of the AHB and the high
speed APB domains is 72 MHz, while the maximum allowed frequency of the low speed
APB domain is 36 MHz.
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STM32F358xC
Functional overview
Figure 2. Clock tree
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069
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51
Functional overview
3.10
STM32F358xC
General-purpose input/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current
capable except for analog inputs.
The I/Os alternate function configuration can be locked if needed following a specific
sequence in order to avoid spurious writing to the I/Os registers.
Fast I/O handling allows I/O toggling up to 36 MHz.
3.11
Direct memory access (DMA)
The flexible general-purpose DMA is able to manage memory-to-memory, peripheral-tomemory and memory-to-peripheral transfers. The DMA controller supports circular buffer
management, avoiding the generation of interrupts when the controller reaches the end of
the buffer.
Each of the 12 DMA channels is connected to dedicated hardware DMA requests, with
software trigger support for each channel. Configuration is done by software and transfer
sizes between source and destination are independent.
The DMA can be used with the main peripherals: SPI, I2C, USART, general-purpose timers,
DAC and ADC.
3.12
Interrupts and events
3.12.1
Nested vectored interrupt controller (NVIC)
The STM32F358xC devices embed a nested vectored interrupt controller (NVIC) able to
handle up to 66 maskable interrupt channels and 16 priority levels.
The NVIC benefits are the following:
•
Closely coupled NVIC gives low latency interrupt processing
•
Interrupt entry vector table address passed directly to the core
•
Closely coupled NVIC core interface
•
Allows early processing of interrupts
•
Processing of late arriving higher priority interrupts
•
Support for tail chaining
•
Processor state automatically saved
•
Interrupt entry restored on interrupt exit with no instruction overhead
The NVIC hardware block provides flexible interrupt management features with minimal
interrupt latency.
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STM32F358xC
3.13
Functional overview
Fast analog-to-digital converter (ADC)
Up to four fast analog-to-digital converters 5 MSPS, with selectable resolution between 12
and 6 bit, are embedded in the STM32F358xC family devices. The ADCs have up to 38
external channels. Some of the external channels are shared between ADC1&2 and
between ADC3&4, performing conversions in single-shot or scan modes. In scan mode,
automatic conversion is performed on a selected group of analog inputs.
The ADCs have also internal channels: Temperature sensor connected to ADC1 channel
16, VBAT/2 connected to ADC1 channel 17, Voltage reference VREFINT connected to the 4
ADCs channel 18, VOPAMP1 connected to ADC1 channel 15, VOPAMP2 connected to
ADC2 channel 17, VOPAMP3 connected to ADC3 channel 17, VOPAMP4 connected to
ADC4 channel 17.
Additional logic functions embedded in the ADC interface allow:
•
Simultaneous sample and hold
•
Interleaved sample and hold
•
Single-shunt phase current reading techniques.
The ADC can be served by the DMA controller.
An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
The events generated by the general-purpose timers and the advanced-control timers can
be internally connected to the ADC start trigger and injection trigger, respectively, to allow
the application to synchronize A/D conversion and timers.
3.13.1
Temperature sensor
The temperature sensor (TS) generates a voltage VSENSE that varies linearly with
temperature.
The temperature sensor is internally connected to the ADC_IN16 input channel which is
used to convert the sensor output voltage into a digital value.
The sensor provides good linearity but it has to be calibrated to obtain good overall
accuracy of the temperature measurement. As the offset of the temperature sensor varies
from chip to chip due to process variation, the uncalibrated internal temperature sensor is
suitable for applications that detect temperature changes only.
To improve the accuracy of the temperature sensor measurement, each device is
individually factory-calibrated by ST. The temperature sensor factory calibration data are
stored by ST in the system memory area, accessible in read-only mode.
3.13.2
Internal voltage reference (VREFINT)
The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the
ADC and Comparators. VREFINT is internally connected to the ADC_IN18 input channel. The
precise voltage of VREFINT is individually measured for each part by ST during production
test and stored in the system memory area. It is accessible in read-only mode.
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51
Functional overview
3.13.3
STM32F358xC
VBAT battery voltage monitoring
This embedded hardware feature allows the application to measure the VBAT battery
voltage using the internal ADC channel ADC_IN17. As the VBAT voltage may be higher
than VDDA, and thus outside the ADC input range, the VBAT pin is internally connected to a
bridge divider by 2. As a consequence, the converted digital value is half the VBAT voltage.
3.13.4
OPAMP reference voltage (VOPAMP)
Every OPAMP reference voltage can be measured using a corresponding ADC internal
channel: VOPAMP1 connected to ADC1 channel 15, VOPAMP2 connected to ADC2
channel 17, VOPAMP3 connected to ADC3 channel 17, VOPAMP4 connected to ADC4
channel 17.
3.14
Digital-to-analog converter (DAC)
Up to two 12-bit buffered DAC channels can be used to convert digital signals into analog
voltage signal outputs. The chosen design structure is composed of integrated resistor
strings and an amplifier in inverting configuration.
This digital interface supports the following features:
3.15
•
Up to two DAC output channels on STM32F358xC devices
•
8-bit or 10-bit monotonic output
•
Left or right data alignment in 12-bit mode
•
Synchronized update capability on STM32F358xC devices
•
Noise-wave generation
•
Triangular-wave generation
•
Dual DAC channel independent or simultaneous conversions on STM32F358xC
devices
•
DMA capability (for each channel on STM32F358xC devices)
•
External triggers for conversion
Operational amplifier (OPAMP)
The STM32F358xC devices embed up to four operational amplifiers with external or internal
follower routing and PGA capability (or even amplifier and filter capability with external
components). When an operational amplifier is selected, an external ADC channel is used
to enable output measurement.
The operational amplifier features:
20/134
•
8.2 MHz bandwidth
•
0.5 mA output capability
•
Rail-to-rail input/output
•
In PGA mode, the gain can be programmed to be 2, 4, 8 or 16.
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STM32F358xC
3.16
Functional overview
Fast comparators (COMP)
The STM32F358xC devices embed seven fast rail-to-rail comparators with programmable
reference voltage (internal or external), hysteresis and speed (low speed for low-power) and
with selectable output polarity.
The reference voltage can be one of the following:
•
External I/O
•
DAC output pin
•
Internal reference voltage or submultiple (1/4, 1/2, 3/4). Refer to Table 26: Embedded
internal reference voltage on page 57 for the value and precision of the internal
reference voltage.
All comparators can wake up from STOP mode, generate interrupts and breaks for the
timers and can be also combined per pair into a window comparator
3.17
Timers and watchdogs
The STM32F358xC devices include up to two advanced control timers, up to 6 generalpurpose timers, two basic timers, two watchdog timers and a SysTick timer. The table below
compares the features of the advanced control, general purpose and basic timers.
Table 5. Timer feature comparison
Timer type
Timer
Counter
resolution
Counter
type
Prescaler
factor
DMA
request
generation
Advanced
TIM1, TIM8
16-bit
Up, Down,
Up/Down
Any integer
between 1
and 65536
Yes
4
Yes
Generalpurpose
TIM2
32-bit
Up, Down,
Up/Down
Any integer
between 1
and 65536
Yes
4
No
Generalpurpose
TIM3, TIM4
16-bit
Up, Down,
Up/Down
Any integer
between 1
and 65536
Yes
4
No
Generalpurpose
TIM15
16-bit
Up
Any integer
between 1
and 65536
Yes
2
1
Generalpurpose
TIM16, TIM17
16-bit
Up
Any integer
between 1
and 65536
Yes
1
1
Basic
TIM6, TIM7
16-bit
Up
Any integer
between 1
and 65536
Yes
0
No
Note:
Capture/
Complementary
compare
outputs
Channels
TIM1/8 can have PLL as clock source, and therefore can be clocked at 144 MHz.
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Functional overview
3.17.1
STM32F358xC
Advanced timers (TIM1, TIM8)
The advanced-control timers (TIM1 on all devices and TIM8 on STM32F358xC devices) can
each be seen as a three-phase PWM multiplexed on 6 channels. They have complementary
PWM outputs with programmable inserted dead-times. They can also be seen as complete
general-purpose timers. The 4 independent channels can be used for:
•
Input capture
•
Output compare
•
PWM generation (edge or center-aligned modes) with full modulation capability (0100%)
•
One-pulse mode output
In debug mode, the advanced-control timer counter can be frozen and the PWM outputs
disabled to turn off any power switches driven by these outputs.
Many features are shared with those of the general-purpose TIM timers (described in
Section 3.17.2 using the same architecture, so the advanced-control timers can work
together with the TIM timers via the Timer Link feature for synchronization or event chaining.
3.17.2
General-purpose timers (TIM2, TIM3, TIM4, TIM15, TIM16, TIM17)
There are up to six synchronizable general-purpose timers embedded in the STM32F358xC
devices (see Table 5 for differences). Each general-purpose timer can be used to generate
PWM outputs, or act as a simple time base.
•
TIM2, 3, and TIM4
These are full-featured general-purpose timers:
–
TIM2 has a 32-bit auto-reload up/downcounter and 32-bit prescaler
–
TIM3 and 4 have 16-bit auto-reload up/downcounters and 16-bit prescalers.
These timers all feature 4 independent channels for input capture/output compare,
PWM or one-pulse mode output. They can work together, or with the other generalpurpose timers via the Timer Link feature for synchronization or event chaining.
The counters can be frozen in debug mode.
All have independent DMA request generation and support quadrature encoders.
•
TIM15, 16 and 17
These three timers general-purpose timers with mid-range features:
They have 16-bit auto-reload upcounters and 16-bit prescalers.
–
TIM15 has 2 channels and 1 complementary channel
–
TIM16 and TIM17 have 1 channel and 1 complementary channel
All channels can be used for input capture/output compare, PWM or one-pulse mode
output.
The timers can work together via the Timer Link feature for synchronization or event
chaining. The timers have independent DMA request generation.
The counters can be frozen in debug mode.
3.17.3
Basic timers (TIM6, TIM7)
These timers are mainly used for DAC trigger generation. They can also be used as a
generic 16-bit time base.
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3.17.4
Functional overview
Independent watchdog (IWDG)
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 40 kHz internal RC and as it operates independently from the
main clock, it can operate in Stop mode. It can be used either as a watchdog to reset the
device when a problem occurs, or as a free running timer for application timeout
management. It is hardware or software configurable through the option bytes. The counter
can be frozen in debug mode.
3.17.5
Window watchdog (WWDG)
The window watchdog is based on a 7-bit downcounter that can be set as free running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
3.17.6
SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a standard
down counter. It features:
3.18
•
A 24-bit down counter
•
Autoreload capability
•
Maskable system interrupt generation when the counter reaches 0.
•
Programmable clock source
Real-time clock (RTC) and backup registers
The RTC and the 16 backup registers are supplied through VDD a switch that takes power
from either the VDD supply when present or the VBAT pin. The backup registers are sixteen
32-bit registers used to store 64 bytes of user application data when VDD power is not
present.
They are not reset by a system or power reset.
The RTC is an independent BCD timer/counter. It supports the following features:
•
Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format.
•
Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision.
•
Automatic correction for 28, 29 (leap year), 30 and 31 days of the month.
•
Two programmable alarms with wake up from Stop mode capability.
•
On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize it with a master clock.
•
Digital calibration circuit with 1 ppm resolution, to compensate for quartz crystal
inaccuracy.
•
Three anti-tamper detection pins with programmable filter. The MCU can be woken up
from Stop mode on tamper event detection.
•
Timestamp feature which can be used to save the calendar content. This function can
be triggered by an event on the timestamp pin, or by a tamper event. The MCU can be
woken up from Stop mode on timestamp event detection.
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Functional overview
•
STM32F358xC
17-bit Auto-reload counter for periodic interrupt with wakeup from STOP capability.
The RTC clock sources can be:
3.19
•
A 32.768 kHz external crystal
•
A resonator or oscillator
•
The internal low-power RC oscillator (typical frequency of 40 kHz)
•
The high-speed external clock divided by 32.
Inter-integrated circuit interface (I2C)
Up to two I2C bus interfaces can operate in multimaster and slave modes. They can support
standard (up to 100 KHz), fast (up to 400 KHz) and fast mode + (up to 1 MHz) modes.
Both support 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses
(2 addresses, 1 with configurable mask). They also include programmable analog and
digital noise filters.
Table 6. Comparison of I2C analog and digital filters
Analog filter
Digital filter
Pulse width of
suppressed spikes
≥ 50 ns
Programmable length from 1 to 15
I2C peripheral clocks
Benefits
Available in Stop mode
1. Extra filtering capability vs.
standard requirements.
2. Stable length
Drawbacks
Variations depending on
temperature, voltage, process
Wakeup from Stop on address
match is not available when digital
filter is enabled.
In addition, they provide hardware support for SMBUS 2.0 and PMBUS 1.1: ARP capability,
Host notify protocol, hardware CRC (PEC) generation/verification, timeouts verifications and
ALERT protocol management. They also have a clock domain independent from the CPU
clock, allowing the I2Cx (x=1,2) to wake up the MCU from Stop mode on address match.
The I2C interfaces can be served by the DMA controller.
Refer to Table 7 for the features available in I2C1 and I2C2.
Table 7. STM32F358xC I2C implementation
I2C features(1)
I2C1
I2C2
7-bit addressing mode
X
X
10-bit addressing mode
X
X
Standard mode (up to 100 kbit/s)
X
X
Fast mode (up to 400 kbit/s)
X
X
Fast Mode Plus with 20mA output drive I/Os (up to 1 Mbit/s)
X
X
Independent clock
X
X
SMBus
X
X
Wakeup from STOP
X
X
1. X = supported.
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3.20
Functional overview
Universal synchronous/asynchronous receiver transmitter
(USART)
The STM32F358xC devices have three embedded universal synchronous/asynchronous
receiver transmitters (USART1, USART2 and USART3).
The USART interfaces are able to communicate at speeds of up to 9 Mbits/s.
They provide hardware management of the CTS and RTS signals, they support IrDA SIR
ENDEC, the multiprocessor communication mode, the single-wire half-duplex
communication mode and have LIN Master/Slave capability. The USART interfaces can be
served by the DMA controller.
3.21
Universal asynchronous receiver transmitter (UART)
The STM32F358xC devices have 2 embedded universal asynchronous receiver
transmitters (UART4, and UART5). The UART interfaces support IrDA SIR ENDEC,
multiprocessor communication mode and single-wire half-duplex communication mode. The
UART4 interface can be served by the DMA controller.
Refer to Table 8 for the features available in all U(S)ARTs interfaces.
Table 8. USART features
USART modes/features(1)
USART1
USART2
USART3
UART4
UART5
Hardware flow control for modem
X
X
X
-
-
Continuous communication using DMA
X
X
X
X
-
Multiprocessor communication
X
X
X
X
X
Synchronous mode
X
X
X
-
-
Smartcard mode
X
X
X
-
-
Single-wire half-duplex communication
X
X
X
X
X
IrDA SIR ENDEC block
X
X
X
X
X
LIN mode
X
X
X
X
X
Dual clock domain and wakeup from Stop mode
X
X
X
X
X
Receiver timeout interrupt
X
X
X
X
X
Modbus communication
X
X
X
X
X
Auto baud rate detection
X
X
X
-
-
Driver Enable
X
X
X
-
-
1. X = supported.
3.22
Serial peripheral interface (SPI)/Inter-integrated sound
interfaces (I2S)
Up to three SPIs are able to communicate up to 18 Mbits/s in slave and master modes in
full-duplex and half-duplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame size is configurable from 4 bits to 16 bits.
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Functional overview
STM32F358xC
Two standard I2S interfaces (multiplexed with SPI2 and SPI3) supporting four different
audio standards can operate as master or slave at half-duplex and full duplex
communication modes. They can be configured to transfer 16 and 24 or 32 bits with 16-bit
or 32-bit data resolution and synchronized by a specific signal. Audio sampling frequency
from 8 kHz up to 192 kHz can be set by 8-bit programmable linear prescaler. When
operating in master mode it can output a clock for an external audio component at 256 times
the sampling frequency.
Refer to Table 9 for the features available in SPI1, SPI2 and SPI3.
Table 9. STM32F358xC SPI/I2S implementation
SPI features(1)
SPI1
SPI2
SPI3
Hardware CRC calculation
X
X
X
Rx/Tx FIFO
X
X
X
NSS pulse mode
X
X
X
I2S mode
-
X
X
TI mode
X
X
X
1. X = supported.
3.23
Controller area network (CAN)
The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It
can receive and transmit standard frames with 11-bit identifiers as well as extended frames
with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and
14 scalable filter banks.
3.24
Infrared Transmitter
The STM32F358xC devices provide an infrared transmitter solution. The solution is based
on internal connections between TIM16 and TIM17 as shown in the figure below. TIM17 is
used to provide the carrier frequency and TIM16 provides the main signal to be sent. The
infrared output signal is available on PB9 or PA13.
To generate the infrared remote control signals, TIM16 channel 1 and TIM17 channel 1 must
be properly configured to generate correct waveforms. All standard IR pulse modulation
modes can be obtained by programming the two timers output compare channels.
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Functional overview
Figure 3. Infrared transmitter
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3.25
Touch sensing controller (TSC)
The STM32F358xC devices provide a simple solution for adding capacitive sensing
functionality to any application. These devices offer up to 24 capacitive sensing channels
distributed over 8 analog I/O groups.
Capacitive sensing technology is able to detect the presence of a finger near a sensor which
is protected from direct touch by a dielectric (glass, plastic, ...). The capacitive variation
introduced by the finger (or any conductive object) is measured using a proven
implementation based on a surface charge transfer acquisition principle. It consists of
charging the sensor capacitance and then transferring a part of the accumulated charges
into a sampling capacitor until the voltage across this capacitor has reached a specific
threshold. To limit the CPU bandwidth usage this acquisition is directly managed by the
hardware touch sensing controller and only requires few external components to operate.
The touch sensing controller is fully supported by the STMTouch touch sensing firmware
library which is free to use and allows touch sensing functionality to be implemented reliably
in the end application.
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51
Functional overview
STM32F358xC
Table 10. Capacitive sensing GPIOs available on STM32F358xC devices
Group
1
2
3
4
Capacitive sensing
signal name
Pin
name
TSC_G5_IO1
PB3
TSC_G5_IO2
PB4
TSC_G5_IO3
PB6
PA3
TSC_G5_IO4
PB7
TSC_G2_IO1
PA4
TSC_G6_IO1
PB11
TSC_G2_IO2
PA5
TSC_G6_IO2
PB12
TSC_G2_IO3
PA6
TSC_G6_IO3
PB13
TSC_G2_IO4
PA7
TSC_G6_IO4
PB14
TSC_G3_IO1
PC5
TSC_G7_IO1
PE2
TSC_G3_IO2
PB0
TSC_G7_IO2
PE3
TSC_G3_IO3
PB1
TSC_G7_IO3
PE4
TSC_G4_IO1
PA9
TSC_G7_IO4
PE5
TSC_G4_IO2
PA10
TSC_G8_IO1
PD12
TSC_G4_IO3
PA13
TSC_G8_IO2
PD13
TSC_G4_IO4
PA14
TSC_G8_IO3
PD14
TSC_G8_IO4
PD15
Capacitive sensing
signal name
Pin
name
TSC_G1_IO1
PA0
TSC_G1_IO2
PA1
TSC_G1_IO3
PA2
TSC_G1_IO4
Group
5
6
7
8
Table 11. No. of capacitive sensing channels available on
STM32F358xC devices
Number of capacitive sensing channels
Analog I/O group
28/134
STM32F358xVx
STM32F358xRx
STM32F358xCx
G1
3
3
3
G2
3
3
3
G3
2
2
1
G4
3
3
3
G5
3
3
3
G6
3
3
3
G7
3
0
0
G8
3
0
0
Number of capacitive
sensing channels
23
17
16
DocID025540 Rev 4
STM32F358xC
Functional overview
3.26
Development support
3.26.1
Serial wire JTAG debug port (SWJ-DP)
The ARM SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a
specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.
3.26.2
Embedded trace macrocell™
The ARM embedded trace macrocell provides a greater visibility of the instruction and data
flow inside the CPU core by streaming compressed data at a very high rate from the
STM32F358xC through a small number of ETM pins to an external hardware trace port
analyzer (TPA) device. The TPA is connected to a host computer using a high-speed
channel. Real-time instruction and data flow activity can be recorded and then formatted for
display on the host computer running debugger software. TPA hardware is commercially
available from common development tool vendors. It operates with third party debugger
software tools.
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51
Pinouts and pin description
4
STM32F358xC
Pinouts and pin description
9''B
966B
3%
3%
%227
3%
3%
3%
3%
3%
3$
3$
Figure 4. STM32F358xC LQFP48 pinout
,1&0
3$
3$
3$
3$
3$
3%
3%
1325
3%
3%
966B
9''B
9%$7
3&
3&26&B,1
3&26&B287
3)26&B,1
3)26&B287
1567
966$95()
9''$95()
3$
3$
3$
30/134
DocID025540 Rev 4
9''B
966B
3$
3$
3$
3$
3$
3$
3%
3%
3%
3%
.47
STM32F358xC
Pinouts and pin description
9''B
966B
3%
3%
%227
3%
3%
3%
3%
3%
3'
3&
3&
3&
3$
3$
Figure 5. STM32F358xC LQFP64 pinout
,1&0
9''B
966B
3$
3$
3$
3$
3$
3$
3&
3&
3&
3&
3%
3%
3%
3%
3$
3)
9''B
3$
3$
3$
3$
3&
3&
3%
3%
1325
3%
3%
966B
9''B
9%$7
3&
3&26&B,1
3&26&B287
3)26&B,1
3)26&B287
1567
3&
3&
3&
3&
966$95()
9''$95()
3$
3$
3$
-36
DocID025540 Rev 4
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51
Pinouts and pin description
STM32F358xC
6$$?
633?
0%
0%
0"
0"
"//4
0"
0"
0"
0"
0"
0$
0$
0$
0$
0$
0$
0$
0$
0#
0#
0#
0!
0!
Figure 6. STM32F358xC LQFP100 pinout
,1&0
6$$?
633?
0&
0! 0! 0! 0! 0! 0! 0#
0#
0#
0#
0$
0$
0$
0$
0$
0$
0$
0$
0"
0"
0" 0"
0!
0&
6$$?
0!
0!
0!
0!
0#
0#
0"
0"
.0/2
0%
0%
0%
0%
0%
0%
0%
0%
0%
0"
0"
633?
6$$?
0%
0%
0%
0%
0%
6"!4
0#
0#/3#?).
0#/3#?/54
0&
0&
0&/3#?).
0&/3#?/54
.234
0#
0#
0#
0#
0&
633!62%&
62%&
6$$!
0!
0!
0!
-36
32/134
DocID025540 Rev 4
STM32F358xC
Pinouts and pin description
Table 12. Legend/abbreviations used in the pinout table
Name
Pin name
Pin type
I/O structure
Notes
Pin
functions
Abbreviation
Definition
Unless otherwise specified in brackets below the pin name, the pin function
during and after reset is the same as the actual pin name
S
Supply pin
I
Input only pin
I/O
Input / output pin
FT
5 V tolerant I/O
FTf
5 V tolerant I/O, FM+ capable
TTa
3.3 V tolerant I/O directly connected to ADC
TC
Standard 3.3V I/O
B
Dedicated BOOT0 pin
RST
Bidirectional reset pin with embedded weak pull-up resistor
POR
External power on reset pin with embedded weak pull-up
resistor, powered from VDDA
Unless otherwise specified by a note, all I/Os are set as floating inputs during
and after reset
Alternate
functions
Functions selected through GPIOx_AFR registers
Additional
functions
Functions directly selected/enabled through peripheral registers
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51
Pinouts and pin description
STM32F358xC
Table 13. STM32F358xC pin definitions
LQFP64
LQFP48
Pin type
I/O structure
Notes
Pin functions
LQFP100
Pin number
1
-
-
PE2
I/O
FT
(1)
TRACECK, TIM3_CH1,
TSC_G7_IO1, EVENTOUT
-
2
-
-
PE3
I/O
FT
(1)
TRACED0, TIM3_CH2,
TSC_G7_IO2, EVENTOUT
-
3
-
-
PE4
I/O
FT
(1)
TRACED1, TIM3_CH3,
TSC_G7_IO3, EVENTOUT
-
4
-
-
PE5
I/O
FT
(1)
TRACED2, TIM3_CH4,
TSC_G7_IO4, EVENTOUT
-
5
-
-
PE6
I/O
FT
(1)
TRACED3, EVENTOUT
6
1
1
VBAT
S
-
-
7
2
2
PC13(2)
I/O
TC
-
8
3
3
PC14(2)
OSC32_IN I/O
(PC14)
TC
-
-
OSC32_IN
-
OSC32_OUT
Pin name
(function
after
reset)
Alternate functions
Additional functions
WKUP3, RTC_TAMP3
Backup power supply
WKUP2, RTC_TAMP1,
RTC_TS, RTC_OUT
TIM1_CH1N
9
4
4
PC15(2)
OSC32_
OUT
(PC15)
10
-
-
PF9
I/O
FT
(1)
TIM15_CH1, SPI2_SCK,
EVENTOUT
-
11
-
-
PF10
I/O
FT
(1)
TIM15_CH2, SPI2_SCK,
EVENTOUT
-
12
5
5
PF0OSC_IN
(PF0)
I/O
FTf
-
TIM1_CH3N, I2C2_SDA,
OSC_IN
13
6
6
PF1OSC_OUT I/O
(PF1)
FTf
-
I2C2_SCL
OSC_OUT
14
7
7
15
16
8
9
-
NRST
PC0
PC1
I/O
TC
-
I/O
I/O
I/O
RST
-
TTa
(1)
Device reset input / internal reset output (active low)
EVENTOUT
ADC12_IN6, COMP7_INM
TTa
(1)
EVENTOUT
ADC12_IN7, COMP7_INP
17
10
-
PC2
I/O
TTa
(1)
COMP7_OUT, EVENTOUT
ADC12_IN8
18
11
-
PC3
I/O
TTa
(1)
TIM1_BKIN2, EVENTOUT
ADC12_IN9
EVENTOUT
ADC12_IN10
19
-
-
PF2
I/O
TTa
(1)
20
12
8
VSSA/
VREF-
S
-
-
34/134
Analog ground/Negative reference voltage
DocID025540 Rev 4
STM32F358xC
Pinouts and pin description
Table 13. STM32F358xC pin definitions (continued)
-
22
-
-
13
23
14
9
10
Notes
-
I/O structure
LQFP48
21
Pin name
(function
after
reset)
Pin type
LQFP64
Pin functions
LQFP100
Pin number
VREF+
S
-
-
Positive reference voltage
VDDA
S
-
-
Analog power supply
VDDA/
VREF+
S
-
-
Analog power supply/Positive reference voltage
PA0
I/O
TTa
Alternate functions
Additional functions
-
USART2_CTS,
TIM2_CH1_ETR, TIM8_BKIN,
TIM8_ETR, TSC_G1_IO1,
COMP1_OUT, EVENTOUT
ADC1_IN1, COMP1_INM,
RTC_ TAMP2, WKUP1,
COMP7_INP
ADC1_IN2, COMP1_INP,
OPAMP1_VINP,
OPAMP3_VINP
24
15
11
PA1
I/O
TTa
-
USART2_RTS_DE,
TIM2_CH2, TSC_G1_IO2,
TIM15_CH1N, RTC_REFIN,
EVENTOUT
25
16
12
PA2
I/O
TTa
(3)
USART2_TX, TIM2_CH3,
TIM15_CH1, TSC_G1_IO3,
COMP2_OUT, EVENTOUT
ADC1_IN3, COMP2_INM,
OPAMP1_VOUT
26
17
13
PA3
I/O
TTa
-
USART2_RX, TIM2_CH4,
TIM15_CH2, TSC_G1_IO4,
EVENTOUT
ADC1_IN4, OPAMP1_VINP,
COMP2_INP,
OPAMP1_VINM
27
18
-
PF4
I/O
TTa
(1)
COMP1_OUT, EVENTOUT
ADC1_IN5
28
19
-
VDD_4
S
-
-
29
30
31
20
21
22
14
15
16
PA4
PA5
PA6
I/O
I/O
I/O
TTa
(3)
-
-
SPI1_NSS, SPI3_NSS,
I2S3_WS, USART2_CK,
TSC_G2_IO1, TIM3_CH2,
EVENTOUT
ADC2_IN1, DAC1_OUT1,
OPAMP4_VINP,
COMP1_INM, COMP2_INM,
COMP3_INM, COMP4_INM,
COMP5_INM,
COMP6_INM,COMP7_INM
TTa
(3)
SPI1_SCK, TIM2_CH1_ETR,
TSC_G2_IO2, EVENTOUT
ADC2_IN2, DAC1_OUT2
OPAMP1_VINP,
OPAMP2_VINM,
OPAMP3_VINP,
COMP1_INM, COMP2_INM,
COMP3_INM,
COMP4_INM,COMP5_INM,
COMP6_INM, COMP7_INM
TTa
(3)
SPI1_MISO, TIM3_CH1,
TIM8_BKIN, TIM1_BKIN,
TIM16_CH1, COMP1_OUT,
TSC_G2_IO3, EVENTOUT
ADC2_IN3, OPAMP2_VOUT
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51
Pinouts and pin description
STM32F358xC
Table 13. STM32F358xC pin definitions (continued)
Notes
I/O structure
Pin name
(function
after
reset)
Pin type
Pin functions
LQFP48
LQFP64
LQFP100
Pin number
Alternate functions
Additional functions
SPI1_MOSI, TIM3_CH2,
TIM17_CH1, TIM1_CH1N,
TIM8_CH1N, TSC_G2_IO4,
COMP2_OUT, EVENTOUT
ADC2_IN4, COMP2_INP,
OPAMP2_VINP,
OPAMP1_VINP
32
23
17
PA7
I/O
TTa
-
33
24
-
PC4
I/O
TTa
(1)
USART1_TX, EVENTOUT
ADC2_IN5
34
25
-
PC5
I/O
TTa
(1)
USART1_RX, TSC_G3_IO1,
EVENTOUT
ADC2_IN11, OPAMP2_VINM,
OPAMP1_VINM
35
26
18
PB0
I/O
TTa
-
TIM3_CH3, TIM1_CH2N,
TIM8_CH2N, TSC_G3_IO2,
EVENTOUT
ADC3_IN12, COMP4_INP,
OPAMP3_VINP,
OPAMP2_VINP
36
27
19
PB1
I/O
TTa
(3)
TIM3_CH4, TIM1_CH3N,
TIM8_CH3N, COMP4_OUT,
TSC_G3_IO3, EVENTOUT
ADC3_IN1, OPAMP3_VOUT
37
28
20
NPOR
I
POR
(4)
Device power-on reset input
38
-
-
PE7
I/O
TTa
(1)
TIM1_ETR, EVENTOUT
ADC3_IN13, COMP4_INP
39
-
-
PE8
I/O
TTa
(1)
TIM1_CH1N, EVENTOUT
COMP4_INM, ADC34_IN6
40
-
-
PE9
I/O
TTa
(1)
TIM1_CH1, EVENTOUT
ADC3_IN2
TTa
(1)
TIM1_CH2N, EVENTOUT
ADC3_IN14
41
-
-
PE10
I/O
PE11
I/O
TTa
(1)
TIM1_CH2, EVENTOUT
ADC3_IN15
PE12
I/O
TTa
(1)
TIM1_CH3N, EVENTOUT
ADC3_IN16
-
PE13
I/O
TTa
(1)
TIM1_CH3, EVENTOUT
ADC3_IN3
-
-
PE14
I/O
TTa
(1)
TIM1_CH4, TIM1_BKIN2,
EVENTOUT
ADC4_IN1
46
-
-
PE15
I/O
TTa
(1)
USART3_RX, TIM1_BKIN,
EVENTOUT
ADC4_IN2
47
29
21
PB10
I/O
TTa
-
USART3_TX, TIM2_CH3,
TSC_SYNC, EVENTOUT
COMP5_INM,
OPAMP4_VINM,
OPAMP3_VINM
48
30
22
PB11
I/O
TTa
-
USART3_RX, TIM2_CH4,
TSC_G6_IO1, EVENTOUT
COMP6_INP, OPAMP4_VINP
-
-
Digital ground
-
-
Digital power supply
TTa
(3)
42
-
43
-
44
-
45
-
49
31
23
VSS_2
S
50
32
24
VDD_2
S
51
36/134
33
25
PB12
I/O
SPI2_NSS, I2S2_WS,
I2C2_SMBA, USART3_CK,
TIM1_BKIN, TSC_G6_IO2,
EVENTOUT
DocID025540 Rev 4
ADC4_IN3, COMP3_INM,
OPAMP4_VOUT,
STM32F358xC
Pinouts and pin description
Table 13. STM32F358xC pin definitions (continued)
26
53
35
27
PB13
I/O
PB14
I/O
Notes
34
I/O structure
LQFP48
52
Pin name
(function
after
reset)
Pin type
LQFP64
Pin functions
LQFP100
Pin number
TTa
-
SPI2_SCK, I2S2_CK,
USART3_CTS, TIM1_CH1N,
TSC_G6_IO3, EVENTOUT
ADC3_IN5, COMP5_INP,
OPAMP4_VINP,
OPAMP3_VINP
-
SPI2_MISO, I2S2ext_SD,
USART3_RTS_DE,
TIM1_CH2N, TIM15_CH1,
TSC_G6_IO4, EVENTOUT
COMP3_INP, ADC4_IN4,
OPAMP2_VINP
SPI2_MOSI, I2S2_SD,
TIM1_CH3N, RTC_REFIN,
TIM15_CH1N, TIM15_CH2,
EVENTOUT
ADC4_IN5, COMP6_INM
TTa
Alternate functions
Additional functions
54
36
28
PB15
I/O
TTa
-
55
-
-
PD8
I/O
TTa
(1)
USART3_TX, EVENTOUT
ADC4_IN12, OPAMP4_VINM
TTa
(1)
USART3_RX, EVENTOUT
ADC4_IN13
USART3_CK, EVENTOUT
ADC34_IN7, COMP6_INM
56
-
-
PD9
I/O
57
-
-
PD10
I/O
TTa
(1)
58
-
-
PD11
I/O
TTa
(1)
USART3_CTS, EVENTOUT
ADC34_IN8, COMP6_INP,
OPAMP4_VINP
59
-
-
PD12
I/O
TTa
(1)
USART3_RTS_DE,
TIM4_CH1, TSC_G8_IO1,
EVENTOUT
ADC34_IN9, COMP5_INP
60
-
-
PD13
I/O
TTa
(1)
TIM4_CH2, TSC_G8_IO2,
EVENTOUT
ADC34_IN10, COMP5_INM
61
-
-
PD14
I/O
TTa
(1)
TIM4_CH3, TSC_G8_IO3,
EVENTOUT
COMP3_INP, ADC34_IN11,
OPAMP2_VINP
62
-
-
PD15
I/O
TTa
(1)
SPI2_NSS, TIM4_CH4,
TSC_G8_IO4, EVENTOUT
COMP3_INM
63
37
-
PC6
I/O
FT
(1)
I2S2_MCK, COMP6_OUT,
TIM8_CH1, TIM3_CH1,
EVENTOUT
-
64
38
-
PC7
I/O
FT
(1)
I2S3_MCK, TIM8_CH2,
TIM3_CH2, COMP5_OUT,
EVENTOUT
-
65
39
-
PC8
I/O
FT
(1)
TIM8_CH3, TIM3_CH3,
COMP3_OUT, EVENTOUT
-
66
40
-
PC9
I/O
FT
(1)
TIM8_CH4, TIM8_BKIN2,
TIM3_CH4, I2S_CKIN,
EVENTOUT
-
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51
Pinouts and pin description
STM32F358xC
Table 13. STM32F358xC pin definitions (continued)
67
68
69
70
71
41
42
43
44
45
29
30
31
32
33
PA8
PA9
PA10
PA11
PA12
I/O
I/O
I/O
I/O
I/O
FT
FTf
FTf
FT
FT
Notes
I/O structure
Pin name
(function
after
reset)
Pin type
Pin functions
LQFP48
LQFP64
LQFP100
Pin number
Alternate functions
Additional functions
-
I2C2_SMBA, I2S2_MCK,
USART1_CK, TIM1_CH1,
TIM4_ETR, MCO,
COMP3_OUT, EVENTOUT
-
-
I2C2_SCL, I2S3_MCK,
USART1_TX, TIM1_CH2,
TIM2_CH3, TIM15_BKIN,
TSC_G4_IO1, COMP5_OUT,
EVENTOUT
-
-
I2C2_SDA, USART1_RX,
TIM1_CH3, TIM2_CH4,
TIM8_BKIN, TIM17_BKIN,
TSC_G4_IO2, COMP6_OUT,
EVENTOUT
-
-
USART1_CTS, CAN_RX,
TIM1_CH1N, TIM1_CH4,
TIM1_BKIN2, TIM4_CH1,
COMP1_OUT, EVENTOUT
-
-
USART1_RTS_DE, CAN_TX,
TIM1_CH2N, TIM1_ETR,
TIM4_CH2, TIM16_CH1,
COMP2_OUT, EVENTOUT
-
USART3_CTS, TIM4_CH3,
TIM16_CH1N, TSC_G4_IO3,
IR_OUT, SWDIO-JTMS,
EVENTOUT
-
I2C2_SCL, USART3_RTS_DE,
TIM4_CH4, EVENTOUT
-
72
46
34
PA13
I/O
FT
-
73
-
-
PF6
I/O
FTf
(1)
74
47
35
VSS_3
S
-
-
Ground
75
48
36
VDD_3
S
-
-
Digital power supply
76
77
38/134
49
50
37
38
PA14
PA15
I/O
I/O
FTf
FTf
-
I2C1_SDA, USART2_TX,
TIM8_CH2, TIM1_BKIN,
TSC_G4_IO4, SWCLK-JTCK,
EVENTOUT
-
-
I2C1_SCL, SPI1_NSS,
SPI3_NSS, I2S3_WS, JTDI,
USART2_RX, TIM1_BKIN,
TIM2_CH1_ETR, TIM8_CH1,
EVENTOUT
-
DocID025540 Rev 4
STM32F358xC
Pinouts and pin description
Table 13. STM32F358xC pin definitions (continued)
LQFP64
LQFP48
Pin type
I/O structure
Notes
Pin functions
LQFP100
Pin number
78
51
-
PC10
I/O
FT
(1)
SPI3_SCK, I2S3_CK,
USART3_TX, UART4_TX,
TIM8_CH1N, EVENTOUT
-
79
52
-
PC11
I/O
FT
(1)
SPI3_MISO, I2S3ext_SD,
USART3_RX, UART4_RX,
TIM8_CH2N, EVENTOUT
-
80
53
-
PC12
I/O
FT
(1)
SPI3_MOSI, I2S3_SD,
USART3_CK, UART5_TX,
TIM8_CH3N, EVENTOUT
-
81
-
-
PD0
I/O
FT
(1)
CAN_RX, EVENTOUT
-
82
-
-
PD1
I/O
FT
(1)
CAN_TX, TIM8_CH4,
TIM8_BKIN2, EVENTOUT
-
83
54
-
PD2
I/O
FT
(1)
UART5_RX, TIM3_ETR,
TIM8_BKIN, EVENTOUT
-
84
-
-
PD3
I/O
FT
(1)
USART2_CTS,
TIM2_CH1_ETR, EVENTOUT
-
85
-
-
PD4
I/O
FT
(1)
USART2_RTS_DE,
TIM2_CH2, EVENTOUT
-
86
-
-
PD5
I/O
FT
(1)
USART2_TX, EVENTOUT
-
Pin name
(function
after
reset)
Alternate functions
Additional functions
87
-
-
PD6
I/O
FT
(1)
USART2_RX, TIM2_CH4,
EVENTOUT
88
-
-
PD7
I/O
FT
(1)
USART2_CK, TIM2_CH3,
EVENTOUT
-
-
SPI3_SCK, I2S3_CK,
SPI1_SCK, USART2_TX,
TIM2_CH2, TIM3_ETR,
TIM4_ETR, TIM8_CH1N,
TSC_G5_IO1, JTDOTRACESWO, EVENTOUT
-
-
SPI3_MISO, I2S3ext_SD,
SPI1_MISO, USART2_RX,
TIM3_CH1, TIM16_CH1,
TIM17_BKIN, TIM8_CH2N,
TSC_G5_IO2, NJTRST,
EVENTOUT
-
-
SPI3_MOSI, SPI1_MOSI,
I2S3_SD, I2C1_SMBA,
USART2_CK, TIM16_BKIN,
TIM3_CH2, TIM8_CH3N,
TIM17_CH1, EVENTOUT
-
89
90
91
55
56
57
39
40
41
PB3
PB4
PB5
I/O
I/O
I/O
FT
FT
FT
DocID025540 Rev 4
39/134
51
Pinouts and pin description
STM32F358xC
Table 13. STM32F358xC pin definitions (continued)
92
58
42
PB6
I/O
FTf
Notes
I/O structure
Pin name
(function
after
reset)
Pin type
Pin functions
LQFP48
LQFP64
LQFP100
Pin number
-
-
I2C1_SDA, USART1_RX,
TIM3_CH4, TIM4_CH2,
TIM17_CH1N, TIM8_BKIN,
TSC_G5_IO4, EVENTOUT
-
59
43
PB7
I/O
FTf
-
94
60
44
BOOT0
I
B
-
61
45
PB8
I/O
FTf
Additional functions
I2C1_SCL, USART1_TX,
TIM16_CH1N, TIM4_CH1,
TIM8_CH1, TSC_G5_IO3,
TIM8_ETR, TIM8_BKIN2,
EVENTOUT
93
95
Alternate functions
Boot memory selection
-
I2C1_SCL, CAN_RX,
TIM16_CH1, TIM4_CH3,
TIM8_CH2, TIM1_BKIN,
TSC_SYNC, COMP1_OUT,
EVENTOUT
-
I2C1_SDA, CAN_TX,
TIM17_CH1, TIM4_CH4,
TIM8_CH3, IR_OUT,
COMP2_OUT, EVENTOUT
-
96
62
46
PB9
I/O
FTf
-
97
-
-
PE0
I/O
FT
(1)
USART1_TX, TIM4_ETR,
TIM16_CH1, EVENTOUT
-
98
-
-
PE1
I/O
FT
(1)
USART1_RX, TIM17_CH1,
EVENTOUT
-
99
63
47
VSS_1
S
-
-
Ground
100
64
48
VDD_1
S
-
-
Digital power supply
1. Function availability depends on the chosen device.
When using the small packages (48 and 64 pin packages), the GPIO pins which are not present on these packages, must
not be configured in analog mode.
2. PC13, PC14 and PC15 are supplied through the power switch. Since the switch sinks only a limited amount of current
(3 mA), the use of GPIO PC13 to PC15 in output mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF
- These GPIOs must not be used as current sources (e.g. to drive an LED).
After the first backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the
content of the Backup registers which is not reset by the main reset. For details on how to manage these GPIOs, refer to
the Battery backup domain and BKP register description sections in the reference manual.
3. These GPIOs offer a reduced touch sensing sensitivity. It is thus recommended to use them as sampling capacitor I/O
4. This pin is powered by VDDA.
40/134
DocID025540 Rev 4
Port
&
Pin
Name
AF0
PA0
-
PA1
RTC_
REFIN
AF1
AF2
AF3
AF4
AF5
AF6
TIM2_
CH1_
ETR
-
TSC_
G1_IO1
-
-
TIM2_
CH2
-
TSC_
G1_IO2
-
AF7
AF8
AF9
AF10
AF11
AF12
AF14
AF15
-
USART2_ COMP1 TIM8_
CTS
_OUT
BKIN
TIM8_
ETR
-
-
-
EVENT
OUT
-
-
USART2_
RTS_DE
TIM15_
CH1N
-
-
-
-
EVENT
OUT
-
DocID025540 Rev 4
-
TIM2_
CH3
-
TSC_
G1_IO3
-
-
-
USART2_ COMP2 TIM15_
TX
_OUT
CH1
-
-
-
-
EVENT
OUT
PA3
-
TIM2_
CH4
-
TSC_
G1_IO4
-
-
-
USART2_
RX
-
-
-
-
-
EVENT
OUT
PA4
-
TIM3_ TSC_
CH2
G2_IO1
-
SPI1_
NSS
USART2_
CK
-
-
-
-
-
-
EVENT
OUT
PA5
-
TIM2_
CH1_
ETR
TSC_
G2_IO2
-
SPI1_
SCK
-
-
-
-
-
-
-
-
EVENT
OUT
PA6
-
TIM16_ TIM3_ TSC_
TIM8_
CH1
CH1
G2_IO3 BKIN
SPI1_
MISO
TIM1_BKIN
-
COMP1
_OUT
-
-
-
-
-
EVENT
OUT
PA7
-
TIM17_ TIM3_ TSC_
TIM8_
CH1
CH2
G2_IO4 CH1N
SPI1_
MOSI
TIM1_CH1N
-
COMP2
_OUT
-
-
-
-
-
EVENT
OUT
I2C2_
SMBA
I2S2_
MCK
TIM1_CH1
USART1_ COMP3
CK
_OUT
-
TIM4_
ETR
-
-
-
EVENT
OUT
PA8
MCO
-
-
-
-
SPI3_NSS,
I2S3_WS
TIM15_
CH2
PA9
-
-
-
I2C2_
TSC_
G4_IO1 SCL
I2S3_
MCK
TIM1_CH2
USART1_ COMP5 TIM15_
TX
_OUT
BKIN
TIM2_
CH3
-
-
-
EVENT
OUT
PA10
-
TIM17_
BKIN
-
TSC_
I2C2_
G4_IO2 SDA
-
TIM1_CH3
USART1_ COMP6
RX
_OUT
TIM2_
CH4
TIM8_
BKIN
-
-
EVENT
OUT
PA11
-
-
-
-
TIM1_CH1N
USART1_ COMP1
TIM4_
CAN_RX
CTS
_OUT
CH1
TIM1_
BKIN2
-
EVENT
OUT
-
-
-
TIM1_CH4
41/134
Pinouts and pin description
PA2
STM32F358xC
Table 14. Alternate functions for port A
Port
&
Pin
Name
AF0
AF1
AF2
AF3
AF4
AF5
AF6
PA12
-
TIM16_
CH1
-
-
-
-
TIM1_CH2N
PA13
SWDIO TIM16_
-JTMS CH1N
-
TSC_
G4_IO3
-
PA14
SWCLK
-JTCK
-
TSC_
I2C1_
G4_IO4 SDA
PA15 JTDI
TIM2_
CH1_
ETR
TIM8_
CH1
-
I2C1_
SCL
IR_
OUT
AF7
AF8
AF9
AF10
USART1_ COMP2
TIM4_
CAN_TX
RTS_DE
_OUT
CH2
AF11
AF12
AF14
AF15
TIM1_ETR
-
-
EVENT
OUT
USART3_
CTS
-
-
TIM4_
CH3
-
-
-
EVENT
OUT
TIM8_
TIM1_BKIN
CH2
USART2_
TX
-
-
-
-
-
-
EVENT
OUT
SPI1_
NSS
USART2_
RX
-
-
-
-
-
EVENT
OUT
-
SPI3_NSS,
I2S3_WS
TIM1_
BKIN
Pinouts and pin description
42/134
Table 14. Alternate functions for port A (continued)
DocID025540 Rev 4
STM32F358xC
Port
&
Pin
Name
AF0
AF1
PB0
-
-
TIM3_
CH3
TSC_
G3_IO2
PB1
-
-
TIM3_
CH4
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF12
AF15
TIM8_
CH2N
-
TIM1_CH2N
-
-
-
-
-
EVENT
OUT
TSC_
G3_IO3
TIM8_
CH3N
-
TIM1_CH3N
-
COMP4_
OUT
-
-
-
EVENT
OUT
TIM4_
ETR
TSC_
G5_IO1
TIM8_
CH1N
SPI1_
SCK
SPI3_SCK,
I2S3_CK
USART2_
TX
-
-
TIM3_
ETR
-
EVENT
OUT
DocID025540 Rev 4
JTDOTIM2_
TRACES
CH2
WO
PB4
NJTRST
TIM16_ TIM3_
CH1
CH1
TSC_
G5_IO2
TIM8_
CH2N
SPI1_
MISO
SPI3_MISO,
I2S3ext_SD
USART2_
RX
-
-
TIM17_
BKIN
-
EVENT
OUT
PB5
-
TIM16_ TIM3_
BKIN
CH2
TIM8_
CH3N
I2C1_
SMBA
SPI1_
MOSI
SPI3_MOSI,
I2S3_SD
USART2_
CK
-
-
TIM17_
CH1
-
EVENT
OUT
PB6
-
TIM16_ TIM4_
CH1
CH1N
TSC_
G5_IO3
I2C1_SCL
TIM8_CH1
TIM8_
ETR
USART1_
TX
-
-
TIM8_
BKIN2
-
EVENT
OUT
PB7
-
TIM17_ TIM4_
CH2
CH1N
TSC_
G5_IO4
I2C1_
SDA
TIM8_
BKIN
-
USART1_
RX
-
-
TIM3_
CH4
-
EVENT
OUT
PB8
-
TIM16_ TIM4_
CH1
CH3
TSC_
SYNC
I2C1_SCL
-
-
-
COMP1_
CAN_RX
OUT
TIM8_
CH2
PB9
-
TIM17_ TIM4_
CH4
CH1
I2C1_
SDA
-
-
COMP2_
CAN_TX
OUT
TIM8_
CH3
PB10
-
TIM2_
CH3
-
TSC_
SYNC
-
-
-
USART3_
TX
-
-
PB11
-
TIM2_
CH4
-
TSC_
G6_IO1
-
-
-
USART3_
RX
-
PB12
-
-
-
TSC_
G6_IO2
I2C2_
SMBA
SPI2_NSS,
I2S2_WS
TIM1_
BKIN
USART3_
CK
PB13
-
-
-
TSC_
G6_IO3
-
SPI2_SCK,
I2S2_CK
TIM1_
CH1N
USART3_
CTS
IR_OUT
TIM1_
BKIN
EVENT
OUT
-
EVENT
OUT
-
-
EVENT
OUT
-
-
-
EVENT
OUT
-
-
-
-
EVENT
OUT
-
-
-
-
EVENT
OUT
Pinouts and pin description
43/134
PB3
STM32F358xC
Table 15. Alternate functions for port B
Port
&
Pin
Name
AF0
AF1
AF2
AF3
AF4
PB14
-
TIM15_
CH1
-
TSC_
G6_IO4
-
PB15
RTC_
REFIN
TIM15_ TIM15_
CH2
CH1N
-
TIM1_
CH3N
AF5
AF6
SPI2_MISO, TIM1_
I2S2ext_SD CH2N
SPI2_MOSI,
I2S2_SD
-
AF7
AF8
AF9
AF10
AF12
AF15
USART3_
RTS_DE
-
-
-
-
EVENT
OUT
-
-
-
-
-
EVENT
OUT
Pinouts and pin description
44/134
Table 15. Alternate functions for port B (continued)
DocID025540 Rev 4
STM32F358xC
Port &
Pin
Name
AF1
AF2
AF3
AF4
AF5
AF6
AF7
DocID025540 Rev 4
PC0
EVENTOUT
-
-
-
-
-
-
PC1
EVENTOUT
-
-
-
-
-
-
PC2
EVENTOUT
-
-
-
-
-
PC3
EVENTOUT
-
-
-
-
PC4
EVENTOUT
-
-
-
-
-
USART1_TX
PC5
EVENTOUT
-
-
-
USART1_RX
PC6
EVENTOUT
TIM3_CH1
-
TIM8_CH1
-
I2S2_MCK
COMP6_OUT
PC7
EVENTOUT
TIM3_CH2
-
TIM8_CH2
-
I2S3_MCK
COMP5_OUT
PC8
EVENTOUT
TIM3_CH3
-
TIM8_CH3
-
PC9
EVENTOUT
TIM3_CH4
-
TIM8_CH4
I2S_CKIN
TIM8_BKIN2
PC10
EVENTOUT
-
-
TIM8_CH1N
UART4_TX
SPI3_SCK, I2S3_CK
USART3_TX
PC11
EVENTOUT
-
-
TIM8_CH2N
UART4_RX
SPI3_MISO, I2S3ext_SD
USART3_RX
PC12
EVENTOUT
-
-
TIM8_CH3N
UART5_TX
SPI3_MOSI, I2S3_SD
USART3_CK
TIM1_CH1N
COMP7_OUT
TSC_G3_IO1
-
-
-
PC14
-
-
-
PC15
-
-
-
-
-
COMP3_OUT
-
-
-
-
-
-
-
-
-
-
-
-
45/134
Pinouts and pin description
PC13
TIM1_BKIN2
STM32F358xC
Table 16. Alternate functions for port C
Port &
Pin Name
AF1
PD0
EVENTOUT
PD1
EVENTOUT
PD2
EVENTOUT
PD3
AF2
AF3
AF4
AF5
AF6
-
-
-
-
-
-
CAN_RX
DocID025540 Rev 4
-
TIM8_CH4
TIM3_ETR
-
TIM8_BKIN
EVENTOUT
TIM2_CH1_ETR
-
-
-
-
USART2_CTS
PD4
EVENTOUT
TIM2_CH2
-
-
-
-
USART2_RTS_DE
PD5
EVENTOUT
-
-
-
-
-
USART2_TX
PD6
EVENTOUT
TIM2_CH4
-
-
-
-
USART2_RX
PD7
EVENTOUT
TIM2_CH3
-
-
-
-
USART2_CK
PD8
EVENTOUT
-
-
-
-
PD9
EVENTOUT
-
-
-
-
-
USART3_RX
PD10
EVENTOUT
-
-
-
-
-
USART3_CK
PD11
EVENTOUT
-
-
-
-
-
USART3_CTS
PD12
EVENTOUT
TIM4_CH1
TSC_G8_IO1
-
-
-
USART3_RTS_DE
PD13
EVENTOUT
TIM4_CH2
TSC_G8_IO2
-
-
-
-
PD14
EVENTOUT
TIM4_CH3
TSC_G8_IO3
-
-
-
-
PD15
EVENTOUT
TIM4_CH4
TSC_G8_IO4
-
-
UART5_RX
TIM8_BKIN2
AF7
-
-
Pinouts and pin description
46/134
Table 17. Alternate functions for port D
USART3_TX
SPI2_NSS
-
STM32F358xC
Port &
Pin Name
AF0
PE0
-
EVENTOUT
TIM4_ETR
-
TIM16_CH1
-
USART1_TX
PE1
-
EVENTOUT
-
-
TIM17_CH1
-
USART1_RX
AF1
AF2
AF3
AF4
AF6
AF7
PE2
TRACECK
EVENTOUT
TIM3_CH1
TSC_G7_IO1
-
-
-
PE3
TRACED0
EVENTOUT
TIM3_CH2
TSC_G7_IO2
-
-
-
PE4
TRACED1
EVENTOUT
TIM3_CH3
TSC_G7_IO3
-
-
-
PE5
TRACED2
EVENTOUT
TIM3_CH4
TSC_G7_IO4
-
-
-
PE6
TRACED3
EVENTOUT
-
-
-
-
-
DocID025540 Rev 4
PE7
-
EVENTOUT
TIM1_ETR
-
-
-
-
PE8
-
EVENTOUT
TIM1_CH1N
-
-
-
-
PE9
-
EVENTOUT
TIM1_CH1
-
-
-
-
PE10
-
EVENTOUT
TIM1_CH2N
-
-
-
-
PE11
-
EVENTOUT
TIM1_CH2
-
-
-
-
PE12
-
EVENTOUT
TIM1_CH3N
-
-
-
-
PE13
-
EVENTOUT
TIM1_CH3
-
-
-
-
PE14
-
EVENTOUT
TIM1_CH4
-
-
PE15
-
EVENTOUT
TIM1_BKIN
-
-
TIM1_BKIN2
-
STM32F358xC
Table 18. Alternate functions for port E
USART3_RX
Pinouts and pin description
47/134
Port &
Pin Name
AF1
AF2
AF3
PF0
-
-
-
I2C2_SDA
-
PF1
-
-
-
I2C2_SCL
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
AF4
AF5
AF6
TIM1_CH3N
AF7
-
PF2
EVENTOUT
PF4
EVENTOUT
COMP1_OUT
PF6
EVENTOUT
TIM4_CH4
PF9
EVENTOUT
-
TIM15_CH1
-
SPI2_SCK
-
-
PF10
EVENTOUT
-
TIM15_CH2
-
SPI2_SCK
-
-
I2C2_SCL
USART3_RTS_DE
Pinouts and pin description
48/134
Table 19. Alternate functions for port F
DocID025540 Rev 4
STM32F358xC
STM32F358xC
5
Memory mapping
Memory mapping
Figure 7. STM32F358xC memory map
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49/134
51
Memory mapping
STM32F358xC
Table 20. STM32F358xC memory map and peripheral register boundary
addresses
Bus
AHB3
AHB2
AHB1
APB2
50/134
Boundary address
Size
(bytes)
Peripheral
0x5000 0400 - 0x5000 07FF
1K
ADC3 - ADC4
0x5000 0000 - 0x5000 03FF
1K
ADC1 - ADC2
0x4800 1800 - 0x4FFF FFFF
~132 M
0x4800 1400 - 0x4800 17FF
1K
GPIOF
0x4800 1000 - 0x4800 13FF
1K
GPIOE
0x4800 0C00 - 0x4800 0FFF
1K
GPIOD
0x4800 0800 - 0x4800 0BFF
1K
GPIOC
0x4800 0400 - 0x4800 07FF
1K
GPIOB
0x4800 0000 - 0x4800 03FF
1K
GPIOA
0x4002 4400 - 0x47FF FFFF
~128 M
0x4002 4000 - 0x4002 43FF
1K
TSC
0x4002 3400 - 0x4002 3FFF
3K
Reserved
0x4002 3000 - 0x4002 33FF
1K
CRC
0x4002 2400 - 0x4002 2FFF
3K
Reserved
0x4002 2000 - 0x4002 23FF
1K
Flash interface
0x4002 1400 - 0x4002 1FFF
3K
Reserved
0x4002 1000 - 0x4002 13FF
1K
RCC
0x4002 0800 - 0x4002 0FFF
2K
Reserved
0x4002 0400 - 0x4002 07FF
1K
DMA2
0x4002 0000 - 0x4002 03FF
1K
DMA1
0x4001 8000 - 0x4001 FFFF
32 K
Reserved
0x4001 4C00 - 0x4001 7FFF
13 K
Reserved
0x4001 4800 - 0x4001 4BFF
1K
TIM17
0x4001 4400 - 0x4001 47FF
1K
TIM16
0x4001 4000 - 0x4001 43FF
1K
TIM15
0x4001 3C00 - 0x4001 3FFF
1K
Reserved
0x4001 3800 - 0x4001 3BFF
1K
USART1
0x4001 3400 - 0x4001 37FF
1K
TIM8
0x4001 3000 - 0x4001 33FF
1K
SPI1
0x4001 2C00 - 0x4001 2FFF
1K
TIM1
0x4001 0800 - 0x4001 2BFF
9K
Reserved
0x4001 0400 - 0x4001 07FF
1K
EXTI
0x4001 0000 - 0x4001 03FF
1K
SYSCFG + COMP + OPAMP
DocID025540 Rev 4
Reserved
Reserved
STM32F358xC
Memory mapping
Table 20. STM32F358xC memory map and peripheral register boundary
addresses (continued)
Bus
APB1
Boundary address
Size
(bytes)
Peripheral
0x4000 8000 - 0x4000 FFFF
32 K
Reserved
0x4000 7800 - 0x4000 7FFF
2K
Reserved
0x4000 7400 - 0x4000 77FF
1K
DAC (dual)
0x4000 7000 - 0x4000 73FF
1K
PWR
0x4000 6C00 - 0x4000 6FFF
1K
Reserved
0x4000 6800 - 0x4000 6BFF
1K
Reserved
0x4000 6400 - 0x4000 67FF
1K
bxCAN
0x4000 5C00 - 0x4000 63FF
2K
Reserved
0x4000 5800 - 0x4000 5BFF
1K
I2C2
0x4000 5400 - 0x4000 57FF
1K
I2C1
0x4000 5000 - 0x4000 53FF
1K
UART5
0x4000 4C00 - 0x4000 4FFF
1K
UART4
0x4000 4800 - 0x4000 4BFF
1K
USART3
0x4000 4400 - 0x4000 47FF
1K
USART2
0x4000 4000 - 0x4000 43FF
1K
I2S3ext
0x4000 3C00 - 0x4000 3FFF
1K
SPI3/I2S3
0x4000 3800 - 0x4000 3BFF
1K
SPI2/I2S2
0x4000 3400 - 0x4000 37FF
1K
I2S2ext
0x4000 3000 - 0x4000 33FF
1K
IWDG
0x4000 2C00 - 0x4000 2FFF
1K
WWDG
0x4000 2800 - 0x4000 2BFF
1K
RTC
0x4000 1800 - 0x4000 27FF
4K
Reserved
0x4000 1400 - 0x4000 17FF
1K
TIM7
0x4000 1000 - 0x4000 13FF
1K
TIM6
0x4000 0C00 - 0x4000 0FFF
1K
Reserved
0x4000 0800 - 0x4000 0BFF
1K
TIM4
0x4000 0400 - 0x4000 07FF
1K
TIM3
0x4000 0000 - 0x4000 03FF
1K
TIM2
DocID025540 Rev 4
51/134
51
Electrical characteristics
STM32F358xC
6
Electrical characteristics
6.1
Parameter conditions
Unless otherwise specified, all voltages are referenced to VSS.
6.1.1
Minimum and maximum values
Unless otherwise specified, the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean±3σ).
6.1.2
Typical values
Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 1.8 V, VDDA = 3.3 V.
They are given only as design guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean±2σ).
6.1.3
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
6.1.4
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 8.
6.1.5
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 9.
Figure 8. Pin loading conditions
Figure 9. Pin input voltage
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9,1
069
52/134
DocID025540 Rev 4
069
STM32F358xC
6.1.6
Electrical characteristics
Power supply scheme
Figure 10. Power supply scheme
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1. Dotted lines represent the internal connections on low pin count packages, joining the dedicated supply
pins.
Caution:
Each power supply pair (VDD/VSS, VDDA/VSSA etc..) must be decoupled with filtering
ceramic capacitors as shown above. These capacitors must be placed as close as possible
to, or below the appropriate pins on the underside of the PCB to ensure the good
functionality of the device.
6.1.7
Current consumption measurement
Figure 11. Current consumption measurement scheme
)$$
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-36
DocID025540 Rev 4
53/134
118
Electrical characteristics
6.2
STM32F358xC
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 21: Voltage characteristics,
Table 22: Current characteristics, and Table 23: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of
the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Table 21. Voltage characteristics(1)
Symbol
Ratings
Min
Max
VDD– VSS
External digital supply voltage (including VDD and
VBAT)
-0.3
1.95
VDDA– VSS
External analog supply voltage
-0.3
4.0
VDD– VDDA
Allowed voltage difference for VDD > VDDA
-
0.4
Allowed voltage difference for VREF+ > VDDA
-
0.4
Input voltage on FT and FTf pins
VSS − 0.3
VDD + 4.0
Input voltage on TTa pins
VSS − 0.3
4.0
Input voltage on any other pin
VSS − 0.3
4.0
Input voltage on POR pin
VSS − 0.3
VDDA + 4.0
Input Voltage on B Pin
0
9
Variations between different VDD power pins
-
50
Variations between all the different ground pins
-
50
VREF+–VDDA(2)
VIN(3)
|ΔVDDx|
|VSSX − VSS|
VESD(HBM)
Electrostatic discharge voltage (human body
model)
Unit
V
mV
see Section 6.3.11: Electrical
sensitivity characteristics
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the
permitted range. The following relationship must be respected between VDDA and VDD:
VDDA must power on before or at the same time as VDD in the power up sequence.
VDDA must be greater than or equal to VDD.
2. VREF+ must be always lower or equal than VDDA (VREF+ ≤ VDDA). If unused then it must be connected to VDDA.
3. VIN maximum must always be respected. Refer to Table 22: Current characteristics for the maximum allowed injected
current values.
54/134
DocID025540 Rev 4
-
STM32F358xC
Electrical characteristics
Table 22. Current characteristics
Symbol
Ratings
Max.
ΣIVDD
Total current into sum of all VDD_x power lines (source)
160
ΣIVSS
Total current out of sum of all VSS_x ground lines (sink)
− 160
(1)
IVDD
Maximum current into each VDD_x power line (source)
IVSS
Maximum current out of each VSS _x ground line (sink)(1)
IIO(PIN)
ΣIIO(PIN)
25
−25
(2)
80
Total output current sourced by sum of all IOs and control pins(2)
Injected current on TC and RST
Injected current on TTa pins
ΣIINJ(PIN)
− 100
Output current source by any I/O and control pin
Injected current on FT, FTf, POR and B
IINJ(PIN)
100
Output current sunk by any I/O and control pin
Total output current sunk by sum of all IOs and control pins
Unit
mA
− 80
pins(3)
-5/+0
pin(4)
±5
(5)
±5
Total injected current (sum of all I/O and control pins)(6)
± 25
1. All main power (VDD, VDDA) and ground (VSS and VSSA) pins must always be connected to the external power supply, in the
permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins.The total output current must not be
sunk/sourced between two consecutive power supply pins referring to high pin count LQFP packages.
3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum
value.
4. A positive injection is induced by VIN > VDD while a negative injection is induced by VIN< VSS. IINJ(PIN) must never be
exceeded. Refer to Table 21: Voltage characteristics for the maximum allowed input voltage values.
5. A positive injection is induced by VIN > VDDA while a negative injection is induced by VIN< VSS. IINJ(PIN) must never be
exceeded. Refer also to Table 21: Voltage characteristics for the maximum allowed input voltage values. Negative injection
disturbs the analog performance of the device. See note (2) below Table 66.
6. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive and
negative injected currents (instantaneous values).
Table 23. Thermal characteristics
Symbol
TSTG
TJ
Ratings
Storage temperature range
Maximum junction temperature
DocID025540 Rev 4
Value
Unit
–65 to +150
°C
150
°C
55/134
118
Electrical characteristics
STM32F358xC
6.3
Operating conditions
6.3.1
General operating conditions
Table 24. General operating conditions
Symbol
Parameter
fHCLK
Min
Max
Internal AHB clock frequency
0
72
fPCLK1
Internal APB1 clock frequency
0
36
fPCLK2
Internal APB2 clock frequency
0
72
Standard operating voltage
1.65
1.95
Analog operating voltage
(OPAMP and DAC not used)
1.65
3.6
2.4
3.6
1.8 V
3.6 V
1.65
3.6
TC I/O
–0.3
VDD+0.3
TTa I/O and POR I/O pins
–0.3
VDDA+0.3
FT, FTf I/O pins
–0.3
5.2
BOOT0
0
5.2
LQFP100
-
488
LQFP64
-
444
LQFP48
-
364
Maximum power
dissipation
–40
85
Low-power dissipation(2)
–40
105
Maximum power
dissipation
–40
105
–40
125
6 suffix version
–40
105
7 suffix version
–40
125
VDD
VDDA
Analog operating voltage
(OPAMP and DAC used)
Analog operating voltage
(ADC used)
VBAT
VIN
PD
Must have a potential
equal to or higher than
VDD
Backup operating voltage
I/O input voltage
Power dissipation at TA =
85 °C for suffix 6 or TA =
105 °C for suffix 7(1)
Ambient temperature for 6
suffix version
TA
Ambient temperature for 7
suffix version
TJ
Conditions
Junction temperature range
Low-power
dissipation(2)
Unit
MHz
V
V
V
V
mW
°C
°C
°C
1. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Table 23: Thermal
characteristics).
2. In low-power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see
Table 23: Thermal characteristics).
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DocID025540 Rev 4
STM32F358xC
6.3.2
Electrical characteristics
Operating conditions at power-up / power-down
The parameters given in Table 25 are derived from tests performed under the ambient
temperature condition summarized in Table 24.
Table 25. Operating conditions at power-up / power-down
Symbol
tVDD
tVDDA
6.3.3
Parameter
Conditions
VDD rise time rate
-
VDD fall time rate
VDDA rise time rate
-
VDDA fall time rate
Min
Max
0
∞
20
∞
0
∞
20
∞
Unit
µs/V
Embedded reference voltage
The parameters given in Table 26 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 24.
Table 26. Embedded internal reference voltage
Symbol
Parameter
VREFINT
Internal reference voltage
TS_vrefint
VRERINT
TCoeff
TREFINT_RDY(3)
Conditions
Min
Typ
Max
Unit
–40 °C < TA < +105 °C
1.16
1.2
1.25
V
V
–40 °C < TA < +85 °C
1.16
1.2
1.24(1)
ADC sampling time when
reading the internal
reference voltage
-
2.2
-
-
µs
Internal reference voltage
spread over the
temperature range
VDD = 1.8 V ±10 mV
-
-
10(2)
mV
Temperature coefficient
-
-
-
100(2) ppm/°C
Internal reference voltage
temporization
-
1.5
2.5
4.5
ms
1. Data based on characterization results, not tested in production.
2. Guaranteed by design, not tested in production.
3. Guaranteed by design, not tested in production. Latency between the time when pin NPOR is set to 1 by
the application and the time when VREFINTRDYF is set to 1 by the hardware.
Table 27. Internal reference voltage calibration values
Calibration value name
VREFINT_CAL
Description
Raw data acquired at
temperature of 30 °C
VDDA= 3.3 V
DocID025540 Rev 4
Memory address
0x1FFF F7BA - 0x1FFF F7BB
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118
Electrical characteristics
6.3.4
STM32F358xC
Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 11: Current consumption
measurement scheme.
All Run-mode current consumption measurements given in this section are performed with a
reduced code that gives a consumption equivalent to CoreMark code.
Typical and maximum current consumption
The MCU is placed under the following conditions:
•
All I/O pins are in input mode with a static value at VDD or VSS (no load)
•
All peripherals are disabled except when explicitly mentioned
•
The Flash memory access time is adjusted to the fHCLK frequency (0 wait state from 0
to 24 MHz,1 wait state from 24 to 48 MHz and 2 wait states from 48 to 72 MHz)
•
Prefetch in ON (reminder: this bit must be set before clock setting and bus prescaling)
•
When the peripherals are enabled fPCLK2 = fHCLK and fPCLK1 = fHCLK/2
•
When fHCLK > 8 MHz, the PLL is ON and the PLL input is equal to HSI/2 (4 MHz) or
HSE (8 MHz) in bypass mode.
The parameters given in Table 28 to Table 37 are derived from tests performed under
ambient temperature and supply voltage conditions summarized in Table 24.
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STM32F358xC
Electrical characteristics
Table 28. Typical and maximum current consumption from VDD supply
at VDD = 1.8 V
All peripherals enabled
Symbol Parameter Conditions
Supply
current in
Run mode,
executing
from Flash
External
clock (HSE
bypass)
Internal
clock (HSI)
IDD
fHCLK
Max @ TA(1)
Typ
Supply
current in
Run mode,
executing
from RAM
Internal
clock (HSI)
Max @ TA(1)
Typ
25 °C
85 °C
105 °C
72 MHz 60.4
65.4
66.6
67.8
64 MHz 54.1
58.6
59.8
48 MHz 41.5
45.0
32 MHz 28.2
Unit
25 °C
85 °C
105 °C
27.3
29.6
30.3
31.0
60.9
24.5
26.5
27.3
27.9
46.1
47.0
18.8
20.4
21.0
21.7
30.6
31.6
32.4
12.9
14.0
14.5
15.1
24 MHz 21.5
23.4
24.2
24.9
9.8
10.8
11.3
11.8
8 MHz
7.2
8.0
8.6
9.1
3.3
3.8
4.1
4.8
1 MHz
1.1
1.4
1.6
2.4
0.6
0.8
1.1
1.9
64 MHz 49.4
53.6
54.6
55.7
24.3
26.3
27.0
27.6
48 MHz 37.9
41.2
42.1
43.0
18.6
20.3
20.8
21.4
32 MHz 25.8
28.1
29.0
29.7
12.7
13.9
14.4
14.9
24 MHz 19.7
21.4
22.3
22.9
6.6
7.3
7.8
8.3
8 MHz
7.5
8.0
8.6
3.3
3.7
4.1
4.8
72 MHz 61.3 66,5
67.6
68,9(2)
28.3
30,6(2)
31.5
32,2(2)
64 MHz 54.9
59.5
60.6
61.9
25.3
27.4
28.1
28.8
48 MHz 41.7
45.3
46.4
47.3
19.1
20.7
21.3
22.0
32 MHz 28.2
30.7
31.7
32.4
12.8
14.0
14.6
15.1
24 MHz 21.3
23.2
24.0
24.7
9.7
10.6
11.1
11.6
8 MHz
7.0
7.8
8.3
8.9
3.1
3.4
4.0
4.6
1 MHz
0.7
0.9
1.3
2.1
0.2
0.4
0.8
1.5
64 MHz 50.0
54.2
55.4
56.5
24.9
27.0
27.7
28.3
48 MHz 38.0
41.3
42.3
43.2
18.7
20.4
21.0
21.6
32 MHz 25.7
27.9
28.8
29.6
12.6
13.7
14.2
14.8
24 MHz 19.4
21.1
22.0
22.6
6.3
7.0
7.4
8.0
8 MHz
7.2
7.7
8.2
3.0
3.3
3.9
4.4
6.8
(2)
External
clock (HSE
bypass)
All peripherals disabled
6.4
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mA
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Electrical characteristics
STM32F358xC
Table 28. Typical and maximum current consumption from VDD supply
at VDD = 1.8 V (continued)
All peripherals enabled
Symbol Parameter Conditions
IDD
Supply
current in
Sleep
mode,
executing
from Flash
or RAM
External
clock (HSE
bypass)
Internal
clock (HSI)
fHCLK
Max @ TA(1)
Typ
All peripherals disabled
Max @ TA(1)
Typ
25 °C
85 °C
105 °C
72 MHz 44.2
48.2
49.4
50.5
64 MHz 39.5
43.1
44.3
48 MHz 29.9
32.7
32 MHz 20.2
Unit
25 °C
85 °C
105 °C
6.6
7.2
7.8
8.4
45.2
5.8
6.5
7.0
7.6
33.8
34.6
4.4
4.9
5.5
6.0
22.1
23.0
23.7
3.0
3.3
3.9
4.5
24 MHz 15.2
16.7
17.5
18.2
2.3
2.5
3.0
3.7
8 MHz
4.9
5.6
6.1
6.7
0.6
0.8
1.2
2.0
1 MHz
0.5
0.7
1.0
1.8
0.1
0.0
0.4
1.2
64 MHz 34.5
37.7
38.9
39.7
5.5
6.2
6.6
7.2
48 MHz 26.1
28.6
29.7
30.4
4.1
4.6
5.1
5.7
32 MHz 17.6
19.3
20.2
20.8
2.7
3.0
3.5
4.2
24 MHz 13.3
14.7
15.4
16.0
1.3
1.6
2.0
2.7
8 MHz
4.9
5.5
6.1
0.5
0.7
1.0
1.9
4.4
mA
1. Data based on characterization results, not tested in production unless otherwise specified.
2. Data based on characterization results and tested in production with code executing from RAM.
Table 29. Typical and maximum current consumption from the VDDA supply
VDDA = 2.4 V
Symbol Parameter
IDDA
Supply
current in
Run/Sleep
mode,
code
executing
from Flash
or RAM
Conditions
(1)
HSE
bypass
HSI clock
fHCLK
Typ
VDDA = 3.6 V
Max @ TA(2)
25 °C
85 °C 105 °C
Typ
Max @ TA(2)
25 °C
Unit
85 °C 105 °C
72 MHz
225
276
289
297
245
302
319
329
64 MHz
198
249
261
268
216
270
284
293
48 MHz
149
195
204
211
159
209
222
230
32 MHz
102
145
152
157
110
154
162
169
24 MHz
80
119
124
128
86
126
131
135
8 MHz
2
3
4
6
3
4
5
9
1 MHz
2
3
5
7
3
4
6
9
64 MHz
270
323
337
344
299
354
371
381
48 MHz
220
269
280
286
244
293
309
318
32 MHz
173
218
228
233
193
239
251
257
24 MHz
151
194
200
204
169
211
219
225
8 MHz
73
97
99
103
88
105
110
116
1. Current consumption from the VDDA supply is independent of whether the peripherals are on or off. Furthermore when the
PLL is off, IDDA is independent from the frequency.
60/134
DocID025540 Rev 4
µA
STM32F358xC
Electrical characteristics
2. Data based on characterization results, not tested in production.
Table 30. Typical and maximum VDD consumption in Stop mode
Max(1)
Symbol Parameter
IDD
Conditions
[email protected] (VDD=VDDA=1.8V)
Supply
All oscillators
current in
OFF
Stop mode
Unit
TA=25 °C
TA=85 °C TA=105 °C
31.1(2)
6.6
1225.8(2)
560.5
µA
1. Data based on characterization results, not tested in production unless otherwise specified.
2. Data based on characterization results and tested in production.
Table 31. Typical and maximum VDDA consumption in Stop mode
Max(1)
[email protected](VDD = 1.8V)
Symbol Parameter Conditions
1.8 V 2.0 V 2.4 V 2.7 V 3.0 V 3.3 V 3.6 V
IDDA
Supply
current in
Stop mode
All
oscillators
OFF
0.76
0.78
0.80
0.83
0.87
0.94
1.01
TA=
25 °C
3.2
TA=
TA=
85 °C 105 °C
5.3
7.9
Unit
µA
1. Data based on characterization results and tested in production.
Note:
The total current consumption is the sum of IDD and IDDA
Table 32. Typical and maximum current consumption from VBAT supply
Symbol
Para
meter
Max
@VBAT = 3.6 V(2)
Typ @VBAT
Conditions
(1)
LSE & RTC
ON; "Xtal
mode"
lower
driving
capability;
Backup LSEDRV[1:
domain 0] = '00'
IDD_VBAT
supply LSE & RTC
current ON; "Xtal
mode"
higher
driving
capability;
LSEDRV[1:
0] = '11'
1.65V
1.8V
2V
0.48
0.50
0.52
2.4V 2.7V
0.58
3V
Unit
T = TA = TA =
3.3V 3.6V A
25°C 85°C 105°C
0.65 0.72 0.80 0.90
1.1
1.5
2.0
µA
0.83
0.86
0.90
0.98
1.03 1.10 1.20 1.30
1.5
2.2
2.9
1. Crystal used: Abracon ABS07-120-32.768 kHz-T with a CL of 6 pF for typical values.
2. Data based on characterization results, not tested in production.
DocID025540 Rev 4
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118
Electrical characteristics
STM32F358xC
Figure 12. Typical VBAT current consumption (LSE and RTC ON/LSEDRV[1:0] = ’00’)
6
6
6
6
6
6
)
6"!4—!
6
6
#
#
#
#
4! #
-36
Typical current consumption
The MCU is placed under the following conditions:
62/134
•
VDD = 1.8 V, VDDA = 3.3 V
•
All I/O pins available on each package are in analog input configuration
•
The Flash access time is adjusted to fHCLK frequency (0 wait states from 0 to 24 MHz,
1 wait state from 24 to 48 MHz and 2 wait states from 48 MHz to 72 MHz), and Flash
prefetch is ON
•
When the peripherals are enabled, fAPB1 = fAHB/2, fAPB2 = fAHB
•
PLL is used for frequencies greater than 8 MHz
•
AHB prescaler of 2, 4, 8,16 and 64 is used for the frequencies 4 MHz, 2 MHz, 1 MHz,
500 kHz and 125 kHz respectively.
DocID025540 Rev 4
STM32F358xC
Electrical characteristics
Table 33. Typical current consumption in Run mode, code with data processing
running from Flash
Typ
Symbol
IDD
Parameter
Conditions
Supply current in
Run mode from
VDD supply
Running from HSE
crystal clock 8 MHz,
code executing from
Flash
IDDA(1) (2)
Supply current in
Run mode from
VDDA supply
fHCLK
Peripherals
enabled
Peripherals
disabled
72 MHz
58.6
26.5
64 MHz
52.6
23.7
48 MHz
40.6
18.5
32 MHz
27.6
12.7
24 MHz
21.1
9.9
16 MHz
14.3
6.8
8 MHz
7.2
3.5
4 MHz
4.1
2.1
2 MHz
2.3
1.3
1 MHz
1.5
0.9
500 kHz
1.0
0.7
125 kHz
0.7
0.5
72 MHz
239.0
64 MHz
210.3
48 MHz
157.0
32 MHz
108.1
24 MHz
84.4
16 MHz
60.8
8 MHz
1.0
4 MHz
1.0
2 MHz
1.0
1 MHz
1.0
500 kHz
1.0
125 kHz
1.0
Unit
mA
µA
1. VDDA monitoring is ON.
2. When peripherals are enabled, the power consumption of the analog part of peripherals such as ADC, DAC, Comparators,
OpAmp etc. is not included. Refer to the tables of characteristics in the subsequent sections.
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Electrical characteristics
STM32F358xC
Table 34. Typical current consumption in Sleep mode, code running from Flash or RAM
Typ
Symbol
IDD
Parameter
Conditions
Supply current in
Sleep mode from
VDD supply
Running from HSE
crystal clock 8 MHz,
code executing from
Flash or RAM
IDDA(1) (2)
Supply current in
Sleep mode from
VDDA supply
fHCLK
Peripherals
enabled
Peripherals
disabled
72 MHz
42.5
6.5
64 MHz
38.0
5.8
48 MHz
28.8
4.4
32 MHz
19.4
3.0
24 MHz
14.6
2.3
16 MHz
9.8
1.6
8 MHz
4.8
0.8
4 MHz
2.9
0.6
2 MHz
1.7
0.5
1 MHz
1.2
0.5
500 kHz
0.9
0.5
125 kHz
0.7
Unit
mA
0.5
72 MHz
239.0
64 MHz
210.3
48 MHz
157.0
32 MHz
108.1
24 MHz
84.4
16 MHz
60.8
8 MHz
1.0
4 MHz
1.0
2 MHz
1.0
1 MHz
1.0
500 kHz
1.0
125 kHz
1.0
µA
1. VDDA monitoring is ON
2. When peripherals are enabled, the power consumption of the analog part of peripherals such as ADC, DAC, Comparators,
OpAmp etc. is not included. Refer to the tables of characteristics in the subsequent sections.
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STM32F358xC
Electrical characteristics
I/O system current consumption
The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull-up generate current consumption when the pin is
externally held low. The value of this current consumption can be simply computed by using
the pull-up/pull-down resistors values given in Table 52: I/O static characteristics.
For the output pins, any external pull-down or external load must also be considered to
estimate the current consumption.
Additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins which should be
configured as analog inputs.
Caution:
Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
I/O dynamic current consumption
In addition to the internal peripheral current consumption (seeTable 36: Peripheral current
consumption), the I/Os used by an application also contribute to the current consumption.
When an I/O pin switches, it uses the current from the MCU supply voltage to supply the I/O
pin circuitry and to charge/discharge the capacitive load (internal or external) connected to
the pin:
I SW = V DD × f SW × C
where
ISW is the current sunk by a switching I/O to charge/discharge the capacitive load
VDD is the MCU supply voltage
fSW is the I/O switching frequency
C is the total capacitance seen by the I/O pin: C = CINT+ CEXT+CS
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.
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Electrical characteristics
STM32F358xC
Table 35. Switching output I/O current consumption
Symbol
Parameter
Conditions(1)
VDD = 1.8 V
Cext = 0 pF
C = CINT + CEXT+ CS
VDD = 1.8 V
Cext = 10 pF
C = CINT + CEXT +CS
ISW
I/O current
consumption
VDD = 1.8 V
Cext = 22 pF
C = CINT + CEXT +CS
VDD = 1.8 V
Cext = 33 pF
C = CINT + CEXT+ CS
VDD = 1.8 V
Cext = 47 pF
C = CINT + CEXT+ CS
1. CS = 5 pF (estimated value).
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DocID025540 Rev 4
I/O toggling
frequency (fSW)
Typ
2 MHz
0.10
4 MHz
0.17
8 MHz
0.40
18 MHz
0.78
36 MHz
1.51
48 MHz
2.06
2 MHz
0.14
4 MHz
0.25
8 MHz
0.57
18 MHz
1.16
36 MHz
2.45
48 MHz
3.03
2 MHz
0.19
4 MHz
0.36
8 MHz
0.75
18 MHz
1.59
36 MHz
3.25
2 MHz
0.23
4 MHz
0.45
8 MHz
0.94
18 MHz
1.97
36 MHz
3.62
2 MHz
0.28
4 MHz
0.55
8 MHz
1.15
18 MHz
2.42
Unit
mA
STM32F358xC
Electrical characteristics
On-chip peripheral current consumption
The MCU is placed under the following conditions:
•
all I/O pins are in analog input configuration
•
all peripherals are disabled unless otherwise mentioned
•
the given value is calculated by measuring the current consumption
•
–
with all peripherals clocked off
–
with only one peripheral clocked on
ambient operating temperature at 25°C and VDD = 1.8 V, VDDA = 3.3 V.
Table 36. Peripheral current consumption
Peripheral
Typical consumption(1)
Unit
IDD
BusMatrix (2)
12.6
DMA1
7.6
DMA2
6.1
CRC
2.1
GPIOA
10.0
GPIOB
10.3
GPIOC
2.2
GPIOD
8.8
GPIOE
3.3
GPIOF
3.0
TSC
5.5
ADC1&2
17.3
ADC3&4
18.8
APB2-Bridge (3)
3.6
SYSCFG
7.3
TIM1
40.0
SPI1
8.8
TIM8
36.4
USART1
23.3
TIM15
17.1
TIM16
10.1
TIM17
APB1-Bridge
µA/MHz
11.0
(3)
6.1
TIM2
49.1
TIM3
38.8
TIM4
38.3
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Electrical characteristics
STM32F358xC
Table 36. Peripheral current consumption (continued)
Peripheral
Typical consumption(1)
Unit
IDD
TIM6
9.7
TIM7
12.1
WWDG
6.4
SPI2
40.4
SPI3
40.0
USART2
41.9
USART3
40.2
UART4
36.5
UART5
30.8
I2C1
10.5
I2C2
10.4
CAN
33.4
PWR
5.7
DAC
15.4
µA/MHz
1. The power consumption of the analog part (IDDA) of peripherals such as ADC, DAC, Comparators, OpAmp
etc. is not included. Refer to the tables of characteristics in the subsequent sections.
2. BusMatrix is automatically active when at least one master is ON (CPU, DMA1 or DMA2).
3. The APBx bridge is automatically active when at least one peripheral is ON on the same bus.
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STM32F358xC
6.3.5
Electrical characteristics
Wakeup time from low-power mode
The wakeup times given in Table 37 are measured starting from the wakeup event trigger up
to the first instruction executed by the CPU:
•
For Stop or Sleep mode: the wakeup event is WFE.
•
WKUP1 (PA0) pin is used to wakeup from Stop and Sleep modes.
All timings are derived from tests performed under ambient temperature and VDD supply
voltage conditions summarized in Table 24.
Table 37. Low-power mode wakeup timings
Symbol
Parameter
Typ @VDD = 1.8 V, VDDA = 3.3V Max
Unit
tWUSTOP
Wakeup from Stop mode
3.8
5.3
µs
tWUSLEEP
Wakeup from Sleep mode
6
-
CPU clock cycles
69.2
100
µs
tWUPOR
Wakeup from Power off
state
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Electrical characteristics
6.3.6
STM32F358xC
External clock source characteristics
High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO. The
external clock signal has to respect the I/O characteristics in Section 6.3.13. However, the
recommended clock input waveform is shown in Figure 13.
Table 38. High-speed external user clock characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
1
8
32
MHz
fHSE_ext
User external clock source
frequency(1)
VHSEH
OSC_IN input pin high level voltage
0.7VDD
-
VDD
VHSEL
OSC_IN input pin low level voltage
VSS
-
0.3VDD
15
-
-
-
-
20
tw(HSEH)
tw(HSEL)
tr(HSE)
tf(HSE)
OSC_IN high or low
-
time(1)
V
ns
OSC_IN rise or fall time(1)
1. Guaranteed by design, not tested in production.
Figure 13. High-speed external clock source AC timing diagram
WZ+6(+
9+6(+
9+6(/
WU+6(
WI+6(
WZ+6(/
W
7+6(
069
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STM32F358xC
Electrical characteristics
Low-speed external user clock generated from an external source
In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO. The
external clock signal has to respect the I/O characteristics in Section 6.3.13. However, the
recommended clock input waveform is shown in Figure 14
Table 39. Low-speed external user clock characteristics
Symbol
Parameter
Conditions
fLSE_ext
User External clock source
frequency(1)
VLSEH
OSC32_IN input pin high level
voltage
VLSEL
OSC32_IN input pin low level
voltage
tw(LSEH)
tw(LSEL)
OSC32_IN high or low time(1)
tr(LSE)
tf(LSE)
Min
Typ
Max
Unit
-
32.768
1000
kHz
0.7VDD
-
VDD
V
-
VSS
-
0.3VDD
450
-
ns
OSC32_IN rise or fall
time(1)
-
-
50
1. Guaranteed by design, not tested in production.
Figure 14. Low-speed external clock source AC timing diagram
WZ/6(+
9/6(+
9/6(/
WU/6(
WI/6(
WZ/6(/
W
7/6(
069
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Electrical characteristics
STM32F358xC
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 32 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on design
simulation results obtained with typical external components specified in Table 40. In the
application, the resonator and the load capacitors have to be placed as close as possible to
the oscillator pins in order to minimize output distortion and startup stabilization time. Refer
to the crystal resonator manufacturer for more details on the resonator characteristics
(frequency, package, accuracy).
Table 40. HSE oscillator characteristics
Symbol
fOSC_IN
RF
Parameter
Conditions(1)
Min(2)
Typ
Max(2)
Unit
4
8
32
MHz
-
200
-
-
8.5
VDD=3.3 V, Rm= 30Ω,
CL=10 [email protected] MHz
-
0.4
-
VDD=3.3 V, Rm= 45Ω,
CL=10 [email protected] MHz
-
0.5
-
VDD=3.3 V, Rm= 30Ω,
CL=5 [email protected] MHz
-
0.8
-
VDD=3.3 V, Rm= 30Ω,
CL=10 [email protected] MHz
-
1
-
VDD=3.3 V, Rm= 30Ω,
CL=20 [email protected] MHz
-
1.5
-
Startup
10
-
-
mA/V
VDD is stabilized
-
2
-
ms
Oscillator frequency
Feedback resistor
During startup
IDD
gm
tSU(HSE)(4)
HSE current consumption
Oscillator transconductance
Startup time
(3)
kΩ
mA
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
2. Guaranteed by design, not tested in production.
3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time.
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer.
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STM32F358xC
Electrical characteristics
For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 15). CL1 and CL2 are usually the
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF
can be used as a rough estimate of the combined pin and board capacitance) when sizing
CL1 and CL2.
Note:
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
Figure 15. Typical application with an 8 MHz crystal
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26&B,1
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UHVRQDWRU
&/
5(;7 I+6(
5)
%LDV
FRQWUROOHG
JDLQ
26&B287
069
1. REXT value depends on the crystal characteristics.
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Electrical characteristics
STM32F358xC
Low-speed external clock generated from a crystal/ceramic resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on design
simulation results obtained with typical external components specified in Table 41. In the
application, the resonator and the load capacitors have to be placed as close as possible to
the oscillator pins in order to minimize output distortion and startup stabilization time. Refer
to the crystal resonator manufacturer for more details on the resonator characteristics
(frequency, package, accuracy).
Table 41. LSE oscillator characteristics (fLSE = 32.768 kHz)
Symbol
IDD
gm
tSU(LSE)(3)
Parameter
LSE current consumption
Oscillator
transconductance
Startup time
Conditions(1)
Min(2)
Typ
Max(2)
LSEDRV[1:0]=00
lower driving capability
-
0.5
0.9
LSEDRV[1:0]=01
medium low driving capability
-
-
1
LSEDRV[1:0]=10
medium high driving capability
-
-
1.3
LSEDRV[1:0]=11
higher driving capability
-
-
1.6
LSEDRV[1:0]=00
lower driving capability
5
-
-
LSEDRV[1:0]=01
medium low driving capability
8
-
-
LSEDRV[1:0]=10
medium high driving capability
15
-
-
LSEDRV[1:0]=11
higher driving capability
25
-
-
VDD is stabilized
-
2
-
Unit
µA
µA/V
s
1. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for
ST microcontrollers”.
2. Guaranteed by design, not tested in production.
3.
tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is
reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer.
Note:
74/134
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
DocID025540 Rev 4
STM32F358xC
Electrical characteristics
Figure 16. Typical application with a 32.768 kHz crystal
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FDSDFLWRUV
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26&B,1
I+6(
'ULYH
SURJUDPPDEOH
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&/
069
Note:
An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden
to add one.
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Electrical characteristics
6.3.7
STM32F358xC
Internal clock source characteristics
The parameters given in Table 42 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 24.
High-speed internal (HSI) RC oscillator
Table 42. HSI oscillator characteristics(1)
Symbol
Parameter
fHSI
TRIM
Conditions
Min
Typ
Max
Unit
Frequency
-
-
8
-
MHz
HSI user trimming step
-
-
-
1(2)
%
-
(2)
Duty cycle
DuCy(HSI)
Accuracy of the HSI oscillator
ACCHSI
45
IDDA(HSI)
-
55
%
TA = -40 to
105°C
-2.8(3)
-
3.8(3)
TA = -10 to 85°C
-1.9(3)
-
2.3(3)
TA = 0 to 85°C
-1.9(3)
-
2(3)
TA = 0 to 70°C
-1.3(3)
-
2(3)
TA = 0 to 55°C
-1(3)
-
2(3)
-1
-
1
-
2(2)
µs
80
100(2)
µA
TA = 25°C(4)
tsu(HSI)
(2)
HSI oscillator startup time
-
1(2)
HSI oscillator power
consumption
-
-
%
1. VDDA = 3.3 V, TA = –40 to 105 °C unless otherwise specified.
2. Guaranteed by design, not tested in production.
3. Data based on characterization results, not tested in production.
4. Factory calibrated, parts not soldered.
Figure 17. HSI oscillator accuracy characterization results for soldered parts
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069
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Electrical characteristics
Low-speed internal (LSI) RC oscillator
Table 43. LSI oscillator characteristics(1)
Symbol
fLSI
tsu(LSI)
Parameter
Min
Typ
Max
Unit
30
40
50
kHz
LSI oscillator startup time
-
-
85
µs
LSI oscillator power consumption
-
0.75
1.2
µA
Frequency
(2)
IDD(LSI)(2)
1. VDDA = 3.3 V, TA = –40 to 105 °C unless otherwise specified.
2. Guaranteed by design, not tested in production.
6.3.8
PLL characteristics
The parameters given in Table 44 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 24.
Table 44. PLL characteristics
Value
Symbol
fPLL_IN
fPLL_OUT
Parameter
Unit
Min
Typ
Max
1(2)
-
24(2)
MHz
PLL input clock duty cycle
(2)
40
-
60(2)
%
PLL multiplier output clock
16(2)
-
72
MHz
PLL input clock(1)
tLOCK
PLL lock time
-
-
200(2)
µs
Jitter
Cycle-to-cycle jitter
-
-
300(2)
ps
1. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with
the range defined by fPLL_OUT.
2. Guaranteed by design, not tested in production.
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Electrical characteristics
6.3.9
STM32F358xC
Memory characteristics
Flash memory
The characteristics are given at TA = –40 to 105 °C unless otherwise specified.
Table 45. Flash memory characteristics
Min
Typ
Max(1)
Unit
16-bit programming time TA = –40 to +105 °C
40
53.5
60
µs
Page (2 KB) erase time
TA = –40 to +105 °C
20
-
40
ms
tME
Mass erase time
TA = –40 to +105 °C
20
-
40
ms
IDD
Supply current
Write mode
-
-
10
mA
Erase mode
-
-
12
mA
Symbol
tprog
tERASE
Parameter
Conditions
1. Guaranteed by design, not tested in production.
Table 46. Flash memory endurance and data retention
Value
Symbol
NEND
tRET
Parameter
Endurance
Data retention
Conditions
TA = –40 to +85 °C (6 suffix versions)
TA = –40 to +105 °C (7 suffix versions)
10
1 kcycle(2) at TA = 85 °C
30
(2)
1 kcycle
10
at TA = 105 °C
kcycles(2)
at TA = 55 °C
1. Data based on characterization results, not tested in production.
2. Cycling performed over the whole temperature range.
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Min(1)
DocID025540 Rev 4
10
20
Unit
kcycles
Years
STM32F358xC
6.3.10
Electrical characteristics
EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
•
Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
•
FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and
VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 47. They are based on the EMS levels and classes
defined in application note AN1709.
Table 47. EMS characteristics
Symbol
Parameter
Conditions
Level/
Class
VFESD
VDD = 1.8 V, LQFP100, TA = +25°C,
Voltage limits to be applied on any I/O pin to
fHCLK = 72 MHz
induce a functional disturbance
conforms to IEC 61000-4-2
2B
VEFTB
Fast transient voltage burst limits to be
applied through 100 pF on VDD and VSS
pins to induce a functional disturbance
VDD = 1.8 V, LQFP100, TA = +25°C,
fHCLK = 72 MHz
conforms to IEC 61000-4-4
4A
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
•
Corrupted program counter
•
Unexpected reset
•
Critical Data corruption (control registers...)
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Electrical characteristics
STM32F358xC
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard which specifies the test board and the pin loading.
Table 48. EMI characteristics
Symbol Parameter
SEMI
6.3.11
Monitored
frequency band
Conditions
Max vs. [fHSE/fHCLK]
Unit
8/72 MHz
0.1 to 30 MHz
VDD = 1.8 V, TA = 25 °C,
30 to 130 MHz
LQFP100 package
Peak level
compliant with IEC
130 MHz to 1GHz
61967-2
SAE EMI Level
7
16
dBµV
23
4
-
Electrical sensitivity characteristics
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the JESD22-A114/C101 standard.
Table 49. ESD absolute maximum ratings
Symbol
VESD(HBM)
Ratings
Conditions
Electrostatic discharge
TA = +25 °C, conforming
voltage (human body model) to JESD22-A114
Electrostatic discharge
VESD(CDM) voltage (charge device
model)
TA = +25 °C, conforming
to JESD22-C101
1. Data based on characterization results, not tested in production.
80/134
DocID025540 Rev 4
Class
Maximum
value(1)
2
2000
Unit
V
II
500
STM32F358xC
Electrical characteristics
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
•
A supply overvoltage is applied to each power supply pin
•
A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78A IC latch-up standard.
Table 50. Electrical sensitivities
Symbol
LU
6.3.12
Parameter
Static latch-up class
Conditions
TA = +105 °C conforming to JESD78A
Class
II level A
I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above VDD (for standard, 3 V-capable I/O pins) should be avoided during normal product
operation. However, in order to give an indication of the robustness of the microcontroller in
cases when abnormal injection accidentally happens, susceptibility tests are performed on a
sample basis during device characterization.
Functional susceptibility to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (higher
than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out
of –5 µA/+0 µA range), or other functional failure (for example reset occurrence or oscillator
frequency deviation).
The test results are given in Table 51
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Electrical characteristics
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Table 51. I/O current injection susceptibility
Functional susceptibility
Symbol
IINJ
Note:
82/134
Description
Negative
injection
Positive
injection
Injected current on BOOT0
–0
NA
Injected current on PC0, PC1, PC2, PC3, PF2, PA0,
PA1, PA2, PA3, PF4, PA4, PA5, PA6, PA7, PC4, PC5
with induced leakage current on other pins from this
group less than -50 µA
–5
-
Injected current on PB0, PB1, PE7, PE8, PE9, PE10,
PE11, PE12, PE13, PE14, PE15, PB12, PB13, PB14,
PB15, PD8, PD9, PD10, PD11, PD12, PD13, PD14 with
induced leakage current on other pins from this group
less than -50 µA
–5
-
Injected current on PC0, PC1, PC2, PC3, PF2, PA0,
PA1, PA2, PA3, PF4, PA4, PA5, PA6, PA7, PC4, PC5,
PB0, PB1, PE7, PE8, PE9, PE10, PE11, PE12, PE13,
PE14, PE15, PB12, PB13, PB14, PB15, PD8, PD9,
PD10, PD11, PD12, PD13, PD14 with induced leakage
current on other pins from this group less than 400 µA
-
+5
Injected current on NPOR pin and on any other FT and
FTf pins
–5
NA
Injected current on any other pins
–5
+5
mA
It is recommended to add a Schottky diode (pin to ground) to analog pins which may
potentially inject negative currents.
DocID025540 Rev 4
Unit
STM32F358xC
6.3.13
Electrical characteristics
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 52 are derived from tests
performed under the conditions summarized in Table 24. All I/Os are CMOS and TTL
compliant.
Table 52. I/O static characteristics
Symbol
VIL
VIH
Parameter
Low level input
voltage
High level input
voltage
Conditions
Vhys
Ilkg
Input leakage
current (3)
Typ
Max
Unit
(1)
TC and TTa I/O
-
-
0.3 VDD+0.07
FT and FTf I/O
-
-
0.475 VDD-0.2 (1)
BOOT0
-
-
0.3 VDD–0.3 (1)
All I/Os except BOOT0
-
-
0.3 VDD (2)
TC and TTa I/O
0.445 VDD+0.398 (1)
-
-
FT and FTf I/O
0.5 VDD+0.2 (1)
-
-
-
-
BOOT0
All I/Os except BOOT0
Schmitt trigger
hysteresis
Min
0.2 VDD+0.95
0.7 VDD
(2)
(1)
-
V
(1)
-
TC and TTa I/O
-
200
FT and FTf I/O
-
100 (1)
-
BOOT0
-
300
(1)
-
TC, FT, FTf and POR I/O
TTa I/O in digital mode
VSS ≤VIN ≤VDD
-
-
±0.1
TTa I/O in digital mode
VDD ≤VIN ≤VDDA
-
-
1
TTa I/O in analog mode
VSS ≤VIN ≤VDDA
-
-
±0.2
FT and FTf I/O(4)
VDD ≤VIN ≤5 V
-
-
10
POR
VDDA ≤ VIN ≤5 V
-
-
10
mV
µA
RPU
Weak pull-up
equivalent resistor(5)
VIN = VSS
25
40
55
kΩ
RPD
Weak pull-down
equivalent resistor(5)
VIN = VDD
25
40
55
kΩ
CIO
I/O pin capacitance
-
-
5
-
pF
1. Data based on design simulation.
2. Tested in production.
3. Leakage could be higher than the maximum value. if negative current is injected on adjacent pins. Refer to Table 51: I/O
current injection susceptibility.
4. To sustain a voltage higher than VDD +0.3 V, the internal pull-up/pull-down resistors must be disabled.
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Electrical characteristics
STM32F358xC
5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
PMOS/NMOS contribution to the series resistance is minimum (~10% order).
All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters.
Figure 18. TC and TTa I/O input characteristics
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STM32F358xC
Electrical characteristics
Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink or
source up to +/- 20 mA (with a relaxed VOL/VOH).
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2:
•
The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
ΣIVDD (see Table 22).
•
The sum of the currents sunk by all the I/Os on VSS plus the maximum Run
consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating
ΣIVSS (see Table 22).
Output voltage levels
Unless otherwise specified, the parameters given in Table 53 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 24. All I/Os (FT, TTa and TC unless otherwise specified) are CMOS and TTL
compliant.
Table 53. Output voltage characteristics
Symbol
Parameter
Conditions
Min
Max
VOL(1)
Output low level voltage for an I/O pin
IIO = +4 mA
1.65 V < VDD < 1.95 V
-
0.4
VOH(2)
Output high level voltage for an I/O pin
IIO = -4 mA
1.65 V < VDD < 1.95 V
VDD – 0.4
-
-
0.4
VOLFM+(1)(3)
IIO = +10 mA
Output low level voltage for an FTf I/O pin in
VDD = 1.65 V to 1.95 V
FM+ mode
Unit
V
1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 22 and the sum of
IIO (I/O ports and control pins) must not exceed ΣIIO(PIN).
2. The IIO current sourced by the device must always respect the absolute maximum rating specified in Table 22 and the sum
of IIO (I/O ports and control pins) must not exceed ΣIIO(PIN).
3. Guaranted by Design, not tested in production.
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Electrical characteristics
STM32F358xC
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 20 and
Table 54, respectively.
Unless otherwise specified, the parameters given are derived from tests performed under
ambient temperature and VDD supply voltage conditions summarized in Table 24.
Table 54. I/O AC characteristics(1)
OSPEEDRy [1:0]
value(1)
x0
01
11
FM+
configuration(4)
-
Symbol
Parameter
Conditions
Min
Max
Unit
CL = 50 pF, VDD = 1.65 V to 1.95 V
-
1
MHz
-
125(3)
-
125(3)
-
4(3)
-
62.5(3)
-
62.5(3)
fmax(IO)out
Maximum frequency(2)
tf(IO)out
Output high to low level
fall time
tr(IO)out
Output low to high level
rise time
fmax(IO)out
Maximum frequency(2)
tf(IO)out
Output high to low level
fall time
tr(IO)out
Output low to high level
rise time
fmax(IO)out
Maximum frequency(2)
CL = 50 pF, VDD = 1.65 V to 1.95 V
-
10(3)
tf(IO)out
Output high to low level
fall time
CL = 50 pF, VDD = 1.65 V to 1.95 V
-
25(3)
tr(IO)out
Output low to high level
rise time
CL = 50 pF, VDD = 1.65 V to 1.95 V
-
25(3)
fmax(IO)out
Maximum frequency(2)
tf(IO)out
Output high to low level
fall time
tr(IO)out
Output low to high level
rise time
tEXTIpw
Pulse width of external
signals detected by the
EXTI controller
CL = 50 pF, VDD = 1.65 V to 1.95 V
CL = 50 pF, VDD = 1.65 V to 1.95 V
ns
CL = 50 pF, VDD = 1.65 V to 1.95 V
ns
MHz
ns
CL = 50 pF, VDD = 1.65 V to 1.95 V
-
-
0.5(4)(3) MHz
-
16(4)(3)
-
44(4)(3)
10
-
ns
1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the RM0316 reference manual for a description of
GPIO Port configuration register.
2. The maximum frequency is defined in Figure 20.
3. Guaranteed by design, not tested in production.
4. The I/O speed configuration is bypassed in FM+ I/O mode. Refer to the RM0316 STM32F303xx, STM32F358xC and
STM32F328x4/6/8 reference manual (RM0316) for a description of FM+ I/O mode configuration.
86/134
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STM32F358xC
Electrical characteristics
Figure 20. I/O AC characteristics definition
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6.3.14
AIC
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU (see Table 52).
Unless otherwise specified, the parameters given in Table 55 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 24.
Table 55. NRST pin characteristics
Symbol
Parameter
VIL(NRST)(1) NRST Input low level voltage
Conditions
Min
Typ
Max
-
-
-
0.3VDD+
0.07(1)
-
-
Unit
V
VIH(NRST)(1)
NRST Input high level voltage
-
0.445VDD+
0.398(1)
Vhys(NRST)
NRST Schmitt trigger voltage hysteresis
-
-
200
-
mV
VIN = VSS
25
40
55
kΩ
-
100(1)
ns
-
-
ns
RPU
VF(NRST)(1)
VNF(NRST)(1)
Weak pull-up equivalent resistor(2)
NRST Input filtered pulse
NRST Input not filtered pulse
-
(1)
700
1. Guaranteed by design, not tested in production.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance must be minimum (~10% order).
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Electrical characteristics
STM32F358xC
Figure 21. Recommended NRST pin protection
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1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 55. Otherwise the reset will not be taken into account by the device.
6.3.15
NPOR pin characteristics
The NPOR pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, Rpu (see Table 56) connected to VDDA supply.
Unless otherwise specified, the parameters given in Table 56 are derived from tests
performed under ambient temperature and VDDA supply voltage conditions summarized in
Table 24.
Table 56. NPOR pin characteristics
(1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIL(NPOR)
NPOR Input low level voltage
-
-
-
0.475VDDA
- 0.2
VIH(NPOR)
NPOR Input high level voltage
-
0.5VDDA
+ 0.2
-
-
Vhys(NPOR)
NPOR Schmitt trigger voltage
hysteresis
-
-
100
-
mV
VIN = VSS
25
40
55
kΩ
RPU
Weak pull-up equivalent resistor(2)
V
1. Guaranteed by design, not tested in production.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to
the series resistance is minimal (~10% order).
6.3.16
Timer characteristics
The parameters given in Table 57 are guaranteed by design.
Refer to Section 6.3.13: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
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Electrical characteristics
Table 57. TIMx(1)(2) characteristics
Symbol
tres(TIM)
fEXT
ResTIM
tCOUNTER
tMAX_COUNT
Parameter
Timer resolution time
Timer external clock
frequency on CH1 to CH4
Timer resolution
16-bit counter clock period
Maximum possible count
with 32-bit counter
Conditions
Min
Max
Unit
-
1
-
tTIMxCLK
fTIMxCLK = 72 MHz
13.9
-
ns
fTIMxCLK = 144 MHz,
x= 1.8
6.95
-
ns
-
0
fTIMxCLK/2
MHz
fTIMxCLK = 72 MHz
0
36
MHz
TIMx (except TIM2)
-
16
TIM2
-
32
-
1
65536
tTIMxCLK
fTIMxCLK = 72 MHz
0.0139
910
µs
fTIMxCLK = 144 MHz,
x= 1.8
0.0069
455
µs
-
-
65536 × 65536
tTIMxCLK
fTIMxCLK = 72 MHz
-
59.65
s
fTIMxCLK = 144 MHz,
x= 1.8
-
29.825
s
bit
1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3, TIM4, TIM6, TIM15, TIM16 and TIM17
timers.
2. Guaranteed by design, not tested in production.
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Electrical characteristics
STM32F358xC
Table 58. IWDG min/max timeout period at 40 kHz (LSI) (1)
Prescaler divider
PR[2:0] bits
Min timeout (ms) RL[11:0]=
0x000
Max timeout (ms) RL[11:0]=
0xFFF
/4
0
0.1
409.6
/8
1
0.2
819.2
/16
2
0.4
1638.4
/32
3
0.8
3276.8
/64
4
1.6
6553.6
/128
5
3.2
13107.2
/256
7
6.4
26214.4
1. These timings are given for a 40 kHz clock but the microcontroller’s internal RC frequency can vary from 30
to 60 kHz. Moreover, given an exact RC oscillator frequency, the exact timings still depend on the phasing
of the APB interface clock versus the LSI clock so that there is always a full RC period of uncertainty.
Table 59. WWDG min-max timeout value @72 MHz (PCLK)(1)
Prescaler
WDGTB
Min timeout value
Max timeout value
1
0
0.05687
3.6409
2
1
0.1137
7.2817
4
2
0.2275
14.564
8
3
0.4551
29.127
1. Guaranteed by design, not tested in production.
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6.3.17
Electrical characteristics
Communications interfaces
I2C interface characteristics
The I2C interface meets the requirements of the standard I2C communication protocol with
the following restrictions: the I/O pins SDA and SCL are mapped to are not “true” opendrain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is
disabled, but is still present.
The I2C characteristics are described in Table 60. Refer also to Section 6.3.13: I/O port
characteristics for more details on the input/output alternate function characteristics (SDA
and SCL).
Table 60. I2C timings specification (see I2C specification, rev.03, June 2007)(1)
Standard mode
Symbol
Fast mode
Fast Mode Plus
Parameter
Unit
Min
Max
Min
Max
Min
Max
0
100
0
400
0
1000
KHz
-
1.3
-
0.5
-
µs
0.26
-
µs
fSCL
SCL clock frequency
tLOW
Low period of the SCL clock
4.7
tHIGH
High Period of the SCL clock
4
tr
Rise time of both SDA and SCL
signals
-
1000
-
300
-
120
ns
tf
Fall time of both SDA and SCL
signals
-
300
-
300
-
120
ns
Data hold time
0
-
0
-
0
-
µs
-
3.45(2)
-
0.9(2)
-
0.45(2)
µs
-
3.45(2)
-
0.9(2)
-
0.45(2)
µs
tHD;DAT
tVD;DAT
Data valid time
0.6
tVD;ACK
Data valid acknowledge time
tSU;DAT
Data setup time
250
-
100
-
50
-
ns
tHD:STA
Hold time (repeated) START
condition
4.0
-
0.6
-
0.26
-
µs
tSU:STA
Set-up time for a repeated START
condition
4.7
-
0.6
-
0.26
tSU:STO
Set-up time for STOP condition
4.0
-
0.6
-
0.26
-
µs
Bus free time between a
STOP and START condition
4.7
-
1.3
-
0.5
-
µs
-
400
-
400
-
550
pF
tBUF
Cb
Capacitive load for each bus line
µs
1. The I2C characteristics are the requirements from I2C bus specification rev03. They are guaranteed by design when
I2Cx_TIMING register is correctly programmed (Refer to the reference manual). These characteristics are not tested in
production.
2. The maximum tHD;DAT could be 3.45 µs, 0.9 µs and 0.45 µs for standard mode, fast mode and fast mode plus, but must
be less than the maximum of tVD;DAT or tVD;ACK by a transition time.
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Electrical characteristics
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Table 61. I2C analog filter characteristics(1)
Symbol
Parameter
Min
Max
Unit
50
260
ns
Pulse width of spikes that are
suppressed by the analog filter
tSP
1. Guaranteed by design, not tested in production.
Figure 22. I2C bus AC waveforms and measurement circuit
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1. Rs: Series protection resistors, Rp: Pull-up resistors, VDD_I2C: I2C bus supply.
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Electrical characteristics
SPI/I2S characteristics
Unless otherwise specified, the parameters given in Table 62 for SPI or in Table 63 for I2S
are derived from tests performed under ambient temperature, fPCLKx frequency and VDD
supply voltage conditions summarized in Table 24.
Refer to Section 6.3.13: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I2S).
Table 62. SPI characteristics(1)
Symbol
Parameter
Conditions
Min
Typ
Master mode,SPI1/2/3
fSCK
1/tc(SCK)
SPI clock frequency
Duty(SCK)
SPI slave input clock
duty cycle
Slave mode
tsu(NSS)
NSS setup time
th(NSS)
tw(SCKH)
tw(SCKL)
tsu(MI)
tsu(SI)
th(MI)
th(SI)
Slave mode,SPI1/2/3
Max
18
-
-
Slave mode transmitter/full
duplex SPI1/2/3
18
50
70
Slave mode, SPI presc = 2
4*Tpclk
-
-
NSS hold time
Slave mode SPI presc = 2
2*Tpclk
-
-
SCK high and low time
Master mode, fPCLK = 36 MHz,
presc = 4
Tpclk-2
Tpclk
Tpclk+2
Master mode
5.5
-
-
Slave mode
6.5
-
-
Master mode
5
-
-
Slave mode
5
-
-
Data input hold time
ta(SO)
Data output access time Slave mode, fPCLK = 24 MHz
0
-
4*Tpclk
tdis(SO)
Data output disable time Slave mode
0
-
24
tv(SO)
Data output valid time
Slave mode (after enable edge)
-
25
39
tv(MO)
Data output valid time
Master mode (after enable edge)
-
1.5
3
Slave mode (after enable edge)
11
-
-
Master mode (after enable edge)
0
-
-
th(SO)
th(MO)
Data output hold time
MHz
12.5(2)
30
Data input setup time
Unit
%
ns
1. Data based on characterization results, not tested in production.
2. Maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit into SCK
low or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a
master having tsu(MI) = 0 while Duty(SCK) = 50%.
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Figure 23. SPI timing diagram - slave mode and CPHA = 0
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Figure 24. SPI timing diagram - slave mode and CPHA = 1(1)
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DL
1. Measurement points are done at 0.5VDD and with external CL = 30 pF.
94/134
DocID025540 Rev 4
STM32F358xC
Electrical characteristics
Figure 25. SPI timing diagram - master mode(1)
(IGH
.33INPUT
3#+/UTPUT
#0(! #0/,
3#+/UTPUT
TC3#+
#0(!
#0/,
#0(! #0/,
#0(!
#0/,
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TW3#+,
TSU-)
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") 4).
,3").
TH-)
-/3)
/54054
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- 3"/54
TV-/
,3"/54
TH-/
AI6
1. Measurement points are done at 0.5VDD and with external CL = 30 pF.
Table 63. I2S characteristics(1)
Symbol
Parameter
Conditions
Min
Max
fCK
1/tc(CK)
I2S clock frequency
Master data: 16 bits,
audio freq=48 kHz
1.496
1.503
Slave
0
12.288
-
8
2
tr(CK)
tf(CK)
I S clock rise and fall
time
Capacitive load
CL = 30 pF
tw(CKH)
I2S clock high time
331
-
tw(CKL)
I2S clock low time
Master fPCLK= 36 MHz,
audio frequency =
48 kHz
332
-
tv(WS)
WS valid time
Master mode
4
-
th(WS)
WS hold time
Master mode
4
-
tsu(WS)
WS setup time
Slave mode
4
-
th(WS)
WS hold time
Slave mode
0
-
Duty Cycle
I2S slave input clock
duty cycle
Slave mode
30
70
DocID025540 Rev 4
Unit
MHz
ns
%
95/134
118
Electrical characteristics
STM32F358xC
Table 63. I2S characteristics(1) (continued)
Symbol
Parameter
Conditions
Min
Max
tsu(SD_MR)
Data input setup time
Master receiver
9
-
tsu(SD_SR)
Data input setup time
Slave receiver
2
-
Master receiver
0
-
Slave receiver
0
-
Data output valid time
Slave transmitter
(after enable edge)
-
29
th(SD_ST)
Data output hold time
Slave transmitter
(after enable edge)
12
-
tv(SD_MT)
Data output valid time
Master transmitter
(after enable edge)
-
3
th(SD_MT)
Data output hold time
Master transmitter
(after enable edge)
2
-
th(SD_MR)
th(SD_SR)
tv(SD_ST)
Data input hold time
Unit
ns
1. Data based on characterization results, not tested in production.
Figure 26. I2S slave timing diagram (Philips protocol)(1)
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DLE
1. Measurement points are done at 0.5VDD and with external CL=30 pF.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
96/134
DocID025540 Rev 4
STM32F358xC
Electrical characteristics
Figure 27. I2S master timing diagram (Philips protocol)(1)
TF#+
TR#+
#+OUTPUT
TC#+
#0/,
TW#+(
#0/,
TV73
TH73
TW#+,
73OUTPUT
TV3$?-4
3$TRANSMIT
,3"TRANSMIT
-3"TRANSMIT
,3"RECEIVE
,3"TRANSMIT
TH3$?-2
TSU3$?-2
3$RECEIVE
"ITNTRANSMIT
TH3$?-4
-3"RECEIVE
"ITNRECEIVE
,3"RECEIVE
AIB
1. Measurement points are done at 0.5VDD and with external CL=30 pF.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
CAN (controller area network) interface
Refer to Section 6.3.13: I/O port characteristics for more details on the input/output alternate
function characteristics (CAN_TX and CAN_RX).
DocID025540 Rev 4
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118
Electrical characteristics
6.3.18
STM32F358xC
ADC characteristics
Unless otherwise specified, the parameters given in Table 64 to Table 67 are guaranteed by
design, with conditions summarized in Table 24.
Table 64. ADC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDDA
Analog supply voltage for
ADC
-
1.8
-
3.6
V
Single-ended mode,
5 MSPS
-
907
1033.0
Single-ended mode,
1 MSPS
-
194
285.5
Single-ended mode,
200 KSPS
-
51.5
70
Differential mode,
5 MSPS
-
887.
5
1009
Differential mode,
1 MSPS
-
212
285
Differential mode,
200 KSPS
-
51
69.5
-
2
-
VDDA
Single-ended mode,
5 MSPS
-
104
139
Single-ended mode,
1 MSPS
-
20.4
37
Single-ended mode,
200 KSPS
-
3.3
11.3
Differential mode,
5 MSPS
-
174
235
Differential mode,
1 MSPS
-
34.6
52.6
Differential mode,
200 KSPS
-
6
13.6
0.14
-
72
Resolution = 12 bits,
Fast Channel
0.01
-
5.14
Resolution = 10 bits,
Fast Channel
0.012
-
6
Resolution = 8 bits,
Fast Channel
0.014
-
7.2
Resolution = 6 bits,
Fast Channel
0.0175
-
9
IDDA
VREF+
IREF
fADC
fS(1)
98/134
ADC current
consumption on VDDA
pin
(see Figure 28)
Positive reference
voltage
ADC current
consumption on VREF+
pin
(see Figure 29)
ADC clock frequency
Sampling rate
DocID025540 Rev 4
µA
V
µA
MHz
MSPS
STM32F358xC
Electrical characteristics
Table 64. ADC characteristics (continued)
Symbol
Conditions
Min
Typ
Max
Unit
fADC = 72 MHz
Resolution = 12 bits
-
-
5.14
MHz
Resolution = 12 bits
-
-
14
1/fADC
Conversion voltage
range(2)
-
0
-
VREF+
V
RAIN(1)
External input
impedance
-
-
-
100
kΩ
CADC(1)
Internal sample and hold
capacitor
-
-
5
-
pF
tCAL(1)
Calibration time
CKMODE = 00
1.5
2
2.5
1/fADC
tlatr(1)
Trigger conversion
latency
Regular and injected
channels without
conversion abort
CKMODE = 01
-
-
2
1/fADC
CKMODE = 10
-
-
2.25
1/fADC
CKMODE = 11
-
-
2.125
1/fADC
Trigger conversion
latency
Injected channels
aborting a regular
conversion
CKMODE = 00
2.5
3
3.5
1/fADC
CKMODE = 01
-
-
3
1/fADC
CKMODE = 10
-
-
3.25
1/fADC
CKMODE = 11
-
-
3.125
1/fADC
fADC = 72 MHz
0.021
-
8.35
µs
-
1.5
-
601.5
1/fADC
-
-
-
10
µs
fADC = 72 MHz
Resolution = 12 bits
0.19
-
8.52
µs
fTRIG(1)
VAIN
tlatrinj(1)
tS(1)
TADCVRE
(1
G_STUP
)
Parameter
External trigger
frequency
Sampling time
ADC Voltage Regulator
Start-up time
Total conversion time
tCONV(1)
(including sampling time)
fADC = 72 MHz
1.56
µs
-
112
1/fADC
Resolution = 12 bits
14 to 614 (tS for sampling +
12.5 for
successive approximation)
1/fADC
1. Data guaranteed by design, not tested in production.
2. VREF+ can be internally connected to VDDA and VREF- can be internally connected to VSSA, depending on
the package. Refer to Section 4: Pinouts and pin description for further details.
DocID025540 Rev 4
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118
Electrical characteristics
STM32F358xC
Figure 28. ADC typical current consumption on VDDA pin
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6LQJOHHQGHGPRGH
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069
Figure 29. ADC typical current consumption on VREF+ pin
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069
100/134
DocID025540 Rev 4
STM32F358xC
Electrical characteristics
Table 65. Maximum ADC RAIN (1)
Resolution
12 bits
10 bits
8 bits
6 bits
RAIN max (kΩ)
Sampling
cycle @
72 MHz
Sampling
time [ns] @
72 MHz
Fast channels(2)
Slow
channels
Other
channels(3)
1.5
20.83
0.018
NA
NA
2.5
34.72
0.150
NA
0.022
4.5
62.50
0.470
0.220
0.180
7.5
104.17
0.820
0.560
0.470
19.5
270.83
2.70
1.80
1.50
61.5
854.17
8.20
6.80
4.70
181.5
2520.83
22.0
18.0
15.0
601.5
8354.17
82.0
68.0
47.0
1.5
20.83
0.082
NA
NA
2.5
34.72
0.270
0.082
0.100
4.5
62.50
0.560
0.390
0.330
7.5
104.17
1.20
0.82
0.68
19.5
270.83
3.30
2.70
2.20
61.5
854.17
10.0
8.2
6.8
181.5
2520.83
33.0
27.0
22.0
601.5
8354.17
100.0
82.0
68.0
1.5
20.83
0.150
NA
0.039
2.5
34.72
0.390
0.180
0.180
4.5
62.50
0.820
0.560
0.470
7.5
104.17
1.50
1.20
1.00
19.5
270.83
3.90
3.30
2.70
61.5
854.17
12.00
12.00
8.20
181.5
2520.83
39.00
33.00
27.00
601.5
8354.17
100.00
100.00
82.00
1.5
20.83
0.270
0.100
0.150
2.5
34.72
0.560
0.390
0.330
4.5
62.50
1.200
0.820
0.820
7.5
104.17
2.20
1.80
1.50
19.5
270.83
5.60
4.70
3.90
61.5
854.17
18.0
15.0
12.0
181.5
2520.83
56.0
47.0
39.0
601.5
8354.17
100.00
100.0
100.0
1. Data based on characterization results, not tested in production.
2. All fast channels, expect channels on PA2, PA6, PB1, PB12.
DocID025540 Rev 4
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118
Electrical characteristics
STM32F358xC
3. Channels available on PA2, PA6, PB1 and PB12.
Table 66. ADC accuracy - limited test conditions 100-pin packages(1)(2)
Symbol Parameter
ET
Single ended
Total
unadjusted
error
Differential
Single ended
EO
Offset error
Differential
Single ended
EG
Gain error
Differential
ED
EL
ENOB
SINAD
102/134
Differential
linearity
error
Integral
linearity
error
Effective
number of
bits
Signal-tonoise and
distortion
ratio
Min
Conditions
ADC clock freq. ≤ 72 MHz
Sampling freq. ≤ 5 Msps
VDDA = VREF+ = 3.3 V
25°C
100-pin package
Single ended
Differential
Single ended
Differential
Single ended
Differential
Single ended
Differential
DocID025540 Rev 4
(3)
Typ
Max
(3)
Unit
±3.5 ±4.5
Fast channel 5.1 Ms
-
Slow channel 4.8 Ms
-
±4
±4.5
Fast channel 5.1 Ms
-
±3
±3
Slow channel 4.8 Ms
-
±3
±3
Fast channel 5.1 Ms
-
±1
±1.5
Slow channel 4.8 Ms
-
±1
±2.5
Fast channel 5.1 Ms
-
±1
±1.5
Slow channel 4.8 Ms
-
±1
±1.5
Fast channel 5.1 Ms
-
±3
±4
Slow channel 4.8 Ms
-
±3.5
±4
Fast channel 5.1 Ms
-
±1.5 ±2.5
Slow channel 4.8 Ms
-
±2
±2.5
Fast channel 5.1 Ms
-
±1
±1.5
Slow channel 4.8 Ms
-
±1
±1.5
Fast channel 5.1 Ms
-
±1
±1
Slow channel 4.8 Ms
-
±1
±1
Fast channel 5.1 Ms
-
±1.5
±2
Slow channel 4.8 Ms
-
±1.5
±3
Fast channel 5.1 Ms
-
±1
±1.5
Slow channel 4.8 Ms
-
±1
±1.5
Fast channel 5.1 Ms
10.7 10.8
-
Slow channel 4.8 Ms
10.7 10.8
-
Fast channel 5.1 Ms
11.2 11.3
-
Slow channel 4.8 Ms
11.1 11.3
-
Fast channel 5.1 Ms
66
67
-
Slow channel 4.8 Ms
66
67
-
Fast channel 5.1 Ms
69
70
-
Slow channel 4.8 Ms
69
70
-
LSB
bits
dB
STM32F358xC
Electrical characteristics
Table 66. ADC accuracy - limited test conditions 100-pin packages(1)(2) (continued)
Symbol Parameter
Single ended
SNR
THD
Signal-tonoise ratio
Total
harmonic
distortion
Min
Conditions
ADC clock freq. ≤ 72 MHz
Sampling freq ≤ 5 Msps
VDDA = VREF+ = 3.3 V
25°C
100-pin package
Differential
Single ended
Differential
Max
(3)
Typ
Fast channel 5.1 Ms
66
67
-
Slow channel 4.8 Ms
66
67
-
Fast channel 5.1 Ms
69
70
-
Slow channel 4.8 Ms
69
70
-
Fast channel 5.1 Ms
-
-76
-76
Slow channel 4.8 Ms
-
-76
-76
Fast channel 5.1 Ms
-
-80
-80
Slow channel 4.8 Ms
-
-80
-80
(3)
Unit
dB
1. ADC DC accuracy values are measured after internal calibration.
2. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this
significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a
Schottky diode (pin to ground) to analog pins which may potentially inject negative current.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 6.3.13 does not affect the ADC
accuracy.
3. Data based on characterization results, not tested in production.
DocID025540 Rev 4
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118
Electrical characteristics
STM32F358xC
Table 67. ADC accuracy, 100-pin packages(1)(2)(3)
Symbol Parameter
ET
Total
unadjusted
error
Single Ended
Differential
Single Ended
EO
Offset error
Differential
Single Ended
EG
ED
EL
ENOB
104/134
Gain error
Differential
linearity
error
Integral
linearity
error
Effective
number of
bits
Min(4) Max(4) Unit
Conditions
ADC clock freq. ≤ 72 MHz,
Differential
Sampling freq. ≤ 5 Msps
1.8V ≤ VDDA , VREF+ ≤ 3.6 V
Single Ended
100-pin package
Differential
Single Ended
Differential
Single Ended
Differential
DocID025540 Rev 4
Fast channel 5.1 Ms
-
±6.5
Slow channel 4.8 Ms
-
±6.5
Fast channel 5.1 Ms
-
±4
Slow channel 4.8 Ms
-
±4
Fast channel 5.1 Ms
-
±3
Slow channel 4.8 Ms
-
±3
Fast channel 5.1 Ms
-
±2
Slow channel 4.8 Ms
-
±2
Fast channel 5.1 Ms
-
±6
Slow channel 4.8 Ms
-
±6
Fast channel 5.1 Ms
-
±3
Slow channel 4.8 Ms
-
±3
Fast channel 5.1 Ms
-
±1.5
Slow channel 4.8 Ms
-
±1.5
Fast channel 5.1 Ms
-
±1.5
Slow channel 4.8 Ms
-
±1.5
Fast channel 5.1 Ms
-
±2
Slow channel 4.8 Ms
-
±3
Fast channel 5.1 Ms
-
±2
Slow channel 4.8 Ms
-
±2
Fast channel 5.1 Ms
10.4
-
Slow channel 4.8 Ms
10.2
-
Fast channel 5.1 Ms
10.8
-
Slow channel 4.8 Ms
10.8
-
LSB
bits
STM32F358xC
Electrical characteristics
Table 67. ADC accuracy, 100-pin packages(1)(2)(3) (continued)
Symbol Parameter
Signal-tonoise and
SINAD
distortion
ratio
SNR
THD
Signal-tonoise ratio
Total
harmonic
distortion
Min(4) Max(4) Unit
Conditions
Single Ended
Differential
ADC clock freq. ≤ 72 MHz, Single Ended
Sampling freq. ≤ 5 Msps,
1.8V ≤ VDDA, VREF+ ≤ 3.6 V
Differential
100-pin package
Single Ended
Differential
Fast channel 5.1 Ms
-
64
Slow channel 4.8 Ms
-
63
Fast channel 5.1 Ms
-
67
Slow channel 4.8 Ms
-
67
Fast channel 5.1 Ms
64
-
Slow channel 4.8 Ms
64
-
Fast channel 5.1 Ms
67
-
Slow channel 4.8 Ms
67
-
Fast channel 5.1 Ms
-
-74
Slow channel 4.8 Ms
-
-74
Fast channel 5.1 Ms
-
-78
Slow channel 4.8 Ms
-
-76
dB
1. ADC DC accuracy values are measured after internal calibration.
2. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this
significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a
Schottky diode (pin to ground) to analog pins which may potentially inject negative current.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 6.3.13 does not affect the ADC
accuracy.
3. Better performance may be achieved in restricted VDDA, frequency and temperature ranges.
4. Data based on characterization results, not tested in production.
DocID025540 Rev 4
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118
Electrical characteristics
STM32F358xC
Table 68. ADC accuracy - limited test conditions 64-pin packages(1)(2)
Symbol
ET
Parameter
Single ended
Total
unadjusted
error
Differential
Single ended
EO
Offset error
Differential
Single ended
EG
Gain error
Differential
ED
EL
Differential
linearity
error
Integral
linearity
error
Effective
ENOB(4) number of
bits
Signal-tonoise and
SINAD(4)
distortion
ratio
106/134
Min
Conditions
ADC clock freq. ≤ 72 MHz
Sampling freq. ≤ 5 Msps
VDDA = VREF+ = 3.3 V
25°C
64-pin package
Single ended
Differential
Single ended
Differential
Single ended
Differential
Single ended
Differential
DocID025540 Rev 4
(3)
Typ
Max
(3)
Fast channel 5.1 Ms
-
±4.0 ±4.5
Slow channel 4.8 Ms
-
±5.5 ±6.0
Fast channel 5.1 Ms
-
±3.5 ±4.0
Slow channel 4.8 Ms
-
±3.5 ±4.0
Fast channel 5.1 Ms
-
±2.0 ±2.0
Slow channel 4.8 Ms
-
±1.5 ±2.0
Fast channel 5.1 Ms
-
±1.5 ±2.0
Slow channel 4.8 Ms
-
±1.5 ±2.0
Fast channel 5.1 Ms
-
±3.0 ±4.0
Slow channel 4.8 Ms
-
±5.0 ±5.5
Fast channel 5.1 Ms
-
±3.0 ±3.0
Slow channel 4.8 Ms
-
±3.0 ±3.0
Fast channel 5.1 Ms
-
±1.0 ±1.0
Slow channel 4.8 Ms
-
±1.0 ±1.0
Fast channel 5.1 Ms
-
±1.0 ±1.0
Slow channel 4.8 Ms
-
±1.0 ±1.0
Fast channel 5.1 Ms
-
±1.5 ±2.0
Slow channel 4.8 Ms
-
±2.0 ±3.0
Fast channel 5.1 Ms
-
±1.5 ±1.5
Slow channel 4.8 Ms
-
±1.5 ±2.0
Fast channel 5.1 Ms
10.8 10.8
-
Slow channel 4.8 Ms
10.8 10.8
-
Fast channel 5.1 Ms
11.2 11.3
-
Slow channel 4.8 Ms
11.2 11.3
-
Fast channel 5.1 Ms
66
67
-
Slow channel 4.8 Ms
66
67
-
Fast channel 5.1 Ms
69
70
-
Slow channel 4.8 Ms
69
70
-
Unit
LSB
bits
dB
STM32F358xC
Electrical characteristics
Table 68. ADC accuracy - limited test conditions 64-pin packages(1)(2) (continued)
Symbol
Parameter
Single ended
SNR(4)
THD(4)
Signal-tonoise ratio
Total
harmonic
distortion
Min
Conditions
ADC clock freq. ≤ 72 MHz
Differential
Sampling freq ≤ 5 Msps
VDDA = VREF+ = 3.3 V
25°C
Single ended
100-pin package
Differential
Max
(3)
Typ
Fast channel 5.1 Ms
66
67
-
Slow channel 4.8 Ms
66
67
-
Fast channel 5.1 Ms
69
70
-
Slow channel 4.8 Ms
69
70
-
Fast channel 5.1 Ms
-
-80
-80
Slow channel 4.8 Ms
-
-78
-77
Fast channel 5.1 Ms
-
-83
-82
Slow channel 4.8 Ms
-
-81
-80
(3)
Unit
dB
1. ADC DC accuracy values are measured after internal calibration.
2. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this
significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a
Schottky diode (pin to ground) to analog pins which may potentially inject negative current.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 6.3.13 does not affect the ADC
accuracy.
3. Data based on characterization results, not tested in production.
4. Value measured with a –0.5dB Full Scale 50kHz sine wave input signal.
DocID025540 Rev 4
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118
Electrical characteristics
STM32F358xC
Table 69. ADC accuracy, 64-pin packages(1)(2)(3)
Symbol Parameter
ET
Total
unadjusted
error
Single Ended
Differential
Single Ended
EO
Offset error
Differential
Single Ended
EG
ED
EL
ENOB
108/134
Gain error
Differential
linearity
error
Integral
linearity
error
Effective
number of
bits
Min(4) Max(4) Unit
Conditions
ADC clock freq. ≤ 72 MHz,
Differential
Sampling freq. ≤ 5 Msps
1.8V ≤ VDDA , VREF+ ≤ 3.6 V
Single Ended
64-pin package
Differential
Single Ended
Differential
Single Ended
Differential
DocID025540 Rev 4
Fast channel 5.1 Ms
-
±6.5
Slow channel 4.8 Ms
-
±6.5
Fast channel 5.1 Ms
-
±4
Slow channel 4.8 Ms
-
±4.5
Fast channel 5.1 Ms
-
±3
Slow channel 4.8 Ms
-
±3
Fast channel 5.1 Ms
-
±2.5
Slow channel 4.8 Ms
-
±2.5
Fast channel 5.1 Ms
-
±6
Slow channel 4.8 Ms
-
±6
Fast channel 5.1 Ms
-
±3.5
Slow channel 4.8 Ms
-
±4
Fast channel 5.1 Ms
-
±1.5
Slow channel 4.8 Ms
-
±1.5
Fast channel 5.1 Ms
-
±1.5
Slow channel 4.8 Ms
-
±1.5
Fast channel 5.1 Ms
-
±3
Slow channel 4.8 Ms
-
±3.5
Fast channel 5.1 Ms
-
±2
Slow channel 4.8 Ms
-
±2.5
Fast channel 5.1 Ms
10.4
-
Slow channel 4.8 Ms
10.4
-
Fast channel 5.1 Ms
10.8
-
Slow channel 4.8 Ms
10.8
-
LSB
bits
STM32F358xC
Electrical characteristics
Table 69. ADC accuracy, 64-pin packages(1)(2)(3) (continued)
Symbol Parameter
Single Ended
Signal-tonoise and
SINAD
distortion
ratio
SNR
THD
Signal-tonoise ratio
Min(4) Max(4) Unit
Conditions
Differential
ADC clock freq. ≤ 72 MHz, Single Ended
Sampling freq. ≤ 5 Msps,
1.8V ≤ VDDA, VREF+ ≤ 3.6 V
Differential
64-pin package
Single Ended
Total
harmonic
distortion
Differential
Fast channel 5.1 Ms
64
-
Slow channel 4.8 Ms
63
-
Fast channel 5.1 Ms
67
-
Slow channel 4.8 Ms
67
-
Fast channel 5.1 Ms
64
-
Slow channel 4.8 Ms
64
-
Fast channel 5.1 Ms
67
-
Slow channel 4.8 Ms
67
-
Fast channel 5.1 Ms
-
-75
Slow channel 4.8 Ms
-
-75
Fast channel 5.1 Ms
-
-79
Slow channel 4.8 Ms
-
-78
dB
1. ADC DC accuracy values are measured after internal calibration.
2. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this
significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a
Schottky diode (pin to ground) to analog pins which may potentially inject negative current.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 6.3.13 does not affect the ADC
accuracy.
3. Better performance may be achieved in restricted VDDA, frequency and temperature ranges.
4. Data based on characterization results, not tested in production.
Table 70. ADC accuracy at 1MSPS(1)(2)
Symbol
Parameter
ET
Total unadjusted error
EO
Offset error
EG
Gain error
ED
Differential linearity error
EL
Integral linearity error
Conditions
ADC clock freq. ≤ 72 MHz,
Sampling freq. ≤ 1 Msps
2.4V ≤ VDDA , VREF+ ≤ 3.6 V
single-ended mode
Typ
Max(3) Unit
Fast channel
±2.5
±5
Slow channel
±3.5
±5
Fast channel
±1
±2.5
Slow channel
±1.5
±2.5
Fast channel
±2
±3
Slow channel
±3
±4
Fast channel
±0.7
±2
Slow channel
±0.7
±2
Fast channel
±1
±3
Slow channel
±1.2
±3
LSB
1. ADC DC accuracy values are measured after internal calibration.
2. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this
significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a
Schottky diode (pin to ground) to analog pins which may potentially inject negative current.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 6.3.13 does not affect the ADC
accuracy.
3. Data based on characterization results, not tested in production.
DocID025540 Rev 4
109/134
118
Electrical characteristics
STM32F358xC
Figure 30. ADC accuracy characteristics
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1. Refer to Table 64 for the values of RAIN.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy
this, fADC should be reduced.
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 10. The 10 nF capacitor
should be ceramic (good quality) and it should be placed as close as possible to the chip.
110/134
DocID025540 Rev 4
STM32F358xC
6.3.19
Electrical characteristics
DAC electrical specifications
Table 71. DAC characteristics
Symbol
VDDA
Parameter
Analog supply voltage for
DAC ON
RLOAD(1) Resistive load with buffer ON
RO(1)
Impedance output with buffer
OFF
CLOAD(1) Capacitive load
Min
Typ
Max
Unit
Comments
2.4
-
3.6
V
-
5
-
-
kΩ
-
-
-
15
When the buffer is OFF, the Minimum
resistive load between DAC_OUT
kΩ
and VSS to have a 1% accuracy is
1.5 MΩ
-
-
50
Maximum capacitive load at
pF DAC_OUT pin (when the buffer is
ON).
It gives the maximum output
excursion of the DAC.
It corresponds to 12-bit input code
(0x0E0) to (0xF1C) at VDDA = 3.6 V
and (0x155) and (0xEAB) at VDDA =
2.4 V
DAC_OUT Lower DAC_OUT voltage
min(1)
with buffer ON
0.2
-
-
V
DAC_OUT Higher DAC_OUT voltage
max(1) with buffer ON
-
-
VDDA – 0.2
V
DAC_OUT Lower DAC_OUT voltage
min(1)
with buffer OFF
-
0.5
-
mV
DAC_OUT Higher DAC_OUT voltage
max(1) with buffer OFF
-
-
VDDA – 1LSB
V
DAC DC current
consumption in quiescent
mode (2)
-
-
380
µA
With no load, middle code (0x800) on
the input
-
-
480
µA
With no load, worst code (0xF1C) on
the input
Differential non linearity
Difference between two
consecutive code-1LSB)
-
-
±0.5
LSB Given for a 10-bit input code
-
-
±2
LSB Given for a 12-bit input code
-
-
±1
LSB Given for a 10-bit input code
INL(3)
Integral non linearity
(difference between
measured value at Code i
and the value at Code i on a
line drawn between Code 0
and last Code 1023)
-
-
±4
LSB Given for a 12-bit input code
-
-
±10
mV
Offset(3)
Offset error
(difference between
measured value at Code
(0x800) and the ideal value =
VDDA/2)
-
-
±3
LSB
Given for a 10-bit input code at
VDDA= 3.6 V
-
-
±12
LSB
Given for a 12-bit input code at
VDDA= 3.6 V
Gain error
-
-
±0.5
%
IDDA(3)
DNL(3)
Gain
error(3)
DocID025540 Rev 4
It gives the maximum output
excursion of the DAC.
-
Given for a 12-bit input code
111/134
118
Electrical characteristics
STM32F358xC
Table 71. DAC characteristics (continued)
Symbol
Min
Typ
Max
Settling time (full scale: for a
10-bit input code transition
between the lowest and the
(3)
tSETTLING
highest input codes when
DAC_OUT reaches final
value ±1LSB
-
3
4
µs CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ
Max frequency for a correct
DAC_OUT change when
small variation in the input
code (from code i to i+1LSB)
-
-
1
MS/s CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ
Wakeup time from off state
tWAKEUP(3) (Setting the ENx bit in the
DAC Control register)
-
6.5
10
CLOAD ≤ 50 pF, RLOAD ≥ 5 kΩ
µs input code between lowest and
highest possible ones.
Power supply rejection ratio
PSRR+ (1) (to VDDA) (static DC
measurement
-
–67
–40
dB No RLOAD, CLOAD = 50 pF
Update
rate(3)
Parameter
Unit
Comments
1. Guaranteed by design, not tested in production.
2. Quiescent mode refers to the state of the DAC a keeping steady value on the output, so no dynamic consumption is
involved.
3. Data based on characterization results, not tested in production.
Figure 32. 12-bit buffered /non-buffered DAC
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1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly
without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the
DAC_CR register.
112/134
DocID025540 Rev 4
STM32F358xC
6.3.20
Electrical characteristics
Comparator characteristics
Table 72. Comparator characteristics(1)
Symbol
VDDA
Parameter
Analog supply voltage
Conditions
VREFINT scaler not in use
VREFINT scaler in use
Min
Typ
Max
1.65
-
3.6
2
-
3.6
Unit
V
VIN
Comparator input voltage
range
-
0
-
VDDA
VBG
Scaler input voltage
-
-
1.2
-
VSC
Scaler offset voltage
-
-
±5
±10
mV
tS_SC
VREFINT scaler startup
time from power down
First VREFINT scaler activation after device
power on
-
-
1(2)
s
Next activations
-
-
0.2
ms
Startup time to reach propagation delay
specification
-
-
60
µs
Ultra-low-power mode
-
2
4.5
-
0.7
1.5
-
0.3
0.6
-
50
100
-
100
240
Ultra-low-power mode
-
2
7
Low-power mode
-
0.7
2.1
Medium power mode
-
0.3
1.2
-
90
180
-
110
300
tSTART
Comparator startup time
Low-power mode
Propagation delay for
200 mV step with 100 mV Medium power mode
overdrive
VDDA ≥ 2.7 V
High speed mode
tD
Propagation delay for full
range step with 100 mV
overdrive
VDDA < 2.7 V
VDDA ≥ 2.7 V
High speed mode
VDDA < 2.7 V
µs
ns
µs
ns
Voffset
Comparator offset error
-
-
±4
±10
mV
dVoffset/dT
Offset error temperature
coefficient
-
-
18
-
µV/°
C
Ultra-low-power mode
-
1.2
1.5
Low-power mode
-
3
5
Medium power mode
-
10
15
High speed mode
-
75
100
IDD(COMP)
COMP current
consumption
DocID025540 Rev 4
µA
113/134
118
Electrical characteristics
STM32F358xC
Table 72. Comparator characteristics(1) (continued)
Symbol
Parameter
Conditions
No hysteresis
(COMPxHYST[1:0]=00)
Vhys
Comparator hysteresis
Min
Typ
Max
-
0
-
High speed mode
Low hysteresis
(COMPxHYST[1:0]=01) All other power
modes
3
High speed mode
Medium hysteresis
(COMPxHYST[1:0]=10) All other power
modes
7
High speed mode
High hysteresis
(COMPxHYST[1:0]=11) All other power
modes
18
5
9
19
Unit
13
8
10
26
15
mV
19
49
31
40
1. Data based on characterization results, not tested in production.
2. For more details and conditions, see Figure 33 Maximum VREFINT scaler startup time from power down.
Figure 33. Maximum VREFINT scaler startup time from power down
069
114/134
DocID025540 Rev 4
STM32F358xC
6.3.21
Electrical characteristics
Operational amplifier characteristics
Table 73. Operational amplifier characteristics(1)
Symbol
Parameter
Condition
Min
Typ
Max
Unit
VDDA
Analog supply voltage
-
2.4
-
3.6
V
CMIR
Common mode input range
-
0
-
VDDA
V
-
-
4
-
-
6
25°C, No Load
on output.
VIOFFSET
Input offset voltage
Maximum
calibration range All
voltage/Temp.
After offset
calibration
ΔVIOFFSET
mV
25°C, No Load
on output.
-
-
1.6
All
voltage/Temp.
-
-
3
Input offset voltage drift
-
-
5
-
µV/°C
ILOAD
Drive current
-
-
-
500
µA
IDDOPAMP
Consumption
No load,
quiescent mode
-
690
1450
µA
-
-
90
-
dB
73
117
-
dB
CMRR
Common mode rejection ratio
PSRR
Power supply rejection ratio
GBW
Bandwidth
-
-
8.2
-
MHz
SR
Slew rate
-
-
4.7
-
V/µs
RLOAD
Resistive load
-
4
-
-
kΩ
CLOAD
Capacitive load
-
-
-
50
pF
Rload = min,
Input at VDDA.
-
-
100
Rload = 20K,
Input at VDDA.
-
-
20
Rload = min,
input at 0V
-
-
100
Rload = 20K,
input at 0V.
-
-
20
VOHSAT
VOLSAT
ϕm
tOFFTRIM
tWAKEUP
DC
High saturation voltage
Low saturation voltage
mV
Phase margin
-
-
62
-
°
Offset trim time: during calibration,
minimum time needed between two
steps to have 1 mV accuracy
-
-
-
2
ms
-
2.8
5
µs
Wake up time from OFF state.
CLOAD ≤50 pf,
RLOAD ≥ 4 kΩ,
Follower
configuration
DocID025540 Rev 4
115/134
118
Electrical characteristics
STM32F358xC
Table 73. Operational amplifier characteristics(1) (continued)
Symbol
PGA gain
Rnetwork
Parameter
Condition
PGA BW
en
Typ
Max
Unit
-
2
-
-
-
4
-
-
-
8
-
-
-
16
-
-
Gain=2
-
5.4/5.4
-
Gain=4
-
16.2/5.4
-
Gain=8
-
37.8/5.4
-
Gain=16
-
40.5/2.7
-
-
-1%
-
1%
-
-
-
±0.2(3)
PGA Gain = 2,
Cload = 50pF,
Rload = 4 KΩ
-
4
-
PGA Gain = 4,
Cload = 50pF,
Rload = 4 KΩ
-
2
-
PGA Gain = 8,
Cload = 50pF,
Rload = 4 KΩ
-
1
-
PGA Gain = 16,
Cload = 50pF,
Rload = 4 KΩ
-
0.5
-
@ 1KHz, Output
loaded with
4 KΩ
-
109
-
Non inverting gain value
-
R2/R1 internal resistance values in
PGA mode (2)
PGA gain error PGA gain error
Ibias
Min
OPAMP input bias current
PGA bandwidth for different non
inverting gain
Voltage noise density
@ 10KHz,
Output loaded
with 4 KΩ
1. Guaranteed by design, not tested in production.
2. R2 is the internal resistance between OPAMP output and OPAMP inverting input.
R1 is the internal resistance between OPAMP inverting input and ground.
The PGA gain =1+R2/R1
3. Mostly TTa I/O leakage, when used in analog mode.
116/134
DocID025540 Rev 4
kΩ
µA
MHz
-
43
-
nV
----------Hz
STM32F358xC
Electrical characteristics
Figure 34. OPAMP Voltage Noise versus Frequency
DocID025540 Rev 4
117/134
118
Electrical characteristics
6.3.22
STM32F358xC
Temperature sensor characteristics
Table 74. TS characteristics
Symbol
Parameter
TL(1)
Min
Typ
Max
Unit
-
±1
±2
°C
Average slope
4.0
4.3
4.6
mV/°C
Voltage at 25 °C
1.34
1.43
1.52
V
4
-
10
µs
2.2
-
-
µs
VSENSE linearity with temperature
(1)
Avg_Slope
V25
tSTART(1)
TS_temp(1)(2)
Startup time
ADC sampling time when reading the
temperature
1. Guaranteed by design, not tested in production.
2. Shortest sampling time can be determined in the application by multiple iterations.
Table 75. Temperature sensor calibration values
Calibration value name
6.3.23
Description
Memory address
TS_CAL1
TS ADC raw data acquired at
temperature of 30 °C,
VDDA= 3.3 V
0x1FFF F7B8 - 0x1FFF F7B9
TS_CAL2
TS ADC raw data acquired at
temperature of 110 °C
VDDA= 3.3 V
0x1FFF F7C2 - 0x1FFF F7C3
VBAT monitoring characteristics
Table 76. VBAT monitoring characteristics
Symbol
Parameter
Min
Typ
Max
Unit
KΩ
R
Resistor bridge for VBAT
-
50
-
Q
Ratio on VBAT measurement
-
2
-
Error on Q
-1
-
+1
%
ADC sampling time when reading the VBAT
1mV accuracy
2.2
-
-
µs
Er
(1)
TS_vbat(1)(2)
1. Guaranteed by design, not tested in production.
2. Shortest sampling time can be determined in the application by multiple iterations.
118/134
DocID025540 Rev 4
STM32F358xC
7
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
7.1
LQFP100 – 14 x 14 mm, low-profile quad flat package
information
Figure 35. LQFP100 – 14 x 14 mm, low-profile quad flat package outline
MM
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1. Drawing is not to scale.
Table 77. LQPF100 – 14 x 14 mm, low-profile quad flat package mechanical data
Symbol
inches(1)
millimeters
Min
Typ
Max
Min
Typ
Max
A
-
-
1.60
-
-
0.063
A1
0.05
-
0.15
0.002
-
0.0059
DocID025540 Rev 4
119/134
131
Package information
STM32F358xC
Table 77. LQPF100 – 14 x 14 mm, low-profile quad flat package mechanical data (continued)
Symbol
inches(1)
millimeters
Min
Typ
Max
Min
Typ
Max
A2
1.35
1.40
1.45
0.0531
0.0551
0.0571
b
0.17
0.22
0.27
0.0067
0.0087
0.0106
c
0.09
-
0.2
0.0035
-
0.0079
D
15.80
16.00
16.2
0.622
0.6299
0.6378
D1
13.80
14.00
14.2
0.5433
0.5512
0.5591
D3
-
12.00
-
-
0.4724
-
E
15.80
16.00
16.2
0.622
0.6299
0.6378
E1
13.80
14.00
14.2
0.5433
0.5512
0.5591
E3
-
12.00
-
-
0.4724
-
e
-
0.50
-
-
0.0197
-
L
0.45
0.60
0.75
0.0177
0.0236
0.0295
L1
-
1.00
-
-
0.0394
-
K
0°
3.5°
7°
0°
3.5°
7°
ccc
-
-
0.08
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 36. LQFP100 – 14 x 14 mm, low-profile quad flat package recommended
footprint
AIC
1. Dimensions are in millimeters.
120/134
DocID025540 Rev 4
STM32F358xC
Package information
Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Figure 37. LQFP100 – 14 x 14 mm, low-profile quad flat package top view example
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1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
DocID025540 Rev 4
121/134
131
Package information
7.2
STM32F358xC
LQFP64 – 10 x 10 mm, low-profile quad flat package
information
Figure 38. LQFP64 – 10 x 10 mm, low-profile quad flat package outline
PP
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1. Drawing is not to scale.
Table 78. LQFP64 – 10 x 10 mm, low-profile quad flat package mechanical
data
inches(1)
millimeters
Symbol
122/134
Min
Typ
Max
Min
Typ
Max
A
-
-
1.60
-
-
0.0630
A1
0.05
-
0.15
0.0020
-
0.0059
A2
1.350
1.40
1.45
0.0531
0.0551
0.0571
b
0.17
0.22
0.27
0.0067
0.0087
0.0106
c
0.09
-
0.20
0.0035
D
-
12.00
-
-
0.4724
-
D1
-
10.00
-
-
0.3937
-
D3
-
7.50
-
-
0.2953
-
E
-
12.00
-
-
0.4724
-
DocID025540 Rev 4
0.0079
STM32F358xC
Package information
Table 78. LQFP64 – 10 x 10 mm, low-profile quad flat package mechanical data
(continued)
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
E1
-
10.00
-
-
0.3937
-
E3
-
7.50
-
-
0.2953
-
e
-
0.50
-
-
0.0197
-
K
0°
3.5°
7°
0°
3.5°
7°
L
0.45
0.60
0.75
0.0177
0.0236
0.0295
L1
-
1.00
-
-
0.0394
-
ccc
-
-
0.08
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 39. LQFP64 – 10 x 10 mm, low-profile quad flat package recommended
footprint
AIC
1. Dimensions are in millimeters.
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Package information
STM32F358xC
Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Figure 40. LQFP64 – 10 x 10 mm, low-profile quad flat package top view example
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1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
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STM32F358xC
LQFP48 – 7 x 7 mm, low-profile quad flat package
information
Figure 41. LQFP48 – 7 x 7 mm, low-profile quad flat package outline
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B
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0).
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1. Drawing is not to scale.
Table 79. LQFP48 – 7 x 7 mm, low-profile quad flat package mechanical
data
Symbol
inches(1)
millimeters
Min
Typ
Max
Min
Typ
Max
A
-
-
1.60
-
-
0.0630
A1
0.05
-
0.15
0.0020
-
0.0059
A2
1.35
1.40
1.45
0.0531
0.0551
0.0571
b
0.17
0.22
0.27
0.0067
0.0087
0.0106
c
0.09
-
0.20
0.0035
-
0.0079
D
8.80
9.00
9.20
0.3465
0.3543
0.3622
D1
6.80
7.00
7.20
0.2677
0.2756
0.2835
D3
-
5.50
-
-
0.2165
-
E
8.80
9.00
9.20
0.3465
0.3543
0.3622
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Package information
STM32F358xC
Table 79. LQFP48 – 7 x 7 mm, low-profile quad flat package mechanical data
(continued)
Symbol
inches(1)
millimeters
Min
Typ
Max
Min
Typ
Max
E1
6.80
7.00
7.20
0.2677
0.2756
0.2835
E3
-
5.50
-
-
0.2165
-
e
-
0.50
-
-
0.0197
-
L
0.45
0.60
0.75
0.0177
0.0236
0.0295
L1
-
1.00
-
-
0.0394
-
K
0°
3.5°
7°
0°
3.5°
7°
ccc
-
-
0.08
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 42. LQFP48 - 7 x 7 mm, low-profile quad flat package recommended footprint
AID
1. Dimensions are in millimeters.
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Package information
Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Figure 43. LQFP48 - 7 x 7 mm, low-profile quad flat package top view example
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1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
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Package information
7.4
STM32F358xC
Thermal characteristics
The maximum chip junction temperature (TJmax) must never exceed the values given in
Table 24: General operating conditions on page 56.
The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated
using the following equation:
TJ max = TA max + (PD max x ΘJA)
Where:
•
TA max is the maximum ambient temperature in °C,
•
ΘJA is the package junction-to-ambient thermal resistance, in ° C/W,
•
PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),
•
PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip
internal power.
PI/O max represents the maximum power dissipation on output pins where:
PI/O max = Σ (VOL × IOL) + Σ((VDD – VOH) × IOH),
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the
application.
Table 80. Package thermal characteristics
Symbol
ΘJA
7.4.1
Parameter
Value
Thermal resistance junction-ambient
LQFP64 - 10 × 10 mm / 0.5 mm pitch
45
Thermal resistance junction-ambient
LQFP48 - 7 × 7 mm
55
Thermal resistance junction-ambient
LQFP100 - 14 × 14 mm / 0.5 mm pitch
41
Unit
°C/W
Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org
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7.4.2
Package information
Selecting the product temperature range
When ordering the microcontroller, the temperature range is specified in the ordering
information scheme shown in Section 8: Part numbering.
Each temperature range suffix corresponds to a specific guaranteed ambient temperature at
maximum dissipation and, to a specific maximum junction temperature.
As applications do not commonly use the STM32F358xC devices at the maximum
dissipation, it is useful to calculate the exact power consumption and junction temperature
to determine which temperature range will be best suited to the application.
The following examples show how to calculate the temperature range needed for a given
application.
Example 1: High-performance application
Assuming the following application conditions:
Maximum ambient temperature TAmax = 82 °C (measured according to JESD51-2),
IDDmax = 50 mA, VDD = 3.5 V, maximum 3 I/Os used at the same time in output at low
level with IOL = 8 mA, VOL= 0.4 V and maximum 2 I/Os used at the same time in output
at low level with IOL = 20 mA, VOL= 1.3 V
PINTmax = 50 mA × 3.5 V= 175 mW
PIOmax = 3 × 8 mA × 0.4 V + 2 × 20 mA × 1.3 V = 61.6 mW
This gives: PINTmax = 175 mW and PIOmax = 61.6 mW:
PDmax = 175 + 61.6 = 236.6 mW
Thus: PDmax = 236.6 mW
Using the values obtained in Table 80 TJmax is calculated as follows:
–
For LQFP64, 45°C/W
TJmax = 82 °C + (45°C/W × 236.6 mW) = 82 °C + 10.65 °C = 92.65 °C
This is within the range of the suffix 6 version parts (–40 < TJ < 105 °C).
In this case, parts must be ordered at least with the temperature range suffix 6 (see
Section 8: Part numbering).
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Package information
STM32F358xC
Example 2: High-temperature application
Using the same rules, it is possible to address applications that run at high ambient
temperatures with a low dissipation, as long as junction temperature TJ remains within the
specified range.
Assuming the following application conditions:
Maximum ambient temperature TAmax = 115 °C (measured according to JESD51-2),
IDDmax = 20 mA, VDD = 3.5 V, maximum 9 I/Os used at the same time in output at low
level with IOL = 8 mA, VOL= 0.4 V
PINTmax = 20 mA × 3.5 V= 70 mW
PIOmax = 9 × 8 mA × 0.4 V = 28.8 mW
This gives: PINTmax = 70 mW and PIOmax = 28.8 mW:
PDmax = 70 + 28.8 = 98.8 mW
Thus: PDmax = 98.8 mW
Using the values obtained in Table 80 TJmax is calculated as follows:
–
For LQFP100, 41°C/W
TJmax = 115 °C + (41°C/W × 98.8 mW) = 115 °C + 4.05 °C = 119.05 °C
This is within the range of the suffix 7 version parts (–40 < TJ < 125 °C).
In this case, parts must be ordered at least with the temperature range suffix 7 (see
Section 8: Part numbering).
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8
Part numbering
Part numbering
Table 81. Ordering information scheme
Example:
STM32
F
358
R
C
T
6
xxx
Device family
STM32 = ARM-based 32-bit microcontroller
Product type
F = general-purpose
Device subfamily
358 = STM32F358
Pin count
C = 48 pins
R = 64 pins
V = 100 pins
Flash memory size
C = 256 Kbytes of Flash memory
Package
T = LQFP
Temperature range
6 = Industrial temperature range, –40 to 85 °C
7 = Industrial temperature range, –40 to 105 °C
Options
xxx = programmed parts
TR = tape and reel
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.
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Revision history
9
STM32F358xC
Revision history
Table 82. Document revision history
Date
Revision
17-Apr-2014
1
Initial release.
2
Updated core description in cover page.
Updated Figure 1: STM32F358xC block diagram.
Updated HSI characteristics Table 42: HSI oscillator characteristics
and Figure 17: HSI oscillator accuracy characterization results for
soldered parts.
Updated Table 29: Typical and maximum current consumption from the
VDDA supply.
Updated Table 51: I/O current injection susceptibility adding ‘on NPOR
pin”.
Updated Table 37: Low-power mode wakeup timings.
Updated Figure 18: TC and TTa I/O input characteristics and
Figure 19: Five volt tolerant (FT and FTf) I/O input characteristics.
Updated Table 13: STM32F358xC pin definitions adding note for I/Os
featuring an analog output function (DAC_OUT,OPAMP_OUT).
Updated Table 64: ADC characteristics adding IDDA & IREF
consumptions.
Added Figure 28: ADC typical current consumption on VDDA pin and
Figure 29: ADC typical current consumption on VREF+ pin.
Added Section 3.8: Interconnect matrix.
Updated Section 6.3.5: Wakeup time from low-power mode removing
standby mode.
Added note for Table 31: Typical and maximum VDDA consumption in
Stop mode and Table 30: Typical and maximum VDD consumption in
Stop mode.
Updated Section 7: Package information with new LQFP100, LQFP64,
LQFP48 package markings.
Updated Table 13: STM32F358xC pin definitions and alternate
functions tables replacing usart_rts by usart_rts_de.
10-Dec-2014
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Changes
DocID025540 Rev 4
STM32F358xC
Revision history
Table 82. Document revision history (continued)
Date
30-Jan-2015
17-Apr-2015
Revision
Changes
3
Updated Section 6.3.20: Comparator characteristics modifying ts_sc,
VDDA characteristics in Table 76 and adding Figure 36: Maximum
VREFINT scaler startup time from power down.
Updated IDD data current consumption in Table 40: HSE oscillator
characteristics.
4
Updated Table 36: Peripheral current consumption with 12.6uA/MHzBusMatrix, 7.6uA/MHz-DMA1, 6.1uA/MHz-DMA2 new current values.
Updated Section 7: Package information: with new package
information structure adding 1 sub paragraph for each package.
Updated Figure 40: LQFP100 – 14 x 14 mm, low-profile quad flat
package top view example removing gate mark.
Added note for all package device markings: “the following figure gives
an example of topside marking orientation versus pin 1 identifier
location”.
Updated Table 82: LQFP64 – 10 x 10 mm, low-profile quad flat
package mechanical data.
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