STMICROELECTRONICS VND5050AJTR-E

VND5050AJ-E
VND5050AK-E
Double channel high side driver with analog current sense
for automotive applications
Features
General
Max supply voltage
VCC
41V
Operating voltage range
VCC
4.5 to 36V
Max On-State resistance (per ch.)
RON
50 mΩ
Current limitation (typ)
ILIMH
18 A
Off state supply current
IS
2 µA(*)
(*) Typical value with all loads connected
Application
■
All types of resistive, inductive and capacitive loads
■ Suitable as LED driver
Main
■
■
■
■
■
■
Inrush current active management by power
limitation
Very low stand-by current
3.0V CMOS compatible input
Optimized electromagnetic emission
Very low electromagnetic susceptibility
In compliance with the 2002/95/ec european
directive
Diagnostic Functions
■
Proportional load current sense
High current sense precision for wide range
currents
■ Current sense disable
■ Thermal shutdown indication
■ Very low current sense leakage
■
Protections
■
Undervoltage shut-down
Overvoltage clamp
■ Load current limitation
■
PowerSSO-12
PowerSSO-24
■
Self limiting of fast thermal transients
Protection against loss of ground and loss of
VCC
■ Thermal shut down
■
■
Reverse battery protection (see Figure 24)
■
Electrostatic discharge protection
Description
The VND5050AJ-E, VND5050AK-E is a monolithic
device made using STMicroelectronics VIPower
M0-5 technology. It is intended for driving resistive
or inductive loads with one side connected to
ground. Active VCC pin voltage clamp protects the
device against low energy spikes (see ISO7637
transient compatibility table).
This device integrates an analog current sense
which delivers a current proportional to the load
current (according to a known ratio) when
CS_DIS is driven low or left open.
When CS_DIS is driven high, the CURRENT
SENSE pin is in a high impedance condition.
Output current limitation protects the device in
overload condition. In case of long overload
duration, the device limits the dissipated power to
safe level up to thermal shut-down intervention.
Thermal shut-down with automatic restart allows
the device to recover normal operation as soon as
fault condition disappears..
Order codes
April 2006
Package
Part number (Tube)
Part number (Tape & Reel)
PowerSSO-12
VND5050AJ-E
VND5050AJTR-E
PowerSSO-24
VND5050AK-E
VND5050AKTR-E
Rev 2
1/26
www.st.com
26
Contents
VND5050AJ-E / VND5050AK-E
Contents
1
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
2.1
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2
Thermal Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.3
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.4
Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1
4
5
6
2/26
GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 15
3.1.1
Solution 1: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1.2
Solution 2: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2
Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3
µC I/Os protection: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1
PowerSSO-12 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2
PowerSSO-24 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.1
Package Mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.2
Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
VND5050AJ-E / VND5050AK-E
Block diagram and pin description
1
Block diagram and pin description
Figure 1.
Block Diagram
VCC
UNDERVOLTAGE
VCC
CLAMP
OUTPUT1
PwCLAMP 1
GND
CURRENT
SENSE1
DRIVER 1
ILIM 1
INPUT1
LOGIC
PwCLAMP 2
DRIVER 2
VDSLIM 1
PwrLIM 1
OUTPUT2
ILIM 2
OVERTEMP. 1
INPUT2
VDSLIM 2
IOUT1
K1
CURRENT
SENSE2
OVERTEMP. 2
IOUT2
K2
PwrLIM 2
CS_DIS
Table 1.
Pin Function
Name
Function
VCC
Battery connection
OUTPUT1,2
Power output
GND
Ground connection. Must be reverse battery protected by an external diode/resistor network
INPUT1,2
Voltage controlled input pin with hysteresis, CMOS compatible. Controls output switch state
CURRENT
SENSE1,2
CS_DIS
Figure 2.
Analog current sense pin, delivers a current proportional to the load current
Active high CMOS compatible pin, to disable the current sense pin
Configuration diagram (top view) & suggested connections for unused and n.c. pins
TAB = Vcc
GND
INPUT2
INPUT1
CURRENT SENSE1
CURRENT SENSE2
CS_DIS
1
2
3
4
5
6
12
11
10
9
8
7
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
VCC
GND
N.C.
INPUT2
N.C.
INPUT1
N.C.
CURRENT SENSE1
N.C.
CURRENT SENSE2
CS_DIS.
VCC
Vcc
OUTPUT2
OUTPUT2
OUTPUT1
OUTPUT1
Vcc
TAB = VCC
PowerSSO-12
Connection / Pin
Floating
To Ground
PowerSSO-24
Current Sense
N.C.
Output
Input
CS_DIS
N.R.
X
X
X
X
Through 1KΩ resistor
X
N.R.
Through 10KΩ resistor
10KΩ
N.R. = Not recommended
3/26
Electrical specifications
2
VND5050AJ-E / VND5050AK-E
Electrical specifications
Figure 3.
Current and Voltage Conventions
IS
VCC
ICSD
OUTPUT1
CS_DIS
VCSD
CURRENT
SENSE1
IIN1
INPUT1
VIN1
IIN2
OUTPUT2
VCC
IOUT1
VOUT1
ISENSE1
VSENSE1
IOUT2
VOUT2
INPUT2
VIN2
GND
CURRENT
SENSE2
ISENSE2
VSENSE2
IGND
VFn = VOUTn - VCC during reverse battery condition
2.1
Absolute Maximum Ratings
Table 2.
Absolute Maximum Ratings
Symbol
Parameter
Unit
VCC
DC supply voltage
41
V
-VCC
Reverse DC supply voltage
0.3
V
-IGND
DC reverse ground pin current
200
mA
IOUT
DC output current
Internally limited
A
-IOUT
Reverse DC output current
IIN
ICSD
12
A
DC input current
-1 to 10
mA
DC current sense disable input current
-1 to 10
mA
200
mA
VCC-41
+VCC
V
V
51
mJ
4000
2000
4000
5000
5000
V
V
V
V
V
-ICSENSE DC Reverse CS pin current
VCSENSE Current sense maximum voltage
EMAX
Maximum switching energy
(L=1.5mH; RL=0Ω; Vbat=13.5V; Tjstart=150°C; IOUT = IlimL(Typ.) )
VESD
Electrostatic Discharge (Human Body Model: R=1.5KΩ;
C=100pF)
– INPUT
– CURRENT SENSE
– CS_DIS
– OUTPUT
– VCC
VESD
Charge device model (CDM-AEC-Q100-011)
Tj
Tstg
4/26
Value
750
V
Junction operating temperature
-40 to 150
°C
Storage temperature
-55 to 150
°C
VND5050AJ-E / VND5050AK-E
2.2
Thermal Data
Table 3.
Thermal Data
Electrical specifications
Value
Symbol
Parameter
Unit
Rthj-case
Thermal resistance junction-case (Max.)
(with one channel ON)
Rthj-amb
Thermal resistance junction-ambient (Max.)
2.3
PowerSSO-12
PowerSSO-24
2.7
2.7
°C/W
See Figure 26
See Figure 30
°C/W
Electrical Characteristics
8V<VCC<36V; -40°C<Tj<150°C, unless otherwise specified.
Table 4.
Power section
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
4.5
13
36
V
4.5
V
VCC
Operating supply voltage
VUSD
Undervoltage shutdown
3.5
VUSDhyst
Undervoltage shut-down
hysteresis
0.5
On state resistance(2)
IOUT=2A; Tj=25°C
IOUT=2A; Tj=150°C
IOUT=2A; VCC=5V; Tj=25°C
Vclamp
Clamp Voltage
IS=20mA
IS
Supply current
Off State; VCC=13V; Tj=25°C;
VIN=VOUT=VSENSE=VCSD=0V
On State; VCC=13V; VIN=5V; IOUT=0A
Off state output current(2)
VIN=VOUT=0V; VCC=13V; Tj=25°C
VIN=VOUT=0V; VCC=13V; Tj=125°C
Output - VCC diode voltage(2)
-IOUT=4A; Tj=150°C
RON
IL(off)
VF
41
0
0
V
50
100
65
mΩ
mΩ
mΩ
46
52
V
2(1)
3
5(1)
6
µA
mA
0.01
3
5
µA
0.7
V
Max.
Unit
(1) PowerMOS leakage included.
(2) For each channel
Table 5.
Symbol
Switching (VCC=13V)
Parameter
Test Conditions
Min.
Typ.
td(on)
Turn-on delay time
RL=6.5Ω (see Figure 6)
25
µs
td(off)
Turn-off delay time
RL=6.5Ω (see Figure 6)
35
µs
dVOUT/dt(on) Turn-on voltage slope
RL=6.5Ω
see Figure 19
V/µs
dVOUT/dt(off) Turn-off voltage slope
RL=6.5Ω
see Figure 20
V/µs
WON
Switching energy losses
during twon
RL=6.5Ω (see Figure 6)
0.24
mJ
WOFF
Switching energy losses
during twoff
RL=6.5Ω (see Figure 6)
0.2
mJ
5/26
Electrical specifications
Table 6.
Symbol
Logic input
Parameter
VIL
Input low level voltage
IIL
Low level input current
VIH
Input high level voltage
IIH
High level input current
VI(hyst)
Input hysteresis voltage
VICL
Input clamp voltage
VCSDL
CS_DIS low level voltage
ICSDL
Low level CS_DIS current
VCSDH
CS_DIS high level voltage
ICSDH
High level CS_DIS current
VCSD(hyst)
CS_DIS hysteresis voltage
VCSCL
Table 7.
Symbol
VND5050AJ-E / VND5050AK-E
CS_DIS clamp voltage
Test Conditions
VIN=0.9V
Unit
0.9
V
1
µA
2.1
V
10
7
V
V
0.9
V
-0.7
VCSD=0.9V
1
µA
2.1
V
VCSD=2.1V
10
0.25
ICSD=1mA
ICSD=-1mA
µA
V
5.5
IIN=1mA
IIN=-1mA
µA
V
5.5
7
V
V
-0.7
Protections and Diagnostics (1)
Parameter
Test Conditions
VCC=13V
5V<VCC<36V
IlimL
Short circuit current during
thermal cycling
VCC=13V TR<Tj<TTSD
TTSD
Shutdown temperature
TR
Reset temperature
TRS
Thermal reset of STATUS
VON
Max.
0.25
DC Short circuit current
VDEMAG
Typ.
VIN=2.1V
IlimH
THYST
Min.
Min.
Typ.
Max.
Unit
12
18
24
24
A
A
7
150
175
A
200
TRS + 1 TRS + 5
135
Thermal hysteresis (TTSD-TR)
Turn-off output voltage
clamp
IOUT=2A; VIN=0; L=6mH
Output voltage drop
limitation
IOUT=0.1A; Tj= -40°C...+150°C
(see Figure 7)
°C
°C
°C
7
°C
VCC-41 VCC-46 VCC-52
V
25
mV
(1) To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals
must be used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must
limit the duration and number of activation cycles
6/26
VND5050AJ-E / VND5050AK-E
Table 8.
Symbol
Electrical specifications
Current Sense (8V<VCC<16V)
Parameter
Test Conditions
Min.
Typ.
Max.
IOUT/ISENSE
IOUT=0.05A; VSENSE=0.5V;VCSD=0V;
Tj= -40°C...150°C
1270
2360
3450
K1
IOUT/ISENSE
IOUT=1A; VSENSE=0.5V;VCSD=0V;
Tj= -40°C
Tj= 25°C...150°C
1470
1570
2020
2020
2610
2470
K2
IOUT/ISENSE
IOUT=2A; VSENSE=4V;VCSD=0V;
Tj= -40°C
Tj= 25°C...150°C
1740
1790
2020
2020
2320
2250
K3
IOUT/ISENSE
IOUT=4A; VSENSE=4V;VCSD=0V;
Tj=-40°C
Tj=25°C...150°C
1880
1900
2010
2010
2160
2120
K0
ISENSE0
Analog sense leakage
current
Unit
IOUT=0A; VSENSE=0V;
VCSD=5V; VIN=0V; Tj=-40°C...150°C
VCSD=0V; VIN=5V; Tj=-40°C...150°C
0
0
1
2
µA
µA
IOUT=2A; VSENSE=0V;
VCSD=5V; VIN=5V; Tj=-40°C...150°C
0
1
µA
5
VSENSE
Max analog sense
output voltage
IOUT=4A; VCSD=0V
VSENSEH
Analog sense output
voltage in
overtemperature
condition
VCC=13V; RSENSE=10KΩ
9
V
ISENSEH
Analog sense output
current in
overtemperature
condition
VCC=13V; VSENSE=5V
8
mA
Delay Response time
tDSENSE1H from falling edge of
CS_DIS pin
VSENSE<4V, 0.5A<Iout<4A
ISENSE=90% of ISENSE max (see Figure 4)
50
100
µs
Delay Response time
tDSENSE1L from rising edge of
CS_DIS pin
VSENSE<4V, 0.5A<Iout<4A
ISENSE=10% of ISENSE max (see Figure 4)
5
20
µs
Delay Response time
tDSENSE2H from rising edge of
INPUT pin
VSENSE<4V, 0.5A<Iout<4A
ISENSE=90% of ISENSE max (see Figure 4)
80
300
µs
Delay Response time
tDSENSE2L from falling edge of
INPUT pin
VSENSE<4V, 0.5A<Iout<4A
ISENSE=10% of ISENSE max (see Figure 4)
100
250
µs
V
7/26
Electrical specifications
Figure 4.
VND5050AJ-E / VND5050AK-E
Current Sense Delay Characteristics
INPUT
CS_DIS
LOAD CURRENT
SENSE CURRENT
tDSENSE2H
Figure 5.
tDSENSE1L
tDSENSE1H
tDSENSE2L
IOUT/ISENSE Vs. IOUT (see Table 8 for details)
Iout/Isense
4000
3500
max Tj= -40ºC to 150ºC
3000
2500
max Tj=25...150ºC
typical value
2000
1500
min Tj=25...150ºC
min Tj=-40ºC to 150ºC
1000
500
0
0
1
2
3
Iout (A)
8/26
4
5
VND5050AJ-E / VND5050AK-E
Table 9.
Electrical specifications
Truth table
INPUT
OUTPUT
SENSE (VCSD=0V)(1)
Normal operation
L
H
L
H
0
Nominal
Overtemperature
L
H
L
L
0
VSENSEH
Undervoltage
L
H
L
L
0
0
Short circuit to GND
(Rsc ≤ 10 mΩ)
L
H
H
L
L
L
0
0 if Tj < TTSD
VSENSEH if Tj > TTSD
Short circuit to VCC
L
H
H
H
0
< Nominal
Negative output voltage
clamp
L
L
0
CONDITIONS
(1) If the VCSD is high, the SENSE output is at a high impedance, its potential depends on leakage currents
and external circuit.
Figure 6.
Switching characteristics
VOUT
tWon
tWoff
90%
80%
dVOUT/dt(off)
dVOUT/dt(on)
10%
tr
tf
t
INPUT
td(on)
td(off)
t
Figure 7.
Output Voltage Drop Limitation
Vcc-Vout
Tj=150oC
Tj=25oC
Tj=-40oC
Von
Von/Ron(T)
Iout
9/26
Electrical specifications
Table 10.
VND5050AJ-E / VND5050AK-E
Electrical Transient Requirements
ISO 7637-2:
2004(E)
TEST LEVELS
Test Pulse
III
IV
Number of
pulses or
test times
1
2a
3a
3b
4
5b(1)
-75V
+37V
-100V
+75V
-6V
+40V
-100V
+50V
-150V
+100V
-7V
+40V
5000 pulses
5000 pulses
1h
1h
1 pulse
1 pulse
ISO 7637-2:
2004(E)
Burst cycle/pulse repetition
time
0.5 s
0.2 s
90 ms
90 ms
5s
5s
100 ms
100 ms
Delays and
Impedance
2 ms, 10 Ω
50 µs, 2 Ω
0.1 µs, 50 Ω
0.1 µs, 50 Ω
100 ms, 0.01 Ω
400 ms, 2 Ω
TEST LEVEL RESULTS
Test Pulse
III
IV
1
2a
3a
3b
4
5b(1)
C
C
C
C
C
C
C
C
C
C
C
C
CLASS
CONTENTS
C
All functions of the device are performed as designed after exposure to disturbance.
One or more functions of the device are not performed as designed after exposure to disturbance
and cannot be returned to proper operation without replacing the device.
E
(1) For load dump exceeding the above value a centralized suppressor must be adopted.
10/26
VND5050AJ-E / VND5050AK-E
Figure 8.
Electrical specifications
Waveforms
NORMAL OPERATION
INPUT
CS_DIS
LOAD CURRENT
SENSE CURRENT
UNDERVOLTAGE
VUSDhyst
VCC
VUSD
INPUT
CS_DIS
LOAD CURRENT
SENSE CURRENT
SHORT TO VCC
INPUT
CS_DIS
LOAD VOLTAGE
LOAD CURRENT
SENSE CURRENT
<Nominal
<Nominal
OVERLOAD OPERATION
Tj
TTSD
TR
TRS
INPUT
CS_DIS
ILIMH
ILIML
LOAD CURRENT
VSENSEH
SENSE CURRENT
current power
limitation limitation
thermal cycling
SHORTED LOAD
NORMAL LOAD
11/26
Electrical specifications
VND5050AJ-E / VND5050AK-E
2.4
Electrical characteristics curves
Figure 9.
Off State Output Current
Figure 10. High Level Input Current
Iloff (uA)
Iih (uA)
1
5
4.5
0.875
Off State
Vcc=13V
Vin=Vout=0V
0.75
Vin=2.1V
4
3.5
0.625
3
0.5
2.5
2
0.375
1.5
0.25
1
0.125
0.5
0
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
Tc (°C)
50
75
100
125
150
175
100
125
150
175
150
175
Tc (°C)
Figure 11. Input Clamp Voltage
Figure 12. Input High Level
Vih (V)
Vicl (V)
4
7
6.8
3.5
Iin=1mA
6.6
3
6.4
2.5
6.2
2
6
5.8
1.5
5.6
1
5.4
0.5
5.2
0
5
-50
-25
0
25
50
75
100
125
150
-50
175
-25
0
25
Figure 13. Input Low Level
75
Figure 14. Input Hysteresis Voltage
Vil (V)
Vhyst (V)
2
1
1.8
0.9
1.6
0.8
1.4
0.7
1.2
0.6
1
0.5
0.8
0.4
0.6
0.3
0.4
0.2
0.2
0.1
0
0
-50
-25
0
25
50
75
Tc (°C)
12/26
50
Tc (°C)
Tc (°C)
100
125
150
175
-50
-25
0
25
50
75
Tc (°C)
100
125
VND5050AJ-E / VND5050AK-E
Electrical specifications
Figure 15. On State Resistance Vs. Tcase
Figure 16. On State Resistance Vs. VCC
Ron (mOhm)
Ron (mOhm)
100
100
90
90
Iout=2A
Vcc=13V
80
Tc= 150°C
80
70
70
60
60
50
50
40
40
30
30
20
20
10
10
Tc= 125°C
Tc= 25°C
Tc= - 40°C
0
0
-50
-25
0
25
50
75
100
125
150
0
175
5
10
15
20
25
30
35
40
150
175
150
175
Vcc (V)
Tc (°C)
Figure 17. Undervoltage Shutdown
Figure 18. ILIMH Vs. Tcase
Ilimh (A)
Vusd (V)
16
25
14
22.5
12
20
10
17.5
8
15
6
12.5
4
10
2
7.5
Vcc=13V
5
0
-50
-25
0
25
50
75
100
125
150
-50
175
-25
0
25
50
75
100
125
Tc (°C)
Tc (°C)
Figure 19. Turn-on Voltage Slope
Figure 20. Turn-off Voltage Slope
(dVout/dt)on (V/ms)
(dVout/dt)off (V/ms)
1000
1000
900
900
Vcc=13V
RI=6.5Ohm
800
Vcc=13V
RI=6.5Ohm
800
700
700
600
600
500
500
400
400
300
300
200
200
100
100
0
0
-50
-25
0
25
50
75
Tc (°C)
100
125
150
175
-50
-25
0
25
50
75
100
125
Tc (°C)
13/26
Electrical specifications
VND5050AJ-E / VND5050AK-E
Figure 21. STAT_DIS Clamp Voltage
Figure 22. Low Level STAT_DIS Voltage
Vsdcl(V)
Vsdl(V)
8
14
7
12
6
Isd=1mA
10
5
8
4
6
3
4
2
2
1
0
0
-50
-25
0
25
50
75
100
125
150
175
Tc (°C)
Vsdh(V)
8
7
6
5
4
3
2
1
0
-25
0
25
50
75
Tc (°C)
14/26
-25
0
25
50
75
Tc (°C)
Figure 23. High Level STAT_DIS Voltage
-50
-50
100
125
150
175
100
125
150
175
VND5050AJ-E / VND5050AK-E
3
Application information
Application information
Figure 24. Application schematic
+5V
VCC
Rprot
CS_DIS
Dld
µC
Rprot
INPUT
OUTPUT
Rprot
CURRENT SENSE
GND
RSENSE
CEXT
VGND
RGND
DGND
Note: Channel 2 has the same internal circuit as channel 1.
3.1
GND protection network against reverse battery
3.1.1
Solution 1:
Resistor in the ground line (RGND only). This can be used with any type of load.
The following is an indication on how to dimension the RGND resistor.
1.
RGND ≤ 600mV / (IS(on)max).
2.
RGND ≥ (−VCC) / (-IGND)
where -IGND is the DC reverse ground pin current and can be found in the absolute
maximum rating section of the device datasheet.
Power Dissipation in RGND (when VCC<0: during reverse battery situations) is:
PD= (-VCC)2/RGND
This resistor can be shared amongst several different HSDs. Please note that the value of
this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the
maximum on-state currents of the different devices.
Please note that if the microprocessor ground is not shared by the device ground then the
RGND will produce a shift (IS(on)max * RGND) in the input thresholds and the status output
values. This shift will vary depending on how many devices are ON in the case of several
high side drivers sharing the same RGND.
15/26
Application information
VND5050AJ-E / VND5050AK-E
If the calculated power dissipation leads to a large resistor or several devices have to share
the same resistor then ST suggests to utilize Solution 2 (see below).
3.1.2
Solution 2:
A diode (DGND) in the ground line.
A resistor (RGND=1kΩ) should be inserted in parallel to DGND if the device drives an
inductive load.
This small signal diode can be safely shared amongst several different HSDs. Also in this
case, the presence of the ground network will produce a shift (≈600mV) in the input
threshold and in the status output values if the microprocessor ground is not common to the
device ground. This shift will not vary if more than one HSD shares the same diode/resistor
network.
3.2
Load dump protection
Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the
VCC max DC rating. The same applies if the device is subject to transients on the VCC line
that are greater than the ones shown in the ISO 7637-2: 2004(E) table.
3.3
µC I/Os protection:
If a ground protection network is used and negative transient are present on the VCC line,
the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line to
prevent the µC I/Os pins to latch-up.
The value of these resistors is a compromise between the leakage current of µC and the
current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of µC
I/Os.
-VCCpeak/Ilatchup ≤ Rprot ≤ (VOHµC-VIH-VGND) / IIHmax
Calculation example:
For VCCpeak= - 100V and Ilatchup ≥ 20mA; VOHµC ≥ 4.5V
5kΩ ≤ Rprot ≤ 180kΩ.
Recommended values: Rprot =10kΩ, CEXT=10nF.
16/26
VND5050AJ-E / VND5050AK-E
Package and PCB thermal data
4
Package and PCB thermal data
4.1
PowerSSO-12 thermal data
Figure 25. PowerSSO-12 PC Board
Layout condition of Rth and Zth measurements (PCB: Double layer, Thermal Vias, FR4 area= 77mm x 86mm,
PCB thickness=1.6mm, Cu thickness=70µm (front and back side), Copper areas: from minimum pad lay-out to 8cm2).
Figure 26. Rthj-amb Vs. PCB copper area in open box free air condition
RTHj_amb(°C/W)
70
65
60
55
50
45
40
0
2
4
6
8
10
PCB Cu heatsink area (cm^2)
Figure 27. PowerSSO-12 Thermal Impedance Junction Ambient Single Pulse
ZTH (˚C/W)
1000
Footprint
100
2 cm2
8 cm2
10
1
0.1
0.0001
0.001
0.01
0.1
1
Time (s)
10
100
1000
Pulse Calculation Formula
Z THδ = R TH ⋅ δ + Z THtp ( 1 – δ )
where δ = tP/T
17/26
Package and PCB thermal data
VND5050AJ-E / VND5050AK-E
Figure 28. Thermal Fitting Model of a Double Channel HSD in PowerSSO-12
Thermal Parameter
Area/island (cm2)
18/26
Footprint
R1=R7 (°C/W)
0.7
R2=R8 (°C/W)
2.8
2
8
R3 (°C/W)
7
R4 (°C/W)
10
10
9
R5 (°C/W)
22
15
10
R6 (°C/W)
26
20
15
C1=C7 (W.s/°C)
0.001
C2=C8 (W.s/°C)
0.0025
C3 (W.s/°C)
0.05
C4 (W.s/°C)
0.2
0.1
0.1
C5 (W.s/°C)
0.27
0.8
1
C6 (W.s/°C)
3
6
9
VND5050AJ-E / VND5050AK-E
4.2
Package and PCB thermal data
PowerSSO-24 thermal data
Figure 29. PowerSSO-24 PC Board
Layout condition of Rth and Zth measurements (PCB: Double layer, Thermal Vias, FR4 area= 77mm x 86mm,
PCB thickness=1.6mm, Cu thickness=70µm (front and back side), Copper areas: from minimum pad lay-out to 8cm2).
Figure 30. Rthj-amb Vs. PCB copper area in open box free air condition
RTHj_amb(°C/W)
55
50
45
40
35
30
0
2
4
6
8
10
PCB Cu heatsink area (cm^2)
Figure 31. PowerSSO-24 Thermal Impedance Junction Ambient Single Pulse
ZTH (˚C/W)
1000
100
Footprint
2 cm2
8 cm2
10
1
0.1
0.0001
0.001
0.01
0.1
1
Time (s)
10
100
1000
Pulse Calculation Formula
Z THδ = R TH ⋅ δ + Z THtp ( 1 – δ )
where δ = tP/T
19/26
Package and PCB thermal data
VND5050AJ-E / VND5050AK-E
Figure 32. Thermal Fitting Model of a Single Channel HSD in PowerSSO-12
Thermal Parameter
Area/island (cm2)
20/26
Footprint
2
8
R1=R7 (°C/W)
0.4
R2=R8 (°C/W)
2
R3 (°C/W)
6
R4 (°C/W)
7.7
R5 (°C/W)
9
9
8
R6 (°C/W)
28
17
10
C1=C7 (W.s/°C)
0.001
C2=C8 (W.s/°C)
0.0022
C3 (W.s/°C)
0.025
C4 (W.s/°C)
0.75
C5 (W.s/°C)
1
4
9
C6 (W.s/°C)
2.2
5
17
VND5050AJ-E / VND5050AK-E
5
Package information
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second-level interconnect. The category of
Second-Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97.
The maximum ratings related to soldering conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
5.1
Package Mechanical
Figure 33. PowerSSO-12™ Package Dimensions
D
0.25 mm
GAUGE PLANE
h x 45˚
C
A2
A
B
ddd
SEATING
PLANE
C
A1
C
12
L
K
7
X
E
H
Y
1
BOTTOM
VIEW
6
e
Table 11.
PowerSSO-12™ Mechanical Data
Symbol
A
A1
A2
B
C
D
E
e
H
h
L
k
X
Y
ddd
millimeters
Min
1.250
0.000
1.100
0.230
0.190
4.800
3.800
Typ
Max
1.620
0.100
1.650
0.410
0.250
5.000
4.000
0.800
5.800
0.250
0.400
0°
1.900
3.600
6.200
0.500
1.270
8°
2.500
4.200
0.100
21/26
Package information
VND5050AJ-E / VND5050AK-E
Figure 34. PowerSSO-24™ Package Dimensions
PowerSSO-24™ Mechanical Data
Table 12.
Symbol
millimeters
Min
Max
A
2.15
2.47
A2
2.15
2.40
a1
0
0.075
b
0.33
0.51
c
0.23
0.32
D
10.10
10.50
E
7.4
7.6
e
0.8
e3
8.8
G
0.1
G1
0.06
H
10.1
h
L
10.5
0.4
0.55
N
22/26
Typ
0.85
10deg
X
4.1
4.7
Y
6.5
7.1
VND5050AJ-E / VND5050AK-E
5.2
Package information
Packing information
Figure 35. PowerSSO-12 Tube Shipment (No Suffix)
B
Base Q.ty
Bulk Q.ty
Tube length (± 0.5)
A
B
C (± 0.1)
C
A
100
2000
532
1.85
6.75
0.6
All dimensions are in mm.
Figure 36. PowerSSO-12 Tape And Reel Shipment (Suffix “TR”)
REEL DIMENSIONS
Base Q.ty
Bulk Q.ty
A (max)
B (min)
C (± 0.2)
F
G (+ 2 / -0)
N (min)
T (max)
2500
2500
330
1.5
13
20.2
12.4
60
18.4
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width
Tape Hole Spacing
Component Spacing
Hole Diameter
Hole Diameter
Hole Position
Compartment Depth
Hole Spacing
All dimensions are in mm.
W
P0 (± 0.1)
P
D (± 0.05)
D1 (min)
F (± 0.1)
K (max)
P1 (± 0.1)
12
4
8
1.5
1.5
5.5
4.5
2
End
Start
Top
cover
tape
No components
Components
No components
500mm min
Empty components pockets
saled with cover tape.
500mm min
User direction of feed
23/26
Package information
VND5050AJ-E / VND5050AK-E
Figure 37. PowerSSO-24 Tube Shipment (No Suffix)
C
Base Q.ty
Bulk Q.ty
Tube length (± 0.5)
A
B
C (± 0.1)
B
49
1225
532
3.5
13.8
0.6
All dimensions are in mm.
A
Figure 38. PowerSSO-24 Tape And Reel Shipment (Suffix “TR”)
REEL DIMENSIONS
Base Q.ty
Bulk Q.ty
A (max)
B (min)
C (± 0.2)
F
G (+ 2 / -0)
N (min)
T (max)
1000
1000
330
1.5
13
20.2
24.4
100
30.4
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width
W
Tape Hole Spacing
P0 (± 0.1)
Component Spacing
P
Hole Diameter
D (± 0.05)
Hole Diameter
D1 (min)
Hole Position
F (± 0.1)
Compartment Depth K (max)
Hole Spacing
P1 (± 0.1)
All dimensions are in mm.
24
4
12
1.55
1.5
11.5
2.85
2
End
Start
Top
cover
tape
No components
Components
Empty components pockets
saled with cover tape.
User direction of feed
24/26
No components
500mm min
500mm min
VND5050AJ-E / VND5050AK-E
6
Revision history
Revision history
Table 13.
Document revision history
Date
Revision
Changes
30-Mar-2006
1
Initial release.
14-Apr-2006
2
PowerSSO-24 dimensions table update.
25/26
VND5050AJ-E / VND5050AK-E
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26/26