EN2340QI

Enpirion® Power Datasheet
EN2340QI 4A PowerSoC
Voltage Mode Synchronous
PWM Buck with Integrated Inductor
Description
Features
The EN2340QI is a Power System on a Chip
(PowerSoC) DC-DC converter. It integrates MOSFET
switches, small-signal control circuits, compensation
and an integrated inductor in an advanced 8x11x3mm
QFN module. It offers high efficiency, excellent line
and load regulation over temperature and up to the
full 4A load range. The EN2340QI operates over a
wide input voltage range and is specifically designed
to meet the precise voltage and fast transient
requirements of high-performance products. The
EN2340 features frequency synchronization to an
external clock, power OK output voltage monitor,
programmable soft-start along with thermal and over
current protection. The device’s advanced circuit
design, ultra high switching frequency and proprietary
integrated inductor technology delivers high-quality,
ultra compact, non-isolated DC-DC conversion.
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The Altera Enpirion solution significantly helps in
system design and productivity by offering greatly
simplified board design, layout and manufacturing
requirements. In addition, overall system level
reliability is improved given the small number of
components required with the Altera Enpirion
solution.
•
•
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All Altera Enpirion products are RoHS compliant,
halogen free and are compatible with lead-free
manufacturing environments.
22nF
22µF
1206
Efficiency vs. Output Current
95
ON
ENABLE
90
VOUT
PG BTMP VDDB BGND
VOUT
PVIN
OFF
•
Space Constrained Applications
Distributed Power Architectures
Output Voltage Ripple Sensitive Applications
Beat Frequency Sensitive Applications
Servers, Embedded Computing Systems,
LAN/SAN Adapter Cards, RAID Storage Systems,
Industrial Automation, Test and Measurement,
and Telecommunications
0.22µF
EN2340QI
RVB
4.75k
Applications
85
2x
22µF
0805
RA
EFFICIENCY (%)
RPG
560
VIN
•
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•
•
•
•
•
Integrated Inductor, MOSFETs, Controller
Wide Input Voltage Range: 4.5V – 14V
Guaranteed 4A IOUT at 85°C with No Airflow
Frequency Synchronization (External Clock)
1% Initial VOUT Accuracy
High Efficiency (Up to 95%)
Output Enable Pin and Power OK signal
Programmable Soft-Start Time
Pin Compatible with the EN2360QI (6A)
Under Voltage Lockout Protection (UVLO)
Programmable Over Current Protection
Thermal Shutdown and Short Circuit Protection
RoHS Compliant, MSL Level 3, 260oC Reflow
CA
AVINO
AVIN
1µF
1µF
RCA
VFB
SS
47nF
PGND
PGND
FADJ
AGND
RCLX
RB
80
Actual Solution Size
200mm 2
75
70
CONDITIONS
VIN = 12.0V
Dual Supply
65
60
VOUT = 5.0V
55
VOUT = 1.8V
50
0
RFS
RCLX
Figure 1. Simplified Applications Circuit
(Footprint Optimized)
0.5
1
1.5
2
2.5
3
3.5
4
OUTPUT CURRENT (A)
Figure 2. Highest Efficiency in Smallest Solution Size
www.altera.com/enpirion
06878
October 9, 2013
Rev E
EN2340QI
Ordering Information
Part Number
Package Markings
TAMBIENT Rating (°C)
Package Description
EN2340QI
EN2340QI
-40 to +85
68-pin (8mm x 11mm x 3mm) QFN T&R
EN2340QI
QFN Evaluation Board
EVB-EN2340QI
Packing and Marking Information: www.altera.com/support/reliability/packing/rel-packing-and-marking.html
AGND
AVIN
ENABLE
POK
52
51
50
49
RCLX
57
VFB
FQADJ
58
AGND
NC
59
53
AGND
60
54
NC(SW)
61
SS
NC(SW)
62
EAOUT
NC(SW)
63
55
NC
64
56
NC
NC
65
NC
67
66
NC
68
Pin Assignments (Top View)
48
S_OUT
NC
1
NC
2
47
S_IN
NC
3
46
BGND
KEEP OUT
NC
4
45
VDDB
NC
5
44
BTMP
NC
6
7
NC
8
NC
9
NC
KEEP OUT
KEEP OUT
NC
69
PGND
43
PG
42
AVINO
31
32
33
34
PGND
PGND
PGND
NC(SW)
PGND
28
NC(SW)
PGND
27
NC
30
26
NC
29
25
VOUT
PGND
24
23
VOUT
VOUT
PVIN
22
PVIN
35
21
36
14
VOUT
13
NC
VOUT
NC
20
PVIN
19
PVIN
37
VOUT
38
12
18
11
NC
17
NC
VOUT
PVIN
VOUT
39
16
10
15
PVIN
NC
PVIN
40
VOUT
41
Figure 3: Pin Out Diagram (Top View)
NOTE A: NC pins are not to be electrically connected to each other or to any external signal, ground, or voltage. All pins
including NC pins must be soldered to the PCB. Failure to follow this guideline may result in part malfunction or damage.
NOTE B: Shaded area highlights exposed metal below the package that is not to be mechanically or electrically
connected to the PCB. Refer to Figure 15 for details.
NOTE C: White ‘dot’ on top left is pin 1 indicator on top of the device package.
Pin Description
I/O Legend:
PIN
P=Power
NAME
I/O
1-15,
25-26,
59, 6468
NC
NC
16-24
VOUT
O
27-28,
NC(SW)
NC
G=Ground
NC=No Connect
I=Input O=Output
I/O=Input/Output
FUNCTION
NO CONNECT – These pins may be internally connected. Do not connect them to each
other or to any other electrical signal. Failure to follow this guideline may result in device
damage.
Regulated converter output. Connect these pins to the load and place output capacitor
between these pins and PGND pins 29-34.
NO CONNECT – These pins are internally connected to the common switching node of the
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06878
October 9, 2013
Rev E
EN2340QI
PIN
NAME
I/O
61-63
29-34
PGND
G
35-41
PVIN
P
42
AVINO
O
43
PG
I/O
44
BTMP
I/O
45
VDDB
O
46
BGND
G
47
S_IN
I
48
S_OUT
O
49
POK
O
50
ENABLE
I
51
AVIN
P
52, 53,
60
AGND
G
54
VFB
I/O
55
EAOUT
O
56
SS
I/O
57
RCLX
I/O
58
FADJ
I/O
69
PGND
FUNCTION
internal MOSFETs. They are not to be electrically connected to any external signal, ground,
or voltage. Failure to follow this guideline may result in damage to the device.
Input/output power ground. Connect these pins to the ground electrode of the input and
output filter capacitors. See VOUT and PVIN pin descriptions for more details.
Input power supply. Connect to input power supply. Decouple with input capacitor to
PGND pins 29-34.
Internal 3.3V linear regulator output. Connect this pin to AVIN (Pin 51) for applications
where operation from a single input voltage (PVIN) is required. If AVINO is being used,
place a 1µF, X5R/X7R, capacitor between AVINO and AGND as close as possible to
AVINO.
PMOS gate. Place a 22nF, X5R/X7R, capacitor between this pin and BTMP. A 560Ω
damping resistor may be connected from PVIN to PG to reduce noise inside the controller
in extreme ambient conditions.
Bottom plate ground. See pin 43 description.
Internal regulated voltage used for the internal control circuitry. Place a 0.22µF, X5R/X7R,
capacitor between this pin and BGND.
Ground for VDDB. See pin 45 description.
Digital synchronization input. This pin accepts either an input clock to phase lock the
internal switching frequency or a S_OUT signal from another EN2340QI. Leave this pin
floating if not used.
Digital synchronization output. PWM signal is output on this pin. Leave this pin floating if
not used.
Power OK is an open drain transistor (pulled up to AVIN or similar voltage) used for power
system state indication. POK is logic high when VOUT is within -10% of VOUT nominal.
Leave this pin floating if not used.
Output enable. Applying a logic high to this pin enables the output and initiates a soft-start.
Applying a logic low disables the output. ENABLE logic cannot be higher than AVIN (refer to
Absolute Maximum Ratings). Do not leave floating. See Power Up/Down Sequencing
section for details.
3.3V Input power supply for the controller. Place a 1µF, X5R/X7R, capacitor between AVIN
and AGND.
Analog ground. This is the ground return for the controller. All AGND pins need to be
connected to a quiet ground.
External feedback input. The feedback loop is closed through this pin. A voltage divider at
VOUT is used to set the output voltage. The mid-point of the divider is connected to VFB. A
phase lead network from this pin to VOUT is also required to stabilize the loop.
Optional error amplifier output. Allows for customization of the control loop.
Soft-start node. The soft-start capacitor is connected between this pin and AGND. The
value of this capacitor determines the startup time.
Programmable over-current protection. Placement of a resistor on this pin will adjust the
over-current protection threshold. See Table 2 for the recommended RCLX Value to set
OCP at the nominal value specified in the Electrical Characteristics table. No current limit
protection when this pin is left floating.
Adding a resistor (RFS) to this pin will adjust the switching frequency of the EN2340QI. See
Table 1 for suggested resistor values on RFS for various PVIN/VOUT combinations to
maximize efficiency. Do not leave floating.
Not a perimeter pin. Device thermal pad to be connected to the system GND plane for heatsinking purposes.
www.altera.com/enpirion, Page 3
06878
October 9, 2013
Rev E
EN2340QI
Absolute Maximum Ratings
CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond the recommended operating
conditions is not implied. Stress beyond the absolute maximum ratings may impair device life. Exposure to absolute
maximum rated conditions for extended periods may affect device reliability.
MIN
MAX
UNITS
Voltages on : PVIN, VOUT, PG
PARAMETER
SYMBOL
-0.5
15
V
Voltages on: ENABLE, POK
-0.3
AVIN+0.3
V
Dual Supply PVIN Rising and Falling Slew Rate (Note 1)
0.3
25
V/ms
Single Supply PVIN Rising and Falling Slew Rate (Note 1)
0.3
6
V/ms
Pin Voltages – AVINO, AVIN, S_IN, S_OUT
2.5
6.0
V
Pin Voltages – VFB, SS, EAOUT, RCLX, FADJ, VDDB, BTMP
-0.5
2.75
V
-65
150
°C
150
°C
Reflow Temp, 10 Sec, MSL3 JEDEC J-STD-020A
260
°C
ESD Rating (based on Human Body Model)
2000
V
ESD Rating (based on CDM)
500
V
Storage Temperature Range
TSTG
Maximum Operating Junction Temperature
TJ-ABS Max
Recommended Operating Conditions
SYMBOL
MIN
MAX
UNITS
Input Voltage Range
PARAMETER
PVIN
4.5
14
V
AVIN: Controller Supply Voltage
AVIN
2.5
5.5
V
Output Voltage Range (Note 2)
VOUT
0.75
5
V
Output Current
IOUT
4
A
Operating Ambient Temperature
TA
-40
+85
°C
Operating Junction Temperature
TJ
-40
+125
°C
Thermal Characteristics
SYMBOL
TYP
UNITS
Thermal Resistance: Junction to Ambient (0 LFM) (Note 3)
PARAMETER
θJA
18
°C/W
Thermal Resistance: Junction to Case (0 LFM)
θJC
2
°C/W
Thermal Shutdown
TSD
160
°C
Thermal Shutdown Hysteresis
TSDH
35
°C
Note 1: PVIN rising and falling slew rates cannot be outside of specification. For accurate power up sequencing, use a
fast ENABLE logic after both AVIN and PVIN is high.
Note 2: Maximum VOUT ≤ VIN - 2.5V
Note 3: Based on 2oz. external copper layers and proper thermal design in line with EIJ/JEDEC JESD51-7 standard for
high thermal conductivity boards.
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06878
October 9, 2013
Rev E
EN2340QI
Electrical Characteristics
NOTE: VIN=12V, Minimum and Maximum values are over operating ambient temperature range (-40°C ≤ TA ≤ +85°C)
unless otherwise noted. Typical values are at TA = 25°C.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Operating Input Voltage
PVIN
4.5
14.0
V
Controller Input Voltage
AVIN
2.5
5.5
V
AVIN Under Voltage
Lock-Out Rising
AVINUVLOR
Voltage above which UVLO is not
asserted
1.7
2.2
2.4
V
AVIN Under Voltage
Lock-Out Falling
AVINOVLOF
Voltage below which UVLO is
asserted
1.7
2.1
2.3
V
AVIN pin Input Current
Internal Linear
Regulator Output
Shut-Down Supply
Current
IAVIN
7
mA
AVINO
3.3
V
IPVINS
PVIN=12V, AVIN=3.3V, ENABLE=0V
500
µA
IAVINS
PVIN=12V, AVIN=3.3V, ENABLE=0V
100
µA
Feedback Pin Voltage
VFB
VIN = 12V, ILOAD = 0, TA = 25°C Only
0.7425
0.750
0.7575
V
Feedback Pin Voltage
VFB
4.5V ≤ VIN ≤ 14V; 0A ≤ ILOAD ≤ 4A
0.735
0.750
0.765
V
Feedback Pin Input
Leakage Current
IFB
VFB pin input leakage current
(Note 4)
5
nA
VOUT Rise Time
tRISE
-5
CSS = 47nF (Note 5 and Note 6)
3.2
Soft-Start Capacitor
Range
CSS_RANGE
10
Continuous Output
Current
IOUT_CONT
0
Over Current Trip Level
IOCP
Reference Table 2
47
ms
68
nF
4
A
6
A
Disable Threshold
VDISABLE
ENABLE pin logic Low
0.0
0.95
V
ENABLE Threshold
VENABLE
ENABLE pin logic High
1.25
AVIN
V
ENABLE Lockout Time
TENLOCKOUT
ENABLE Input Current
IENABLE
Switching Frequency
FSW
370k internal pull-down (Note 4)
RFS =3kΩ
External SYNC Clock
Frequency Lock Range
FPLL_LOCK
Range of SYNC clock frequency (See
Table 1)
S_IN Threshold – Low
VS_IN_LO
S_IN clock logic low level (Note 4)
S_IN Threshold – High
VS_IN_HI
S_IN clock logic high level (Note 4)
S_OUT Threshold – Low
VS_OUT_LO
S_OUT clock logic low level (Note 4)
S_OUT Threshold –
High
VS_OUT_HI
S_OUT clock logic high level (Note 4)
POK Lower Threshold
POKLT
VOUT / VOUT_NOM
POK Output low Voltage
VPOKL
With 4mA current sink into POK
POK Output Hi Voltage
VPOKH
PVIN range: 4.5V ≤ VIN ≤ 14V
POK Pin VOH Leakage
Current
IPOKL
POK High (Note 4)
8
ms
4
µA
1.0
MHz
0.8
1.8
1.8
1.8
MHz
0.8
V
2.5
V
0.8
V
2.5
V
90
%
0.4
V
AVIN
V
1
µA
Note 4: Parameter not production tested but is guaranteed by design.
Note 5: Rise time calculation begins when AVIN > VUVLO and ENABLE = HIGH.
Note 6: VOUT Rise Time Accuracy does not include soft-start capacitor tolerance.
www.altera.com/enpirion, Page 5
06878
October 9, 2013
Rev E
EN2340QI
Typical Performance Curves
Efficiency vs. Output Current
100
90
95
85
90
80
75
VOUT = 5.0V
70
VOUT = 3.3V
65
VOUT = 2.5V
60
VOUT = 1.2V
55
VOUT = 1.0V
85
EFFICIENCY (%)
EFFICIENCY (%)
Efficiency vs. Output Current
95
CONDITIONS
VIN = 12.0V
AVIN = 3.3V
Dual Supply
80
75
VOUT = 5.0V
70
VOUT = 3.3V
65
VOUT = 2.5V
60
VOUT = 1.2V
55
VOUT = 1.2V
50
50
0
0.5
1
1.5
2
2.5
OUTPUT CURRENT (A)
3
3.5
0
4
0.5
95
95
90
90
85
85
80
75
70
65
VOUT = 2.5V
60
VOUT = 1.2V
55
VOUT = 1.0V
1
1.5
2
2.5
OUTPUT CURRENT (A)
3
3.5
4
Efficiency vs. Output Current
100
EFFICIENCY (%)
EFFICIENCY (%)
Efficiency vs. Output Current
CONDITIONS
VIN = 5.0V
CONDITIONS
AVIN = 3.3V
VIN = 8.0V
Dual
Supply
80
CONDITIONS
VIN = 12.0V
75
70
DUAL SUPPLY VOUT = 5.0V
65
SINGLE SUPPLY VOUT = 5.0V
60
DUAL SUPPLY VOUT = 1.0V
55
SINGLE SUPPLY VOUT = 1.0V
50
50
0
0.5
1
1.5
2
2.5
OUTPUT CURRENT (A)
3
3.5
0
4
0.5
1
1.5
2
2.5
3
3.5
4
OUTPUT CURRENT (A)
Output Voltage vs. Output Current
Output Voltage vs. Output Current
1.010
3.310
1.008
VIN = 5V
1.006
VIN = 8V
1.004
VIN = 12V
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
CONDITIONS
VIN = 8.0V
CONDITIONS
AVIN
= 3.3V
VIN = Supply
8.0V
Dual
1.002
1.000
0.998
0.996
0.994
VIN = 8V
3.306
VIN = 12V
3.304
CONDITIONS
VOUT_NOM = 3.3V
3.302
3.300
3.298
3.296
3.294
CONDITIONS
CONDITIONS
VOUT_NOM
VIN ==5.0V
1.0V
0.992
3.308
3.292
0.990
3.290
0.0
0.5
1.0 1.5 2.0 2.5 3.0
OUTPUT CURRENT (A)
3.5
4.0
0.0
0.5
1.0 1.5 2.0 2.5 3.0
OUTPUT CURRENT (A)
3.5
4.0
www.altera.com/enpirion, Page 6
06878
October 9, 2013
Rev E
EN2340QI
Typical Performance Curves (Continued)
Output Voltage vs. Input Voltage
Output Voltage vs. Input Voltage
3.320
CONDITIONS
VOUT_NOM = 1.0V
1.015
Load = 0A
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
1.020
Load = 1A
Load = 2A
1.010
Load = 3A
1.005
Load = 4A
1.000
0.995
CONDITIONS
VOUT_NOM = 3.3V
3.315
3.310
Load = 2A
3.305
Load = 3A
3.300
Load = 4A
3.295
3.290
3.280
2
4
6
8
10
12
INPUT VOLTAGE (V)
14
16
2
4
6
8
10
12
INPUT VOLTAGE (V)
14
16
Output Voltage vs. Temperature
Output Voltage vs. Temperature
1.204
1.204
CONDITIONS
VIN = 8V
VOUT_NOM = 1.2V
1.203
1.202
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
Load = 1A
3.285
0.990
1.201
1.200
LOAD = 0A
1.199
LOAD = 1A
LOAD = 2A
1.198
LOAD = 3A
1.197
CONDITIONS
VIN = 10V
VOUT_NOM = 1.2V
1.203
1.202
1.201
1.200
LOAD = 0A
1.199
LOAD = 1A
LOAD = 2A
1.198
LOAD = 3A
1.197
LOAD = 4A
LOAD = 4A
1.196
1.196
-40
35
60
-15
10
AMBIENT TEMPERATURE ( C)
-40
85
-15
10
35
60
AMBIENT TEMPERATURE ( C)
85
Output Voltage vs. Temperature
Output Voltage vs. Temperature
1.204
1.204
CONDITIONS
VIN = 12V
VOUT_NOM = 1.2V
1.203
1.202
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
Load = 0A
1.201
1.200
LOAD = 0A
1.199
LOAD = 1A
LOAD = 2A
1.198
LOAD = 3A
1.197
CONDITIONS
VIN = 14V
VOUT_NOM = 1.2V
1.203
1.202
1.201
1.200
LOAD = 0A
1.199
LOAD = 1A
LOAD = 2A
1.198
LOAD = 3A
1.197
LOAD = 4A
LOAD = 4A
1.196
1.196
-40
-15
10
35
60
AMBIENT TEMPERATURE ( C)
85
-40
-15
10
35
60
AMBIENT TEMPERATURE ( C)
85
www.altera.com/enpirion, Page 7
06878
October 9, 2013
Rev E
EN2340QI
Typical Performance Characteristics
Output Ripple at 20MHz Bandwidth
Output Ripple at 500MHz Bandwidth
CONDITIONS
VIN = 12V
VOUT = 1V
IOUT = 2A
CIN = 2 x 22µF (1206)
COUT = 2 x 47 µF (1206)
CONDITIONS
VIN = 12V
VOUT = 1V
IOUT = 2A
CIN = 2 x 22µF (1206)
COUT = 2 x 47 µF (1206)
VOUT
(AC Coupled)
VOUT
(AC Coupled)
Output Ripple at 20MHz Bandwidth
VOUT
(AC Coupled)
Output Ripple at 500MHz Bandwidth
CONDITIONS
VIN = 12V
VOUT = 1V
IOUT = 4A
CIN = 2 x 22µF (1206)
COUT = 2 x 47 µF (1206)
VOUT
(AC Coupled)
Enable Startup/Shutdown Waveform (0A)
Enable Startup/Shutdown Waveform (4A)
ENABLE
ENABLE
VOUT
VOUT
POK
POK
LOAD
CONDITIONS
VIN = 12V
VOUT = 1V
IOUT = 4A
CIN = 2 x 22µF (1206)
COUT = 2 x 47 µF (1206)
CONDITIONS
VIN = 12V, VOUT = 1.0V, No Load, Css = 47nF
CIN = 2 x 22µF (1206), COUT = 2 x 47 µF (1206)
LOAD
CONDITIONS
VIN = 12V, VOUT = 1.0V, LOAD = 4A, Css = 47nF
CIN = 2 x 22µF (1206), COUT = 2 x 47 µF (1206)
www.altera.com/enpirion, Page 8
06878
October 9, 2013
Rev E
EN2340QI
Typical Performance Characteristics (Continued)
Load Transient from 50mA to 2A
Load Transient from 50mA to 4A
VOUT = 1V
(AC Coupled)
20mV / DIV
VOUT = 1V
(AC Coupled)
50mV / DIV
CONDITIONS
VIN = 12V, VOUT = 1V
CIN = 22µF (1206)
COUT = 2 x 22µF (0805)
Small Solution Size Configuration
LOAD
LOAD
Load Transient from 2A to 4A
CONDITIONS
VIN = 12V, VOUT = 1V
CIN = 22µF (1206)
COUT = 2 x 22µF (0805)
Small Solution Size Configuration
Load Transient from 50mA to 4A
VOUT = 1.8V
(AC Coupled)
100mV / DIV
VOUT = 1.8V
(AC Coupled)
100mV / DIV
LOAD
CONDITIONS
VIN = 12V, VOUT = 1.8V
CIN = 22µF (1206)
COUT = 2 x 22µF (0805)
Small Solution Size Configuration
LOAD
Load Transient from 50mA to 3A
Load Transient from 50mA to 3A
VOUT = 3.3V
(AC Coupled)
100mV / DIV
VOUT = 3.3V
(AC Coupled)
100mV / DIV
LOAD
CONDITIONS
VIN = 12V, VOUT = 1.8V
CIN = 22µF (1206)
COUT = 2 x 22µF (0805)
Small Solution Size Configuration
CONDITIONS
VIN = 12V, VOUT = 3.3V
CIN = 22µF (1206)
COUT = 2 x 22µF (0805)
Small Solution Size Configuration
LOAD
CONDITIONS
VIN = 12V, VOUT = 3.3V
CIN = 22µF (1206)
COUT = 2 x 47µF (1206)
Best Performance Configuration
www.altera.com/enpirion, Page 9
06878
October 9, 2013
Rev E
EN2340QI
Functional Block Diagram
S_OUT S_IN
UVLO
Digital I/O
BTMP
PVIN
PG
Linear
Regulator
To PLL
AVINO
Thermal Limit
Current Limit
NC(SW)
Gate Drive
VOUT
BGND
(-)
PWM
Comp
(+)
FADJ
PGND
VDDB
Compensation
Network
PLL/Sawtooth
Generator
EAOUT
VFB
(-)
Error
Amp
(+)
Power
Good
Logic
SS
Soft Start
ENABLE
POK
300k
Voltage Reference Generator
370k
Band Gap
Reference
EN2340QI
AVIN
AGND
Figure 4: Functional Block Diagram
Functional Description
Synchronous Buck Converter
The EN2340QI is a highly integrated synchronous,
buck converter with integrated controller, power
MOSFET switches and inductor. The nominal input
voltage (PVIN) range is 4.5V to 14V and can
support up to 4A of continuous output current. The
output voltage is programmed using an external
resistor divider network. The control loop utilizes a
Type IV Voltage-Mode compensation network and
maximizes on a low-noise PWM topology. Much of
the compensation circuitry is internal to the device.
However, a phase lead capacitor is required along
with the output voltage feedback resistor divider to
complete the Type IV compensation network.. The
high switching frequency of the EN2340QI enables
the use of small size input and output filter
capacitors, as well as a wide loop bandwidth within
a small foot print.
Protection Features:
The power supply has the following protection
features:
• Programmable Over-Current Protection
• Thermal Shutdown with Hysteresis.
• Under-Voltage Lockout Protection
Additional Features:
•
•
•
Switching Frequency Synchronization.
Programmable Soft-Start
Power OK Output Monitoring
www.altera.com/enpirion, Page 10
06878
October 9, 2013
Rev E
EN2340QI
Power Up Sequence
The EN2340QI is designed to be powered by either
a single input supply (PVIN) or two separate
supplies: one for PVIN and the other for AVIN. The
EN2340QI is not “hot pluggable.” Refer to the PVIN
Slew Rate specification on page 4.
the device at a programmed PVIN voltage level.
The lower resistor (4.02k) can be adjusted to set
startup and shutdown at a specific PVIN voltage
level. See ENABLE and DISABLE thresholds in the
Electrical Characteristics table.
Dual Input Supply Application (PVIN and AVIN):
Single Input Supply Application (PVIN):
22nF
0.22µF
RPG
560
VIN
VOUT
PG BTMP VDDB BGND
VOUT
EN2340QI
10k
ENABLE
4.02k
22µF
1206
EN2340QI
2x
22µF
0805
ENABLE
22µF
1206
RA
CA
RA
AVIN
1µF
AVIN
1µF
2x
22µF
0805
47nF
RCA
CA
AVINO
VAVIN
AVINO
1µF
VOUT
PG BTMP VDDB BGND
VOUT
PVIN
RVB
4.75k
0.22µF
PVIN
RPG
560
VIN
22nF
RCA
VFB
SS
VFB
SS
PGND
PGND
47nF
FADJ
AGND
RFS
RCLX
RB
PGND
PGND
FADJ
AGND
RCLX
RB
RFS
RCLX
RCLX
Figure 7: Dual Input Supply Schematic
Figure 5: Single Input Supply Schematic
The EN2340QI has an internal linear regulator that
converts PVIN to 3.3V. The output of the linear
regulator is provided on the AVINO pin once the
device is enabled. AVINO should be connected to
AVIN on the EN2340QI. In this application, the
following external components are required: Place
a 1µF, X5R/X7R capacitor between AVINO and
AGND as close as possible to AVINO. Place a
1µF, X5R/X7R capacitor between AVIN and AGND
as close as possible to AVIN. In addition, place a
resistor (RVB) between VDDB and AVIN, as shown
in Figure 5. Altera recommends RVB=4.75kΩ. In this
application, ENABLE cannot be asserted before
PVIN. See diagram below for a recommended
startup and shutdown sequencing.
In this application, place a 1µF, X5R/X7R, capacitor
between AVIN and AGND as close as possible to
AVIN. Refer to Figure 7 for a recommended
schematic for a dual input supply application.
For dual input supply applications, the sequencing
of the two input supplies, PVIN and AVIN, is very
important. There are two common acceptable turnon sequences for the device. AVIN can always
come up before PVIN. If PVIN comes up before
AVIN, then ENABLE must be toggled last, after
AVIN is asserted. Do not turn off AVIN before PVIN
and ENABLE during shutdown. Doing so will
disable the internal controller while there may still
be energy in the system. The device will not softshutdown properly and damage may occur. See
diagram below for a recommended startup and
shutdown sequencing.
12V
PVIN
0V
PVIN slew rate limitations
as per datasheet
12V
PVIN – Recommended
to be ramped down
after the Vout softshutdown occurs
3.3V
ENABLE
0V
Delay from ENABLE rising
edge to soft start begin
~ 1ms
VOUT
Delay from ENABLE falling
edge to soft shutdown
begin ~ 1.5ms
Soft Start Time ≈ 2ms
w/Css=47nF
PVIN
0V
PVIN slew rate limitations
as per datasheet
PVIN powered
down before AVIN
3.3V
AVIN
AVIN powered up before PVIN
0V
3.3V
ENABLE
Soft Shutdown
Time ≈ 1.3ms
w/Css=47nF
0V
Delay from ENABLE rising
edge to soft start begin
~ 1ms
VOUT
Figure 6: Single Supply Startup/Shutdown Sequence
If no external enable signal is used, a resister
divider (see Figure 5) from PVIN to ENABLE and
then to ground can be used to enable and disable
Delay from ENABLE falling
edge to soft shutdown
begin ~ 1.5ms
Soft Start Time ≈ 2ms
w/Css=47nF
PVIN/AVIN –
Recommended
to be ramped down
after the Vout softshutdown occurs
Soft Shutdown
Time ≈ 1.3ms
w/Css=47nF
Figure 8: Dual Supply Startup/Shutdown Sequencing
www.altera.com/enpirion, Page 11
06878
October 9, 2013
Rev E
EN2340QI
Enable Operation
Rfs vs. SW Frequency
The ENABLE pin provides a means to enable
normal operation or to shut down the device. A
logic high will enable the converter into normal
operation. When the ENABLE pin is asserted (high)
the device will undergo a normal soft-start. A logic
low will disable the converter. A logic low will power
down the device in a controlled manner and the
device is subsequently shut down. The ENABLE
signal has to be low for at least the ENABLE
Lockout Time (8ms) in order for the device to be reenabled. To ensure accurate startup sequencing
the ENABLE/DISABLE signal should be faster than
1V/100µs. A slower ENABLE/DISABLE signal may
result in a delayed startup and shutdown response.
SWITCHING FREQUENCY (MHz)
1.800
1.600
1.400
1.200
1.000
CONDITIONS
VIN = 6V to 12V
VOUT = 0.8V to 3.3V
0.800
0.600
0
2
4
6
8 10 12 14 16 18 20 22
RFS RESISTOR VALUE (kΩ)
Figure 9. Typical RFS vs. Switching Frequency
Pre-Bias Precaution
The EN2340QI is not designed to be turned on into
a pre-biased output voltage. Be sure the output
capacitors are not charged or the output of the
EN2340QI is not pre-biased when the EN2340QI is
first enabled.
PVIN
12V
Frequency Synchronization
The switching frequency of the EN2340QI can be
phase-locked to an external clock source to move
unwanted beat frequencies out of band. The
internal switching clock of the EN2340QI can be
phase locked to a clock signal applied to the S_IN
pin. An activity detector recognizes the presence of
an external clock signal and automatically phaselocks the internal oscillator to this external clock.
Phase-lock will occur as long as the input clock
frequency is in the range of 0.8MHz to 1.8MHz. The
external clock frequency must be within ±10% of
the nominal switching frequency set by the RFS
resistor. It is recommended to use a synchronized
clock frequency close to the typical frequency
recommendations in Table 1. A 3.01kΩ resistor
from FQADJ to ground is recommended for clock
frequencies within ±10% of 1MHz. When no clock
is present, the device reverts to the free running
frequency of the internal oscillator set by the RFS
resistor.
The efficiency performance of the EN2340QI for
various PVIN/VOUT combinations can be optimized
by adjusting the switching frequency. Table 1
shows recommended RFS values for various
PVIN/VOUT combinations in order to optimize
performance of the EN2340QI.
5V
VOUT
5.0V
3.3V
2.5V
1.8V
1.2V
<1.0V
2.5V
1.8V
1.5V
1.2V
<1.0V
RFS
30k
15k
10k
4.87k
1.65k
1.3k
22.1k
10k
6.65k
4.87k
3.01k
Typical fsw
1.7 MHz
1.38 MHz
1.3 MHz
1.15 MHz
0.95 MHz
0.8 MHz
1.4 MHz
1.3 MHz
1.25 MHz
1.15 MHz
1.0 MHz
Table 1: Recommended RFS Values
Spread Spectrum Mode
The external clock frequency may be swept
between 0.8MHz and 1.8MHz at repetition rates of
up to 10 kHz in order to reduce EMI frequency
components.
Soft-Start Operation
Soft start is a means to ramp the output voltage
gradually upon start-up. The output voltage rise
time is controlled by the choice of soft-start
capacitor, which is placed between the SS pin (pin
56) and the AGND pin (pin 52). During start-up of
the converter, the reference voltage to the error
amplifier is linearly increased to its final level by an
internal current source of approximately 10µA. The
soft-start time is measured from when VIN > VUVLOR
and ENABLE pin voltage crosses its logic high
threshold to when VOUT reaches its programmed
value. The total soft-start time can be calculated by:
Soft Start Time (ms): T SS ≈ Css [nF] x 0.067
www.altera.com/enpirion, Page 12
06878
October 9, 2013
Rev E
EN2340QI
Recommended RCLX Value
Typical soft-start time is approximately 3.2ms with
SS capacitor value of 47nF.
44
POK Operation
40
RCLX VAVLUE (kΩ))
The POK signal is an open drain signal (requires a
pull up resistor to AVIN or similar voltage) from the
converter indicating the output voltage is within the
specified range. Typically, a 100kΩ or lower
resistance is used as the pull-up resistor. The POK
signal will be logic high (AVIN) when the output
voltage is above 90% of the programmed voltage
level. If the output voltage is below this point, the
POK signal will be a logic low. The POK signal can
be used to sequence down-stream converters by
tying to their enable pins.
Over-Current Protection (OCP)
Generally, the higher the RCLX value, the higher
the current limit threshold for a given input and
output voltage condition.
Note: If the RCLX pin is left open, the output
current will be unlimited and the device will not
have current limit protection.
Reference Table 2 for a list of recommended
resistor values on RCLX that will set the OCP trip
point at the typical value of 6A, also specified in the
Electrical
Characteristics
table.
Contact
www.altera.com/mysupport for specific RCLX
values to be use for special cases.
PVIN = 8V
PVIN = 5V
38
36
34
32
CONDITIONS
Current Limit ≈ 6A
TA = 25 C
30
28
26
0.5
1
1.5
2 2.5 3 3.5 4
OUTPUT VOLTAGE (V)
4.5
5
5.5
Figure 10. Typical RCLX vs. Output Voltage
PVIN
The current limit function is achieved by sensing
the current flowing through a sense PFET. When
the sensed current exceeds the current limit for
more than 32 cycles, both power FETs are turned
off for the rest of the switching cycle. If the overcurrent condition is removed, the over-current
protection circuit will re-enable PWM operation. In
the event the OCP circuit trips consistently in
normal operation, the device enters a hiccup mode.
While in hiccup mode, the device is disabled for a
short while and restarted with a normal soft-start.
The hiccup time is approximately 32ms. This cycle
can continue indefinitely as long as the over current
condition persists. The OCP trip point depends on
PVIN, VOUT and the RCLX resistor.
PVIN = 12V
42
5V
8V
12V
VOUT Range
0.75V < VOUT ≤ 1.2V
1.2V < VOUT ≤ 2.0V
2.0V < VOUT ≤ 2.5V
0.75V < VOUT ≤ 1.2V
1.2V < VOUT ≤ 2.0V
2.0V < VOUT ≤ 3.0V
3.0V < VOUT ≤ 4.0V
4.0V < VOUT ≤ 5.0V
0.75V < VOUT ≤ 1.2V
1.2V < VOUT ≤ 2.0V
2.0V < VOUT ≤ 3.0V
3.0V < VOUT ≤ 4.0V
4.0V < VOUT ≤ 5.0V
RCLX
Value
30.1kΩ
31.6kΩ
33.2kΩ
30.9kΩ
32.4kΩ
35.7kΩ
38.3kΩ
40.2kΩ
31.6kΩ
33.2kΩ
36.5kΩ
39.2kΩ
41.2kΩ
Current
Limit
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
6A
Table 2: Recommended RCLX Values and Current Limit
Thermal Overload Protection
Thermal shutdown circuit will disable device
operation when the junction temperature exceeds
approximately 160°C. After a thermal shutdown
event, when the junction temperature drops by
approx 35°C, the converter will re-start with a
normal soft-start.
Input Under-Voltage Lock-Out (UVLO)
Internal circuits ensure that the converter will not
start switching until the AVIN input voltage is above
the specified minimum voltage. Hysteresis, input
de-glitch and output leading edge blanking ensures
high noise immunity and prevents false UVLO
triggers.
www.altera.com/enpirion, Page 13
06878
October 9, 2013
Rev E
EN2340QI
Application Information
Output Voltage Programming and Loop
Compensation
The EN2340QI output voltage is programmed using
a simple resistor divider network. A phase lead
capacitor (CA) plus a resistor (RCA) are required for
stabilizing the loop. Figure 11 shows the required
components and the equations to calculate their
values. The values recommended for CA and RCA
will vary with each PVIN and VOUT combination.
The EN2340 solution can be optimized for either
smallest size or highest performance. Please see
Table 6 for a list of recommended CA and RCA
values for each solution option.
The EN2340QI output voltage is determined by the
voltage presented at the VFB pin. This voltage is
set by way of a resistor divider between VOUT and
AGND with the midpoint going to VFB. Since VFB
is a sensitive node, do not touch the VFB node
while the device is in operation as doing so may
introduce parasitic capacitance into the control loop
that causes the device to behave abnormally and
damage may occur.
The EN2340QI uses a Type IV compensation
network.
Most of this network is integrated.
However a phase lead capacitor and a resistor are
required in parallel with the upper resistor of the
external feedback network (see Figure 11). Total
compensation is optimized for either low output
ripple or small solution size, and will result in a wide
loop bandwidth and excellent load transient
performance for most applications. See Table 6 for
compensation values for both options based on
input and output voltage conditions.
In some cases modifications to the compensation
may be required. The EN2340QI provides the
capability to modify the control loop response to
allow for customization for specific applications.
For more information, contact Altera MySupport
(www.altera.com/mysupport).
VOUT
180
(R A in kΩ)
VOUT
Round R A up to closest
RA =
CA
RA
RCA standard value higher than
the calculated value.
VFB × RA
RB =
(VOUT − VFB )
VFB
RB
 VFB is 0.75V

 nominal



Figure 11: External Feedback
Compensation. See Table 6 for details.
Input Capacitor Selection
The EN2340QI requires a 22µF/1206 input
capacitor. Low-cost, low-ESR ceramic capacitors
should be used as input capacitors for this
converter. The dielectric must be X5R or X7R
rated. Y5V or equivalent dielectric formulations
must not be used as these lose too much
capacitance with frequency, temperature and
bias voltage. In some applications, lower value
capacitors are needed in parallel with the larger,
capacitors in order to provide high frequency
decoupling.
Table 3 contains a list of
recommended input capacitors.
Recommended Input Capacitors
Description
22µF, 16V,
X5R, 10%,
1206
22µF, 16V,
X5R, 20%,
1206
MFG
P/N
Murata
GRM31CR61C226ME15
Taiyo Yuden
EMK316ABJ226ML-T
Table 3: Recommended Input Capacitors
Output Capacitor Selection
As seen from Table 6, the EN2340QI has been
optimized for use with either two 47µF/1206 or two
22µF/0805 output capacitors. Low ESR ceramic
capacitors are required with X5R or X7R rated
dielectric formulation. Y5V or equivalent dielectric
formulations must not be used as these lose
too much capacitance with frequency,
temperature and bias voltage. Table 4 contains a
list of recommended output capacitors. In some
applications, extra bulk capacitance is required at
www.altera.com/enpirion, Page 14
06878
October 9, 2013
Rev E
EN2340QI
the load. In this case, up to 1000µF of bulk
capacitance may be used at the load as long as the
minimum ESR between the device output and the
bulk capacitance is maintained. Table 4 shows the
recommended compensation components for
applications that require bulk capacitance at the
load.
PVIN (V)
4.5 to 14
≥10
<10
VOUT (V)
≥2.5
0.6 to 1.5
Min. ESR
4mΩ
9mΩ
1.5 to 2.5
7mΩ
0.6 to 1.5
12mΩ
1.5 to 2.5
9mΩ
Com pensation
COUT = 2x47µF/1206
Bulk Cap ≤ 1000µF
CA = 100pF
RA = 250kΩ
RCA = 5kΩ
Table 4: Minimum ESR for Bulk Capacitance at Load
Output ripple voltage is determined by the
aggregate output capacitor impedance. Capacitor
impedance, denoted as Z, is comprised of
capacitive reactance, effective series resistance,
ESR, and effective series inductance, ESL
reactance.
Placing output capacitors in parallel reduces the
impedance and will hence result in lower ripple
voltage.
1
Z Total
=
1
1
1
+
+ ... +
Z1 Z 2
Zn
Recommended Output Capacitors
Description
MFG
P/N
47µF, 6.3V, X5R,
20%, 1206
Murata
GRM31CR60J476ME19L
47µF, 10V, X5R,
20%, 1206
Taiyo
Yuden
LMK316BJ476ML- T
22µF, 10V, X5R,
20%, 0805
Panasonic
ECJ-2FB1A226M
22µF, 10V, X5R,
20%, 0805
Taiyo
Yuden
LMK212BJ226MG- T
Table 5: Recommended Output Capacitors
www.altera.com/enpirion, Page 15
06878
October 9, 2013
Rev E
EN2340QI
Low VOUT Ripple
Smallest Solution Size
CIN = 1 x 22µF/1206
COUT = 2 x 47µF/1206
CIN = 1 x 22µF/1206
RA= 180/(Vout0.5) kΩ
COUT = 2 x 22µF/0805
Nominal
Nominal
Nominal
Nominal
RCA
Deviation
RCA
Deviation
PVIN
VOUT
CA (pF)
Ripple
RA (kΩ)
CA (pF)
Ripple
(kΩ)
(mV)
(kΩ)
(mV)
(mV)
(mV)
(Note 7)
(Note 7)
≤1.0V
10
30
≤5
≤47
75
27
0.1
≤10
≤34
1.2V
12
27
6
48
43
39
0.1
13
33
1.5V
15
27
5
53
56
39
0.1
15
38
14V
1.8V
22
27
6
54
56
39
0.1
18
41
2.5V
27
24
8
55
51
39
0.1
26
59
3.3V
39
18
11
63
51
33
0.1
35
63
5.0V
47
8.2
18
97
75
22
5.1
42
115
≤1.0V
18
22
≤4
≤48
27
47
0.1
≤10
≤35
1.2V
22
22
5
49
75
47
0.1
13
37
1.5V
27
20
5
53
75
47
0.1
15
38
12V
1.8V
33
20
6
54
75
47
0.1
17
44
2.5V
47
18
7
54
56
47
0.1
25
59
3.3V
56
15
10
66
51
39
0.1
32
63
5.0V
56
10
16
99
75
22
5.1
39
128
≤1.0V
33
18
≤3
≤45
27
82
0.1
≤9
≤35
1.2V
39
18
4
46
30
100
0.1
13
39
1.5V
47
18
5
54
30
100
0.1
14
43
10V
1.8V
56
16
6
56
30
100
0.1
17
50
2.5V
68
12
7
57
75
56
0.1
26
70
3.3V
82
10
9
68
56
47
0.1
30
83
5.0V
100
4.3
14
98
75
33
5.1
33
140
≤1.0V
100
8.2
≤3
≤51
100
100
0.1
≤10
≤41
1.2V
100
8.2
4
51
100
100
0.1
12
43
1.5V
100
8.2
4
54
100
100
0.1
14
46
8.0V
1.8V
100
8.2
5
57
100
100
0.1
16
53
2.5V
100
8.2
6
64
91
82
0.1
23
71
3.3V
100
8.2
8
70
75
56
0.1
25
85
5.0V
100
8.2
10
110
75
56
5.1
30
127
≤1.0V
100
8.2
≤3
≤60
100
100
0.1
≤9
≤46
1.2V
100
8.2
4
63
100
100
0.1
12
51
1.5V
100
8.2
4
65
100
100
0.1
14
56
6.6V
1.8V
100
8.2
5
68
100
100
0.1
16
61
2.5V
100
8.2
5
75
100
100
0.1
19
83
3.3V
100
8.2
6
85
91
82
0.1
22
106
≤1.0V
100
8.2
≤3
≤73
100
100
0.1
≤9
≤56
1.2V
100
8.2
3
75
100
100
0.1
11
63
5V
1.5V
100
8.2
4
76
100
100
0.1
13
70
1.8V
100
8.2
4
80
100
100
0.1
13
78
2.5V
100
8.2
4
88
100
100
0.1
14
98
Table 6: RA, CA, and RCA Values for Various PVIN/VOUT Combinations: Low V OUT Ripple vs. Smallest Solution Size. See
Figure 11. Use the equations in Figure 11 to calculate RA (for low VOUT ripple option) and RB.
Note 7: Nominal Deviation is for a 2A load transient step.
Note 8: For compensation values of output voltage in between the specified output voltages, choose compensation values
of the lower output voltage setting.
www.altera.com/enpirion, Page 16
06878
October 9, 2013
Rev E
EN2340QI
Thermal Considerations
Thermal considerations are important power supply
design facts that cannot be avoided in the real
world. Whenever there are power losses in a
system, the heat that is generated by the power
dissipation needs to be accounted for. The Altera
Enpirion PowerSoC helps alleviate some of those
concerns.
The Altera Enpirion EN2340QI DC-DC converter is
packaged in an 8x11x3mm 68-pin QFN package.
The QFN package is constructed with copper lead
frames that have exposed thermal pads. The
exposed thermal pad on the package should be
soldered directly on to a copper ground pad on the
printed circuit board (PCB) to act as a heat sink.
The recommended maximum junction temperature
for continuous operation is 125°C. Continuous
operation above 125°C may reduce long-term
reliability. The device has a thermal overload
protection circuit designed to turn off the device at
an approximate junction temperature value of
160°C.
The EN2340QI is guaranteed to support the full 4A
output current up to 85°C ambient temperature.
The following example and calculations illustrate
the thermal performance of the EN2340QI.
Example:
Figure 12: Efficiency vs. Output Current
For VIN = 12V, VOUT = 3.3V at 4A, η ≈ 91%
η = POUT / PIN = 91% = 0.91
PIN = POUT / η
PIN ≈ 13.2W / 0.9 ≈ 14.51W
The power dissipation (PD ) is the power loss in the
system and can be calculated by subtracting the
output power from the input power.
PD = PIN – POUT
≈ 14.51W – 13.2W ≈ 1.31W
With the power dissipation known, the temperature
rise in the device may be estimated based on the
theta JA value (θJA). The θJA parameter estimates
how much the temperature will rise in the device for
every watt of power dissipation. The EN2340QI has
a θJA value of 18 ºC/W without airflow.
Determine the change in temperature (ΔT) based
on PD and θJA.
ΔT = PD x θJA
ΔT ≈ 1.31W x 18°C/W = 23.5°C ≈ 24°C
VIN = 12V
The junction temperature (T J ) of the device is
approximately the ambient temperature (T A) plus
the change in temperature. We assume the initial
ambient temperature to be 25°C.
VOUT = 3.3V
T J = T A + ΔT
IOUT = 4A
T J ≈ 25°C + 24°C ≈ 49°C
First calculate the output power.
POUT = 3.3V x 4A = 13.2W
The maximum operating junction temperature
(T JMAX) of the device is 125°C, so the device can
operate at a higher ambient temperature. The
maximum ambient temperature (T AMAX) allowed can
be calculated.
Next, determine the input power based on the
efficiency (η) shown in Figure 12.
T AMAX = T JMAX – PD x θJA
Efficiency vs. Output Current
≈ 125°C – 24°C ≈ 101°C
The maximum ambient temperature the device can
reach is 101°C given the input and output
conditions. Note that the efficiency will be slightly
lower at higher temperatures and this calculation is
an estimate.
100
90
91%
EFFICIENCY (%)
80
70
60
50
40
30
20
VOUT = 3.3V
10
CONDITIONS
VIN = 12.0V
0
0
0.5
1
1.5
2
2.5
OUTPUT CURRENT (A)
3
3.5
4
www.altera.com/enpirion, Page 17
06878
October 9, 2013
Rev E
EN2340QI
Engineering Schematic
Figure 13: Engineering Schematic with Engineering Notes
www.altera.com/enpirion, Page 18
06878
October 9, 2013
Rev E
EN2340QI
Layout Recommendation
Figure 14: Top Layer Layout with Critical Components
(Top View). See Figure 13 for corresponding schematic.
This layout only shows the critical components and
top layer traces for minimum footprint in singlesupply mode. Alternate circuit configurations &
other low-power pins need to be connected and
routed according to customer application. Please
see the Gerber files at www.altera.com for details
on all layers.
Recommendation 1: Input and output filter
capacitors should be placed on the same side of
the PCB, and as close to the EN2340QI package
as possible. They should be connected to the
device with very short and wide traces. Do not use
thermal reliefs or spokes when connecting the
capacitor pads to the respective nodes. The +V and
GND traces between the capacitors and the
EN2340QI should be as close to each other as
possible so that the gap between the two nodes is
minimized, even under the capacitors.
Recommendation 2: The PGND connections for
the input and output capacitors on layer 1 need to
have a slit between them in order to provide some
separation between input and output current loops.
Recommendation 3: The system ground plane
should be the first layer immediately below the
surface layer. This ground plane should be
continuous and un-interrupted below the converter
and the input/output capacitors.
Recommendation 4: The thermal pad underneath
the component must be connected to the system
ground plane through as many vias as possible.
The drill diameter of the vias should be 0.33mm,
and the vias must have at least 1 oz. copper plating
on the inside wall, making the finished hole size
around 0.20-0.26mm. Do not use thermal reliefs or
spokes to connect the vias to the ground plane.
This connection provides the path for heat
dissipation from the converter.
Recommendation 5: Multiple small vias (the same
size as the thermal vias discussed in
recommendation 4) should be used to connect
ground terminal of the input capacitor and output
capacitors to the system ground plane. It is
preferred to put these vias along the edge of the
GND copper closest to the +V copper. These vias
connect the input/output filter capacitors to the
GND plane, and help reduce parasitic inductances
in the input and output current loops. If vias cannot
be placed under the capacitors, then place them on
both sides of the slit in the top layer PGND copper.
Recommendation 6: AVIN is the power supply for
the small-signal control circuits. It should be
connected to the input voltage at a quiet point. In
Figure 14 this connection is made at the input
capacitor.
Recommendation 7: The layer 1 metal under the
device must not be more than shown in Figure 14.
Refer to the section regarding Exposed Metal on
Bottom of Package. As with any switch-mode
DC/DC converter, try not to run sensitive signal or
control lines underneath the converter package on
other layers.
Recommendation 8: The VOUT sense point should
be just after the last output filter capacitor. Keep the
sense trace short in order to avoid noise coupling
into the node. Contact Altera MySupport for any
remote sensing applications.
Recommendation 9: Keep RA, CA, RB, and RCA
close to the VFB pin (Refer to Figure 14). The VFB
pin is a high-impedance, sensitive node. Keep the
trace to this pin as short as possible. Whenever
possible, connect RB directly to the AGND pins 52
and 53 instead of going through the GND plane.
Recommendation 10: Follow all the layout
recommendations as close as possible to optimize
performance. Altera provides schematic and layout
reviews for all customer designs. Contact Altera
MySupport
for
detailed
support
(www.altera.com/mysupport).
www.altera.com/enpirion, Page 19
06878
October 9, 2013
Rev E
EN2340QI
Design Considerations for Lead-Frame Based Modules
Exposed Metal on Bottom of Package
Lead-frames offer many advantages in thermal performance, in reduced electrical lead resistance, and in
overall foot print. However, they do require some special considerations.
In the assembly process lead frame construction requires that, for mechanical support, some of the lead-frame
cantilevers be exposed at the point where wire-bond or internal passives are attached. This results in several
small pads being exposed on the bottom of the package, as shown in Figure 15.
Only the thermal pad and the perimeter pads are to be mechanically or electrically connected to the PC board.
The PCB top layer under the EN2340QI should be clear of any metal (copper pours, traces, or vias) except for
the thermal pad. The “shaded-out” area in Figure 15 represents the area that should be clear of any metal on
the top layer of the PCB. Any layer 1 metal under the shaded-out area runs the risk of undesirable shorted
connections even if it is covered by soldermask.
The solder stencil aperture should be smaller than the PCB ground pad. This will prevent excess solder from
causing bridging between adjacent pins or other exposed metal under the package. Please consult the
Enpirion Manufacturing Application Note for more details and recommendations.
Figure 15: Lead-Frame exposed metal (Bottom View)
Shaded area highlights exposed metal that is not to be mechanically or electrically connected to the PCB.
www.altera.com/enpirion, Page 20
06878
October 9, 2013
Rev E
EN2340QI
Recommended PCB Footprint
Figure 16: EN2340QI PCB Footprint (Top View)
The solder stencil aperture for the thermal pad (shown in blue) is based on Altera’s manufacturing recommendations
www.altera.com/enpirion, Page 21
06878
October 9, 2013
Rev E
EN2340QI
Package and Mechanical
Figure 17: EN2340QI Package Dimensions (Bottom View)
Packing and Marking Information: www.altera.com/support/reliability/packing/rel-packing-and-marking.html
www.altera.com/enpirion, Page 22
06878
October 9, 2013
Rev E
EN2340QI
Contact Information
Altera Corporation
101 Innovation Drive
San Jose, CA 95134
Phone: 408-544-7000
www.altera.com
© 2013 Altera Corporation—Confidential. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX
words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor
products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without
notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in
writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for
products or services.
www.altera.com/enpirion, Page 23
06878
October 9, 2013
Rev E