RENESAS M61556FP

M61556FP
100 W 1-Channel Amplifier Predriver
REJ03F0089-0100Z
Rev.1.0
Sep.19.2003
Description
The M61556FP is a predriver IC developed for use as the output driver of a digital audio power amplifier. It can be
combined with an N-channel MOSFET to create a 100 W, 1-channel (8Ω load) digital amplifier. (The 200 W version,
the M61557FP, is pin compatible with the M61556FP.)
Features
• On-chip dead time adjustment circuit: Supports easy adjustment by connecting a single resistor. (H-L dead time can
be fine adjusted independently for sides A and B.)
• Suitable for driving full-bridge N-channel MOSFET devices.
• Maximum bootstrap supply voltage: 88 V (peak value)
• Supports high-speed switching.
• On-chip diode for bootstrap circuit.
• On-chip VDD low voltage detector circuit.
• On-chip clock loss detector circuit.
• Output impedance: 2.5 Ω
• Input is TTL level, allowing connecting to 3.3 V or 5 V processors.
Rev.1.0, Sep.19.2003, page 1 of 13
M61556FP
System Block Diagram (Stereo Configuration)
M61556FP
MCU
INA+
Dead time
generator
circuit
Signal processor
LSI for digital
amplifier
producing PWM
output
Dead time
constant
current
circuit
(Example)
M65817AFP
M65881AFP
INB+
Dead time
generator
circuit
CH1
CH2
M61556FP
Rev.1.0, Sep.19.2003, page 2 of 13
Level
shifter
VDD low
voltage
detector
Clock loss
detector
Level
shifter
Thermistor
detector
circuit
Protector
control
logic
Thermistor
External protection
detector
M61556FP
Sample Application Circuit
VDD = 12V
GND
PowerMOSFET:
LSGOUTA 42
1 NC
2 GNDA
NC 41
1µF
0.01µF
3 PAD5VA
VDDA 40
10Ω
4 NC
4.7µF
NC 39
5 INA+
HBA 38
7 VDDP
8 PROUT
0.01µF
9 FIL5V
10 NC
4.7µF
11 FILDT
0.01µF
12 IREFDT
6.2kΩ
13 GNDP
14 NC
HSGOUTA 37
10Ω
NC 36
OUTDA 35
DTCONTB1 34
THIN 33
NC 32
PROTECT 31
CH1
CH2
Signal processor LSI for digital amplifier
producing PWM output
16 GNDA
DTCONTA3
VDDA 27
HSGOUTB
10Ω
0.022uF
0.01µF
20 GNDB
21 NC
10uH
HBB 26
4.7µF
19 PAD5VB
PowerVDD:
Power
DD:
DTCONTB3 29
OUTDB 28
18 NC
External
Protect
Detector
DTCONTB2 30
15 DTCONTA2
17 INB+
Thermistor
PROUT
PR
(protection status monitor)
M61556FP
6 DTCONTA1
INB+
10uH
0.022µF
INA+
NC 25
VDDB 24
10Ω
1µF
NC 23
LSGOUTB 22
To other channels
Notes :
1. Refer to section 9.1, Dead Time Control, for information on the settings for pins 6, 15, 16, 29, 30, and 34.
2. Audio performance can be improved by connecting a snubber circuit to the output power FET.
Rev.1.0, Sep.19.2003, page 3 of 13
M61556FP
HBA
HSGOUTA
OUTDA
LSGOUTA
THIN
PROTECT
HBB
HSGOUTB
OUTDB
LSGOUTB
Block diagram
38
37
35 42
33
31
26
27
28
22
Level
shifter
Level
shifter
Level
shifter
Level
shifter
Thermistor
detector
circuit
Protector control
logic
VDD
low
voltage
detector
Dead time
generate circuit
Dead time
generate circuit
5
2
7
8
9
11 12
13 24
19
17
20
PAD5VA
INA+
GNDA
VDDP
PROUT
FIL5V
FILDT
GNDP
PAD5VB
INB+
GNDB
Rev.1.0, Sep.19.2003, page 4 of 13
VDDB
3
IREFDT
40
VDDA
IREF
M61556FP
Pin Descriptions
Pin No.
Side-A
control
(pre)
block
A/B
common
protectio
n block
Side-B
control
(pre)
block
Pin Name
Pin Description
2
GNDA
Ground pin for side-A control circuit
3
PADVA
Side-A filter pin for generating 5 V power supply on-chip
5
40
INA+
VDDA
Side-A PWM + input pin (high side)
Power supply pin for side-A control circuit
42
35
LSGOUTA
OUTDA
Side-A low side prebuffer output
Virtual VSS connector pin for side-A high side bootstrap capacitor
37
38
HSGOUTA
HBA
Side-A high side prebuffer output
Bootstrap capacitor connector pin power supply pin for side-A high side. Power is
supplied to the high side control circuit from a bootstrap circuit.
6
15
DTCONTA1
DTCONTA2
Pin 1 for adjusting dead time high/low differential
Pin 2 for adjusting dead time high/low differential
16
7
DTCONTA3
VDDP
Pin 3 for adjusting dead time high/low differential
Power supply pin for common circuit block
8
RPOUT
9
FIL5V
Protection factor detect output pin. A low-level signal (when pull-up is applied) is
output if protection factor is detected (open drain output).
Filter pin for generating 5 V power supply on-chip
11
12
FILDT
IREFDT
Filter pin for dead time circuit
Connector pin for dead time adjustment resistor
13
31
GNDP
PROTECT
Ground pin for common circuit block
Input pin for external protection control signals
33
17
THIN
INB+
Input pin for external thermistor circuit detect voltage
Side-B PWM + input pin (high side)
19
20
PAD5VB
GNDB
Side-B filter pin for generating 5 V power supply on-chip
Ground pin for side-B control circuit
26
HBB
27
HSGOUTB
Bootstrap capacitor connection pin power supply pin for side-B high side. Power is
supplied to the high side control circuit from a bootstrap circuit.
Side-B high side prebuffer output
28
22
OUTDB
LSGOUTB
Virtual VSS connector pin for side-B high side bootstrap capacitor
Side-B low side prebuffer output
24
34
VDDB
DTCONTB1
Power supply pin for side-B control circuit
Pin 1 for adjusting dead time high/low differential
30
29
DTCONTB2
DTCONTB3
Pin 2 for adjusting dead time high/low differential
Pin 3 for adjusting dead time high/low differential
Absolute Maximum Ratings
Parameter
Symbol
Ratings
Units
Conditions
HBA, HBB
HBA, HBB
88*
V
HBA and HBB pin voltage
VDD power supply voltage
Maximum rated operating voltage
Absolute maximum rated voltage
VDD
16
V
Input pin application voltage
Internal power consumption
Vin
Pd
−0.3 to 5.5
1.1
V
W
Junction temperature
Operating temperature range
Tj
Ta
150
−20 to +75
°C
°C
Storage temperature
Tstg
−40 to +125
°C
Note : * HB pin values include peak values for ringing voltage, etc.
Rev.1.0, Sep.19.2003, page 5 of 13
M61556FP
Derating Curve
Power Dissipation Pd (W)
2.0
1.5
1.1
1.0
0.65
0.5
0
0
25
50
75
100
125
150
Ambient temperature Ta (˚C)
Recommended Operating Condition
Rated value
Item
Symbol
Min.
Typ.
Max.
Unit
Condition
Power supply voltage for
common circuit and control
circuit blocks
VDD
10.8
12
13.2
V
VDDA (pin 40), VDDB (pin 24)
High input voltage
Low input voltage
VIH
VIL
VDDP (pin 7)
Rev.1.0, Sep.19.2003, page 6 of 13
2.2
−0.25


5.3
0.8
V
V
INA+ (pin 5), INB+ (pin 17)
M61556FP
Electrical characteristics
(Unless otherwise specified, Ta = 25°C, VDDP, VDDA, B = 12 V, VDA, B = 21 V)
Limits
Item
Symbol
Min.
Typ.
Max.
Unit
Measuring Conditions
Circuit current
VDD circuit current
IDD (A, B)

5
TBD
mA
No input
IDDF (A, B)

30
TBD
mA
IDDP

5
TBD
mA
During operation (f = 768 kHz, duty =
50%)
No input
VIH
VIL
2.2




0.8
V
V
VDDR
VDDH
TBD
TBD
7
0.5
TBD
TBD
V
V
Between VDD and GND
Detection → Recovery
THR
TBD
6.0
TBD
V
THIN pin (pin 33)
THH
TBD
4.8
TBD
V
Detection → Recovery
Diode forward voltage
Diode forward voltage
VFL
VFH


1.5
2.0
TBD
TBD
V
V
HB output current = 100µA
HB output current = 100mA
Diode operating resistance
RDON

1.2
TBD
Ω
HB output current = 100mA
Low side gain driver
High input voltage
VOLL

0.25
0.3
V
ILO = 100mA
Low input voltage
Pull-up output current
VOHL
IOHL


0.25
2
0.3

V
A
ILO = −100mA, VOHL = VDD−VHO
VLO = 0V
Pull-down output current
IOLL

2

A
VLO = 12V
High side gain driver
High input voltage
VOLH

0.25
0.3
V
IHO = 100mA
Low input voltage
Pull-up output current
VOHH
IOHH


0.25
2
0.3

V
A
IHO = −100mA, VOHH = VHB−VHO
VHO = 0V
Pull-down output current
IOLH

2

A
VHO = 12V
Switching characteristics
Output rise time
trc

TBD

ns
f = 500KHz, CL = 1000pF
Output fall time
Output rise time (3 V to 9 V)
tfc
tr


TBD
TBD

TBD
ns
µs
f = 500KHz, CL = 1000pF
f = 50KHz, CL = 0.1µF
Output fall time (9 V to 3 V)
Operation input frequency
tf
1/tpf

TBD
TBD
768
TBD
TBD
µs
KHz
f = 50KHz, CL = 0.1µF
Minimum input pulse width
tpw
40


ns
Cycle = 1.3 µs (f = 768 kHz)
Input voltage
High input voltage
Low input voltage
Low voltage detection
VDD low voltage detect level
VDD detect hysteresis
voltage
Thermistor voltage detection
Thermistor voltage detect
level
Thermistor detect hysteresis
voltage
Bootstrap diode
Rev.1.0, Sep.19.2003, page 7 of 13
M61556FP
I/O Timing
tpf
tpw
INA+,INB+
Td
Td
Dead time
Dead time
HSGOUTA /B
LSGOUTA/B
Dead Time
To prevent the M61556FP from being destroyed by the shoot-through current from an external MOSFET device, dead
time is provided between HSGOUTA and LSGOUTA as well as between HSGOUTB and LSGOUTB. Refer to the
Dead Time Control section below for information on adjusting the dead time.
Function
Signal System
1. Dead Time Control Settings
The dead time, which protects the M61556FP from being destroyed by the shoot-through current from an external
MOSFET device, can be adjusted as desired by the user by adjusting the external resistor (R) connected to pin 12.
It is possible to adjust the dead times of the high and low sides by setting the dead time control pins of side-A and sideB to 0 V or 12 V. This makes it easy to tailor the dead time to account for minute variations due to circuit board layout
and to match the characteristics of the connected MOSFET devices.
Relationship Between Pin 12 Resistor, Dead Time Setting, and Output Shoot-Through Current
Pin 12 Resistance Value
Dead time setting
Small
Short
Output stage shoot-through current
Large shoot-through current
Note: Dead time values are averages for the high and low sides.
Rev.1.0, Sep.19.2003, page 8 of 13
← →
← →
Large
Long
← →
Small shoot-through current
M61556FP
Dead Time Control Pin and High/Low Dead Time Balance
DTCONT*1
DTCONT*2
DTCONT*3
12V
0V
0V
12V
0V
12V
12V
12V
12V
12V
0V
12V
0V
0V
0V
0V
0V
12V
0V
0V
12V
12V
0V
12V
High Side Dead Time
Low Side Dead Time
Long
Short
(INIT)
(INIT)
INIT
INIT
Short
Long
Note: The sums of the dead times for the high and low sides produced by the above adjustments are constant.
DTCONT Pin No. list
Side-A
Side-B
DTCONT*1
Pin 6
Pin 34
DTCONT*2
Pin 15
Pin 30
DTCONT*3
Pin 16
Pin 29
(“INIT” refers to the initial status with no setting made by the user.)
Protection System
2. VDD Low Voltage Detector Circuit
In order to prevent internal malfunctioning caused by abnormally low power supply voltage, the M61556FP is
equipped with a VDD low voltage detector circuit that is triggered if a drop occurs on the VDD power supply voltage.
When abnormally low voltage is detected, a low-level signal is output to the HSGOUTA and HSGOUTB pins and a
high-level signal to the LSGOUTA and LSGOUTB pins, the Nch totem pole output is kept low, and a low-level signal,
indicating a malfunction, is output to PROUT. (The VDD output circuit is connected to the common power supply
VDDP pin (pin 7), so for VDDA and VDDB (pins 24 and 40) an external connection should be made to VDDP.)
3. Clock Loss Detector Circuit
The major operation performed by the M61556FP is the input and output of PWM pulse waveforms, so protection is
provided to ensure stable bootstrap operation in cases where no signal is input for a set period of time. In the protected
state, a low-level signal is output to the HSGOUTA, HSGOUTB, LSGOUTA, and LSGOUTB pins, the high and low
sides of the external Nch MOS FET are both turned off, and a low-level signal, indicating a malfunction, is output to
PROUT.
4. External Protection Detect Signal Input Pin (PROTECT)*
Pin 31 of the M61556FP is the external protection detect signal input pin (PROTECT). If a low-level signal is to pin 31,
the on-chip logic circuitry causes a low-level signal to be output to the HSGOUTA, HSGOUTB, LSGOUTA, and
LSGOUTB pins, the high and low sides of the external Nch MOS FET to both turn off, and a low-level signal,
indicating under protection, to be output to PROUT.
5. External Thermistor Circuit Detect Voltage Input Pin (THIN)
Pin 33 of the M61556FP is the external thermistor circuit detect voltage input pin (THIN). If the pin 33 voltage
becomes one-half VDD or higher, through resistance division by the external thermistor and resistor, the on-chip logic
circuitry causes a low-level signal to be output to the HSGOUTA, HSGOUTB, LSGOUTA, and LSGOUTB pins, the
high and low sides of the external Nch MOS FET to both turn off, and a low-level signal, indicating a malfunction, to
be output to PROUT.
Rev.1.0, Sep.19.2003, page 9 of 13
M61556FP
Overheating Detection Function Diagram
VDD
1/ 2VDD
2/ 5VDD
THIN pin voltage
(pin 33)
Hys=1.2V
(VDD = 12V)
Thermistor
33
Protection detect output
PROUT (pin 8)
THIN
INA+
or INB+
GND
Signal output resumes
after rising edge detected
Signal output
pin control
Normal
operation
Normal
operation
Function when
malfunction
detected
Note: The threshold voltage and hysteresis width are the current setting values, and they can be changed.
Functions When Protection Detection Occurs
When protection detection occurs, a low-level signal is output to the HSGOUTA, HSGOUTB, LSGOUTA, and
LSGOUTB pins, asynchronously to the PWM inputs (INA+, INA–, INB+, INB–), the high and low sides of the
external Nch MOS FET are both turned off, and a low-level signal, indicating a malfunction, is output to PROUT. The
PROUT output and signal output pins states when a malfunction is detected are listed in the table below.
Table of Signal Output Pin States During Protection Operation
PROUT output
when malfunction
detected
PROTECT
input pin
HSGOUTA/B
LSGOUTA/B
Power transistor
output status
L

L
H
L
VDD low voltage
protection
Clock loss detection
L

L
L
Hi-Z
External protection
Thermistor
L
L
L (*)

L
L
L
L
Hi-Z
Hi-Z
Recovery from Protection Detection Status
The manner in which recovery to signal output from protection detection status takes place varies depending on the
protection circuit involved. Once the recovery conditions have been met, recovery takes place at the rising edge of
INA+ or INB+ to high level, whichever is first. The recovery conditions for the different protection functions are listed
in the table below.
Rev.1.0, Sep.19.2003, page 10 of 13
M61556FP
Necessary Conditions for Recovery from Protection Detection Status
Recovery Conditions
External protection*
PROTECT pin low: protection status, high: normal operation
Recovery: After a rising edge from low to high is input to the PROTECT pin, normal
operation resumes at the rising edge of the first signal. If a low-level signal is input to the
PROTECT pin, the M61556FP is forced into protected status, regardless of the other
modes.
Thermistor
After the overheating condition has been corrected and the THIN pin voltage drops to
(1/2 VDD – 1.5) V, recovery to normal operation takes place at the rising edge of INA+
or INB+ to high level, whichever is first.
VDD low voltage detector
After the low voltage condition has been corrected and the on-chip VDD detect circuit
determines that the voltage is normal, recovery to normal operation takes place at the
rising edge of INA+ or INB+ to high level, whichever is first.
After the abnormal input condition has been corrected and the on-chip abnormal input
detect circuit determines that the input is normal, recovery to normal operation takes
place at the rising edge of INA+ or INB+ to high level, whichever is first.
Clock loss detector
* Note that the high and low settings are the reverse of those in the old specifications.
External Protection Detect Signal Input Pin PROTECT (Pin 31)/Protection Detect Output
PROUT (Pin 9) Timing Diagram
Malfunction identified (external protection)
Recovery from external protection (rising edge of PROTECT)
External protection
detect signal input pin
PROTECT (Pin 31)
Should be 1 µsec. or more
Protection detect output
PROUT (pin 8)
INA+
or INB+
Signal output recovery after
rising edge detection
Signal output pin control
Normal
operation
Normal
operation
Function when malfunction
detected
The above diagram shows the timing from the start of external protection control through recovery from protection
status. With the other protection functions, recovery from protected status also occurs when the leading edge is detected,
as in the diagram above.
Functions at Power-On
To prevent control malfunctions when the M61556FP is powered on, the logic circuitry determines when VDD has
risen to approximately 1.5 V or higher and then outputs a low-level signal to HSGOUTA and HSGOUTB, outputs a
high-level signal to LSGOUTA and LSGOUTB, and switches the Nch totem pole output to low-level. This charges the
external bootstrap capacitor and ensures stable bootstrap operation.
Rev.1.0, Sep.19.2003, page 11 of 13
M61556FP
Power-On Function Diagram
VDD
1.5V
High side
HSGOUTA, HSGOUTB (Undefined)
(OFF)
Low side
LSGOUTA, LSGOUTB
(Undefined)
(ON)
Totem pole output
OUTDA, OUTDB
Undefined
"L"
Items in parentheses ( ) indicate the
output Nch MOS FET state.
Rev.1.0, Sep.19.2003, page 12 of 13
HE
G
Z1
e
1
42
z
Detail G
D
y
JEDEC Code
—
MMP
b
Weight(g)
0.63
21
22
Lead Material
Alloy 42/Cu Alloy
L1
EIAJ Package Code
SSOP42-P-450-0.80
E
Rev.1.0, Sep.19.2003, page 13 of 13
Detail F
A2
A
A1
F
c
L
A
A1
A2
b
c
D
E
e
HE
L
L1
z
Z1
y
Symbol
e1
b2
e1
I2
b2
Dimension in Millimeters
Min
Nom
Max
2.4
—
—
—
—
0.05
—
2.0
—
0.5
0.4
0.35
0.2
0.15
0.13
17.7
17.5
17.3
8.6
8.4
8.2
—
0.8
—
12.23
11.93
11.63
0.7
0.5
0.3
—
1.765
—
—
—
0.75
—
0.9
—
0.15
—
—
0˚
—
10˚
—
0.5
—
—
11.43
—
—
1.27
—
Recommended Mount Pad
e
Plastic 42pin 450mil SSOP
I2
42P2R-A
M61556FP
Package Dimensions
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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