SM72295 Photovoltaic Full Bridge Driver General Description Features The SM72295 is designed to drive 4 discrete N type MOSFET’s in a full bridge configuration. The drivers provide 3A of peak current for fast efficient switching and integrated high speed bootstrap diodes. Current sensing is provided by 2 transconductance amplifiers with externally programmable gain and filtering to remove ripple current to provide average current information to the control circuit. The current sense amplifiers have buffered outputs available to provide a low impedance interface to an A/D converter if needed. An externally programmable input over voltage comparator is also included to shutdown all outputs. Under voltage lockout with a PGOOD indicator prevents the drivers from operating if VCC is too low. ■ ■ ■ ■ ■ ■ Renewable Energy Grade Dual Half Bridge MOSFET Drivers Integrated 100V bootstrap diodes Independent High and Low driver logic inputs Bootstrap supply voltage range up to 115V DC Two current sense amplifiers with externally programmable gain and buffered outputs ■ Programmable over voltage protection ■ Supply rail under-voltage lockouts with power good indicator Package ■ SOIC-28 Typical Application Circuit 30134101 © 2011 National Semiconductor Corporation 301341 www.national.com SM72295 Photovoltaic Full Bridge Driver February 25, 2011 SM72295 Connection Diagram 30134116 Top View SOIC-28 Ordering Information Order Number Description NSC Package Drawing Supplied As SM72295X 28L SOIC WIDE M28B 1000 Units in Tape and Reel SM72295E 28L SOIC WIDE M28B 250 Units in Tape and Reel www.national.com 2 SM72295 Pin Descriptions Pin Name Description Application Information 5 AGND Analog ground Ground return for the analog circuitry. Tie to the ground plane under the IC 23 PGND Power ground return Ground return for the LO drivers. Tie to the ground plane under the IC 21,25 VCCA, VCCB Positive gate drive supply Locally decouple to PGND using low ESR/ESL capacitor located as close to IC as possible. 26,20 HBA, HBB High side gate driver bootstrap rail. Connect the positive terminal of the bootstrap capacitor to HB and the negative terminal to HS. The bootstrap capacitor should be placed as close to IC as possible. 27, 19 HOA, HOB High side gate driver output Connect to gate of high side MOSFET with a short low inductance path. 28, 18 HSA, HSB High side MOSFET source connection Connect to bootstrap capacitor negative terminal and the source of the high side MOSFET. 7, 8 HIA, HIB High side driver control input The inputs have TTL type thresholds. Unused inputs should be tied to ground and not left open. 6, 9 LIA, LIB Low side driver control input The inputs have TTL type thresholds. Unused inputs should be tied to ground and not left open. 24, 22 LOA, LOB Low side gate driver output Connect to the gate of the low side MOSFET with a short low inductance path. VDD 3.3V or 5V regulator output Bypass with 0.1uF. Reference for over voltage shutdown and IOUT/IIN clamp 17 10 PGOOD Power good indicator output Open drain output with an internal pull-up resistor to VDD indicating VCC is in regulation. PGOOD low implies VCC is out of regulation. 15 OVP Over voltage indicator output Open drain output with an internal pull-up resistor to VDD indicating OVS >VDD. OVP is low when OVS>VDD. 11 BOUT 4 BIN Buffered IOUT Buffered IOUT. Buffered IIN 1 SIA Sense high input for input current Tie to positive side of the current sense resistor through an external gain sense transconductance amplifier programming resistor (RI). Amplifier transconductance is 1/RI. Buffered IIN. 2 S0A Sense low input for input current Tie to negative side of the current sense resistor through an external gain sense transconductance amplifier programming resistor. Amplifier transconductance is 1/RI. 3 IIN Output for current sense transconductance amplifier 14 SIB Sense high input for output current Tie to positive side of the current sense resistor through an external gain sense amplifier programming resistor (RI). Amplifier transconductance is 1/RI. 13 S0B Sense low input for output current Tie to negative side of the current sense resistor through an external gain sense amplifier programming resistor. Amplifier transconductance is 1/RI. 12 IOUT Output for current sense comparator. Output of the output current sense amplifier. Requires an external resistor to ground (RL). Gain is RL/RI, where RI is the external resistor in series with the SIB pin. 16 OVS Sense input for over voltage Requires an external resistor divider. VDD is the reference voltage. Output of the input current sense amplifier. Requires an external resistor to ground (RL). Gain is RL/RI, where RI is the external resistor in series with the SIA pin. 3 www.national.com SM72295 BIN, BOUT Junction Temperature Storage Temperatue Range ESD Rating Human Body Model Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. VCCA, VCCB VDD HBA to HSA, HBB to HSB LIA,LIB,HIA,HIB,OVS LOA,LOB HOA,HOB SIA,SOA,SIB,SOB SIA to SOA, SIB to SOB HSA,HSB (note 5) HBA, HBB PGOOD, OVP IIN, IOUT -0.3 to 14V -0.3 to 7V -0.3 to 15V -0.3 to 7V -0.3 to VCC+ 0.3V HS–0.3 to HB + 0.3V -0.3 to 100V -0.8 to 0.8V -5 to 100V 115V -0.3 to VDD -0.3 to VDD -0.3 to VDD 150°C -55°C to +150°C 2 kV Recommended Operating Conditions VCCA,VCCB VDD SI, SO common mode HS (Note 5) HBA, HBB HS Slew Rate Junction Temperature +8V to +14V +3V to 7V VDD+1V to 100V -1V to 100V HS+7V to HS+14V <50V/ns -40°C to +125°C Electrical Characteristics Specifications in standard typeface are for TJ = 25°C, and those in boldface type apply over the full operating junction temperature range. No load on LO & HO, VCC = 10V, VDD = 5V, HB-HS = 10V, OVS = 0V unless otherwise indicated. Symbol Parameter Conditions Min Typ Max Units SUPPLY CURRENTS IDD VDD Quiescent Current SIA = SOB, SIB = SOB. 25 40 μA ICC VCC Quiescent Current (ICCA+ICCB) All outputs off 500 800 μA ICCO VCC Operating Current (ICCA+ICCB) LOA & LOB switching at 200kHz 2.2 3 mA IHB HBA, HBB Quiescent Current All outputs off 55 200 μA IHBO HBA, HBB Operating Current HOA & HOB switching at 200kHz 700 1000 μA IHBS HBA & HBB to VSS Current, Quiescent HS = 100V, HB = 110V 0.1 10 μA IHBSO HBA and HBB to VSS Current, f = 200kHz Operating μA 130 PGOOD, OVB OUTPUTs VOL Output Low RDS 25 50 Ω RPU VDD pull up resistor 50 90 kΩ 1.8 2.3 LI ,HI INPUT PINS VIL Input Voltage Threshold VIHYS Input Voltage Hysteresis RI LI, HI Pull down Resistance 1.3 50 V mV 100 200 400 kΩ VDD-50mV VDD VDD +50mV V OVER VOLTAGE SHUTDOWN VOVR OVS Rising Threshold VOVH OVS threshold Hysteresis IOVS OVS input bias current OVS<VDD 5% VDD 1 nA UNDER VOLTAGE SHUTDOWN VCCR VCC Rising Threshold VCCH VCC threshold Hysteresis VHBR HB-HS Rising Threshold VHBH HB-HS Threshold Hysteresis 6 6.9 7.4 0.5 5.7 6.6 V V 7.1 0.4 V V BOOT STRAP DIODE VDH High-Current Forward Voltage IVCC-HB = 100mA RD Dynamic Resistance www.national.com IVCC-HB = 100mA 4 0.8 1 V 1 1.65 Ω Parameter Conditions Min Typ Max Units LO & HO GATE DRIVER VOL Low-Level Output Voltage ILO = 100mA VOL = LO-PGND or HO-HS 0.16 0.4 V VOH High-Level Output Voltage ILO = -100mA VOH = VCC-LO or VCC-HO 0.28 0.6 V IOHL Peak Pullup Current HO, LO = 12V IOLL Peak Pulldown Current HO, LO = 0V 3 A tLPHL LO Turn-Off Propagation Delay LI Falling to LO Falling 22 ns tLPLH LO Turn-On Propagation Delay LI Rising to LO Rising 26 ns tHPHL HO Turn-Off Propagation Delay 22 ns tHPLH LO Turn-On Propagation Delay HI Rising to HO Rising 26 ns tMON Delay Matching: LO on & HO off 1 ns tMOFF Delay Matching: LO off & HO on 1 ns tRC, tFC Either Output Rise/Fall Time 8 ns tPW Minimum Input Pulse Width that Changes the Output 50 ns tBS Bootstrap Diode Turn-On or Turn-Off Time 37 ns 3 HI Falling to HO Falling CL = 1000pF IF = 100mA/ IR = 100mA A CURRENT SENSE AMPLIFIER VOS Offset voltage RSI = RSO = 500, 10mV sense resistor voltage -2 Gain is programmed with 5mV sense resistor voltage Gain 5mV external resistors RSI = RSO = 1000, RL = 75K IOUT, IIN =(RL/RSI )* (SI-SO) Gain 50mV Gain is programmed with 50mV sense resistor voltage external resistors RSI = RSO = 1000, RL = 75K IOUT, IIN =(RL/RSI )* (SI-SO) Vclamp Output Clamp 0.1V sense resistor voltage RSI = RSO = 1000, RL = 75K 2 mV 390 mV 3.85 V VDD V CURRENT SENSE BUFFER Offset voltage (BIN-IIN), (BOUT-IOUT) IIN = 2.5V -60 Output low voltage BOUT,BIN IIN, IOUT = 0 0 Output high voltage BOUT,BIN IIN, IOUT = VDD VDD-100mV VDD-30mV 60 mV 50 mV VDD mV THERMAL RESISTANCE θJA Junction to Ambient SOIC-28 (Note 3) 60 °C/W Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical Characteristics tables. Note 2: The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. 2 kV for all pins except HB, HO & HS which are rated at 1000V. Note 3: 2 layer board with 2 oz Cu using JEDEC JESD51 thermal board. Note 4: Min and Max limits are 100% production tested at 25ºC. Limits over the operating temperature range are guaranteed through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate National’s Average Outgoing Quality Level (AOQL). Note 5: In the application the HS nodes are clamped by the body diode of the external lower N-MOSFET, therefore the HS node will generally not exceed –1V. However, in some applications, board resistance and inductance may result in the HS node exceeding this stated voltage transiently. If negative transients occur, the HS voltage must never be more negative than VCC-15V. For example if VCC = 10V, the negative transients at HS must not exceed –5V. 5 www.national.com SM72295 Symbol SM72295 Block Diagram 30134102 FIGURE 1. Block Diagram www.national.com 6 Operating Current vs Temperature VCC Undervoltage Rising Threshold vs Temperature 30134111 30134113 VCC Quiescent Current vs Temperature VCC Undervoltage Threshold Hysteresis vs Temperature 30134112 30134114 VDD Quiescent Current vs Temperature Gate Drive High Level Output Voltage vs Temperature 30134115 30134109 7 www.national.com SM72295 Typical Performance Characteristics SM72295 Gate Drive Low level Output Voltage vs Temperature Bootstrap Diode Forward Voltage vs Temperature 30134110 30134106 Current Sense Amplifier Input Offset Voltage vs Temperature Current Sense Amplifier Output Buffer Offset Voltage vs Temperature 30134107 30134108 Timing Diagram 30134103 FIGURE 2. www.national.com 8 SM72295 Diode Power Dissipation VIN = 50V Power Dissipation Considerations The total IC power dissipation is the sum of the gate driver losses and the bootstrap diode losses. The gate driver losses are related to the switching frequency (f), output load capacitance on LO and HO (CL), and supply voltage (VDD) and can be roughly calculated as: PDGATES = 2 • f • CL • VDD2 There are some additional losses in the gate drivers due to the internal CMOS stages used to buffer the LO and HO outputs. The following plot shows the measured gate driver power dissipation versus frequency and load capacitance. At higher frequencies and load capacitance values, the power dissipation is dominated by the power losses driving the output loads and agrees well with the above equation. This plot can be used to approximate the power losses due to the gate drivers. 30134105 Gate Driver Power Dissipation (LO + HO) VCC = 12V, Neglecting Diode Losses Layout Considerations The optimum performance of high and low-side gate drivers cannot be achieved without taking due considerations during circuit board layout. Following points are emphasized. 1. Low ESR / ESL capacitors must be connected close to the IC, between VDD and VSS pins and between the HB and HS pins to support the high peak currents being drawn from VDD during turn-on of the external MOSFET. 2. To prevent large voltage transients at the drain of the top MOSFET, a low ESR electrolytic capacitor must be connected between MOSFET drain and ground (VSS). 3. In order to avoid large negative transients on the switch node (HS pin), the parasitic inductances in the source of top MOSFET and in the drain of the bottom MOSFET (synchronous rectifier) must be minimized. 4. Grounding Considerations: a. The first priority in designing grounding connections is to confine the high peak currents that charge and discharge the MOSFET gate into a minimal physical area. This will decrease the loop inductance and minimize noise issues on the gate terminal of the MOSFET. The MOSFETs should be placed as close as possible to the gate driver. b. The second high current path includes the bootstrap capacitor, the bootstrap diode, the local ground referenced bypass capacitor and low-side MOSFET body diode. The bootstrap capacitor is recharged on a cycle-by-cycle basis through the bootstrap diode from the ground referenced VDD bypass capacitor. The recharging occurs in a short time interval and involves high peak current. Minimizing this loop length and area on the circuit board is important to ensure reliable operation. 30134104 The bootstrap diode power loss is the sum of the forward bias power loss that occurs while charging the bootstrap capacitor and the reverse bias power loss that occurs during reverse recovery. Since each of these events happens once per cycle, the diode power loss is proportional to frequency. Larger capacitive loads require more current to recharge the bootstrap capacitor resulting in more losses. Higher input voltages (VIN) to the half bridge result in higher reverse recovery losses. The following plot was generated based on calculations and lab measurements of the diode recovery time and current under several operating conditions. This can be useful for approximating the diode power dissipation. The total IC power dissipation can be estimated from the previous plots by summing the gate drive losses with the bootstrap diode losses for the intended application. 9 www.national.com SM72295 Physical Dimensions 30134150 NS Package Drawing M28B www.national.com 10 SM72295 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead TSSOP Package NS Package Number MXA20A 11 www.national.com SM72295 Photovoltaic Full Bridge Driver Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: www.national.com Products Design Support Amplifiers www.national.com/amplifiers WEBENCH® Tools www.national.com/webench Audio www.national.com/audio App Notes www.national.com/appnotes Clock and Timing www.national.com/timing Reference Designs www.national.com/refdesigns Data Converters www.national.com/adc Samples www.national.com/samples Interface www.national.com/interface Eval Boards www.national.com/evalboards LVDS www.national.com/lvds Packaging www.national.com/packaging Power Management www.national.com/power Green Compliance www.national.com/quality/green Switching Regulators www.national.com/switchers Distributors www.national.com/contacts LDOs www.national.com/ldo Quality and Reliability www.national.com/quality LED Lighting www.national.com/led Feedback/Support www.national.com/feedback Voltage References www.national.com/vref Design Made Easy www.national.com/easy www.national.com/powerwise Applications & Markets www.national.com/solutions Mil/Aero www.national.com/milaero PowerWise® Solutions Serial Digital Interface (SDI) www.national.com/sdi Temperature Sensors www.national.com/tempsensors SolarMagic™ www.national.com/solarmagic PLL/VCO www.national.com/wireless www.national.com/training PowerWise® Design University THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. 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