size：0.3MB - Torex Semiconductor

XC6119 Series
ETR02016-003
Voltage Detector with Delay Time Adjustable
■GENERAL DESCRIPTION
The XC6119 series is a highly precise, low power consumption voltage detector, manufactured using CMOS and laser trimming
technologies.
The device includes the built-in delay circuit. A release delay time can be set freely by connecting an external delay capacitor to
the Cd pin.
The device using an ultra small package (USPN-4) is suited for high density mounting applications.
Both CMOS and N-channel open drain output configurations are available.
■APPLICATIONS
■FEATURES
●Microprocessor reset circuitry
High Accuracy
: +2%
(Detection Voltage >1.5V)
●Charge voltage monitors
+30mV
●Memory battery back-up switch circuits
●Power failure detection circuits
(Detection Voltage <1.5V)
Low Power Consumption
: 0.5μA TYP. in detect state
(VDF=1.0V, VIN= 0.9V)
0.9μA TYP. in release state
(VDF=1.0V, VIN= 1.1V)
Detect Voltage Options
: 0.8V ~ 5.0V (0.1V increments)
Operating Voltage Range
: 0.7V ~ 6.0V
Detect Voltage Temperature Characteristics
: ±100ppm/ OC TYP.
Output Configuration
: CMOS or
Built-In Delay Circuit
: Delay Time Adjustable
Operating Ambient Temperature
: -40 OC ~ +85 OC
Packages
Environmentally Friendly
: SSOT-24, USPN-4
: EU RoHS Compliant, Pb Free
N-channel open drain
■TYPICAL APPLICATION CIRCUIT ■TYPICAL PERFORMANCE
CHARACTERISTICS
●Release Delay Time vs. Delay Capacitance
(No Pull-Up resistor needed
for CMOS output product)
Release Delay Time: t DR (ms)
XC6119xxxAx
VIN(min)=0.7V VIN(max)=6.0V
tr=5μs Ta=25℃
10000
1000
100
10
1
0.1
0.0001
0.001
0.01
0.1
1
Delay Capacitance: Cd (μF)
1/16
XC6119 Series
■PIN CONFIGURATION
USPN-4
(BOTTOM VIEW)
SSOT-24
（TOP VIEW）
■PIN ASSIGNMENT
PIN NUMBER
PIN NAME
FUNCTION
USPN-4
SSOT-24
1
4
VOUT
Output (Detect ”L”)
2
3
Cd
Delay Capacitance
3
2
VSS
Ground
4
1
VIN
Input
■PRODUCT CLASSIFICATION
●Ordering Information
XC6119①②③④⑤⑥-⑦(*1)
(*1)
2/16
DESIGNATOR
ITEM
SYMBOL
①
Output Configuration
②③
Detect Voltage
08 ~ 50
④
Output Delay &
Hysteresis
A
⑤⑥-⑦
Packages
(Order Unit)
DESCRIPTION
C
CMOS output
N
N-ch open drain output
e.g. 18→1.8V
Built-in delay pin & hysteresis 5% (TYP.)
7R-G
USPN-4 (5,000/Reel)
NR-G
SSOT-24 (3,000/Reel)
The “-G” suffix denotes Halogen and Antimony free as well as being fully RoHS compliant.
XC6119
Series
■BLOCK DIAGRAMS
(1) XC6119C (CMOS Output)
(2) XC6119N (N-ch Open Drain Output)
* Diodes inside the circuits are ESD protection diodes and parasitic diodes.
■ABSOLUTE MAXIMUM RATINGS
Ta=25℃
PARAMETER
Output
Voltage
Power
Dissipation
Input Voltage
Output Current
XC6119C (*1)
XC6119N (*2)
Delay Pin Voltage
Delay Pin Current
USPN-4 *
SSOT-24
Operating Ambient Temperature
Storage Temperature
SYMBOL
VIN
IOUT
VOUT
VCD
ICD
Pd
Ta
Tstg
RATINGS
VSS-0.3～+7.0
10
VSS-0.3～VIN+0.3
VSS-0.3～+7.0
VSS-0.3～VIN+0.3
5.0
100
150
-40～+85
-55～+125
UNITS
V
mA
V
V
mA
mW
o
o
C
C
NOTE:
*1: CMOS output
*2: N-ch open drain output
3/16
XC6119 Series
■ELECTRICAL CHARACTERISTICS
Ta=25℃
PARAMETER
SYMBOL
CONDITIONS
MIN.
Operating Voltage
VIN
VDF(T)=0.8～5.0V (*1)
0.7
Detect Voltage
VDF
VDF(T)=0.8～5.0V
Hysteresis Width
VHYS
Supply Current 1
ISS1
Supply Current 2
ISS2
IOUT1
Output Current
CMOS output
(P-ch)
N-ch Open
Drain Output
Temperature
Characteristics
Delay Resistance (*7)
Delay Pin Sink Current
Delay Capacitance Pin
Threshold Voltage
Unspecified Operating
Voltage (*8)
VIN=VDF×0.9
VDF(T)=0.8～1.9V
VDF(T)=2.0～3.9V
VDF(T)=4.0～5.0V
VIN=VDF×1.1
VDF(T)=0.8～1.9V
VDF(T)=2.0～3.9V
VDF(T)=4.0～5.0V
VIN=0.7V
VDS=0.5V(Nch)
VIN=1.0V(※2)
VDS=0.5V(Nch)
VIN=2.0V(※3)
VDS=0.5V(Nch)
VIN=3.0V(※4)
VDS=0.5V(Nch)
VIN=4.0V(※5)
VDS=0.5V(Nch)
(*6)
VIN=VDF×1.1
VDS=0.5V(Pch)
ILEAK
VIN = VDF×0.9V, VOUT = 0V,
Cd: Open
VIN = 6.0V, VOUT = 6.0V,
Cd: Open
IOUT2
Leakage
Current
VIN=1.0～6.0V
ΔVDF/
(ΔTa・
VDF)
RDELAY
ICD
VTCD
VUNS
Detect Delay Time (*9)
tDF0
Detect Delay Time (*9)
tDR0
VDF
×0.02
VIN=0～0.7V
VIN=6.0→0.7V
Cd: Open
VIN=0.7V→6.0V
Cd: Open
MAX.
UNIT
CIRCUIT
6.0
V
-
V
①
V
①
μA
②
μA
②
mA
③
mA
④
μA
③
ppm/o
C
①
MΩ
μA
⑤
⑤
E-1
VDF
×0.05
VDF
×0.08
0.5
0.6
0.7
1.2
1.3
1.4
0.9
1.1
1.2
1.8
2.0
2.2
0.01
0.36
0.1
0.7
0.8
1.6
1.2
2.0
1.6
2.3
E-2
-0.20
0.20
o
o
-40 C≦Ta≦85 C
VIN=6.0V, Cd=0V
Cd=0.5V, VIN=0.7V
VIN=1.0V
VIN=6.0V
TYP.
0.40
±100
1.6
8
0.4
2.9
2.0
60
0.5
3.0
2.4
0.6
3.1
V
⑥
0.3
0.4
V
⑦
30
230
μs
⑧
30
200
μs
⑧
NOTE:
*1: VDF(T): Setting Detect Voltage
*2: VDF(T)＞1.0V
*3: VDF(T)＞2.0V
*4: VDF(T)＞3.0V
*5: VDF(T)＞4.0V
*6: This numerical value is applied only to the XC6119C series (CMOS output).
*7: Calculated from the voltage value and the current value of both ends of the resistor.
*8: The maximum voltage of the VOUT in the range of the VIN 0 to 0.7V. This numerical value is applied only to the XC6119C series
(CMOS output).
*9: Time which ranges from the state of VIN =VDF to the VOUT reaching 0.6V when the VIN falls without connecting to the Cd pin.
*10: Time which ranges from the state of VIN= VDF +VHYS to the VOUT reaching 5.4V when the VIN rises without connecting to the Cd
pin.
4/16
XC6119
Series
■VOLTAGE CHART
SYMBOL
PARAMETER
SETTING
DETECT
VOLTAGE
VDF(T)
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
4.0
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
5.0
E-1
E-2
DETECT VOLTAGE (*1)
(V)
OUTPUT CURRENT (*2)
(mA)
MIN.
VDF
TYP.
MAX.
IOUT2
0.770
0.870
0.970
1.070
1.170
1.270
1.370
1.470
1.568
1.666
1.764
1.862
1.960
2.058
2.156
2.254
2.352
2.450
2.548
2.646
2.744
2.842
2.940
3.038
3.136
3.234
3.332
3.430
3.528
3.626
3.724
3.822
3.920
4.018
4.116
4.214
4.321
4.410
4.508
4.606
4.704
4.802
4.900
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
4.0
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
5.0
0.830
0.930
1.030
1.130
1.230
1.330
1.430
1.530
1.632
1.734
1.836
1.938
2.040
2.142
2.244
2.346
2.448
2.550
2.652
2.754
2.856
2.958
3.060
3.162
3.264
3.366
3.468
3.570
3.672
3.774
3.876
3.978
4.080
4.182
4.284
4.386
4.488
4.590
4.692
4.794
4.896
4.998
5.100
MIN.
TYP.
-0.40
-0.20
-0.60
-0.30
-0.80
-0.40
-1.00
-0.50
-1.20
-0.60
-1.30
-0.65
NOTE:
*1: When VDF(T)≦1.4V, the detection accuracy is ±30mV. When VDF(T)≧1.5V, the detection accuracy is ±2%.
*2: This numerical value is applied only to the XC6119C series (CMOS output).
5/16
XC6119 Series
■TEST CIRCUITS
Circuit 2
Circuit 1
RPULL=100kΩ
(No resistor needed for
CMOS output products)
Circuit 4
Circuit 3
Circuit 6
Circuit 5
RPULL=100kΩ
(No resistor needed for
CMOS output
VIN
VOUT
XC6119 Series
Cd
A
VSS
Circuit 7
Circuit 8
RPULL=100kΩ
VIN
(No resistor needed for
CMOS output products)
VOUT
XC6119 Series
Cd
V
VSS
6/16
Waveform Measurement Point
XC6119
Series
■OPERATIONAL EXPLANATION
A typical circuit example is shown in Figure 1, and the timing chart of Figure 1 is shown in Figure 2 on the next page.
The circuit which uses the delay
Capacitance pin as power input.
N-ch transictor for the delay
Capacitance discharge.
Delay Capacitor
Figure 1: Typical application circuit example
Input Voltage: VIN
Release Voltage: VDF+VHYS
Detect Voltage: VDF
Minimum Operationg Voltage (0.7V)
Delay Capacitance Pin Voltage: VCD
Delay Capacitance Pin Threshold Voltage: VTCD
Output Pin Voltage: VOUT
Figure 2: The timing chart of Figure 1
① As an early state, the input voltage pin is applied sufficiently high voltage to the release voltage and the delay capacitance
(Cd) is charged to the input pin voltage. While the input pin voltage (VIN) starts dropping to reach the detect voltage (VDF)
(VIN > VDF), the output voltage (VOUT) keeps the “High” level (=VIN).
② When the input pin voltage keeps dropping and becomes equal to the detect voltage (VIN = VDF), an N-ch transistor for the
delay capacitance discharge is turned ON, and starts to discharge the delay capacitance. For the internal circuit, which
uses the delay capacitance pin as power input, the reference voltage operates as a comparator of VIN, and the output
voltage changes into the “Low” level (≦VIN×0.1). The detect delay time (tDF) is defined as time which ranges from VIN =VDF
to the VOUT of “Low” level (especially, when the Cd pin is not connected: tDF0).
③ While the input pin voltage keeps below the detect voltage, and 0.7V or more, the delay capacitance is discharged to the
ground voltage (=VSS) level. Then, the output voltage (VOUT) maintains the “Low” level.
④ While the input pin voltage drops to less than 0.7V and it increases again to 0.7V or more, the output voltage may not be able
to maintain the “Low” level. Such an operation is called “Unspecified Operation”, and voltage which occurs at the output pin
voltage is defined as unstable operating voltage (VUNS).
7/16
XC6119 Series
■OPERATIONAL EXPLANATION (Continued)
⑤ While the input pin voltage increases more than 0.7V and it reaches to the release voltage level (VIN＜VDF +VHYS), the
output voltage (VOUT) maintains the “Low” level.
⑥ When the input pin voltage continues to increase more than 0.7V up to the release voltage level (= VDF + VHYS), the N-ch
transistor for the delay capacitance discharge will be turned OFF, and the delay capacitance will be started discharging via a
delay resistor (RDELAY). The internal circuit, which uses the delay capacitance pin as power input, will operate as a
hysteresis comparator (Rise Logic Threshold: VTLH=VTCD, Fall Logic Threshold: VTHL=VSS) while the input pin voltage keeps
higher than the detect voltage (VIN > VDF).
⑦ While the input pin voltage becomes equal to the release voltage or higher and keeps the detect voltage or higher, the delay
capacitance (Cd) will be charged up to the input pin voltage. When the delay capacitance pin voltage (VCD) reaches to the
delay capacitance pin threshold voltage (VTCD), the output voltage changes into the “High” (=VIN) level. tDR is defined as
time which ranges from VIN =VDF+VHYS to the VOUT of “High” level (especially when the Cd pin is not connected: tDR0). tDR
can be given by the formula (1).
tDR = －RDELAY×Cd×In (1－VTCD / VIN) +tDR0 …(1)
* In = a natural logarithm
The release delay time can also be briefly calculated with the formula (2) because the delay resistance is 2.0MΩ(TYP.) and the
delay capacitance pin threshold voltage is VIN /2 (TYP.)
tDR=RDELAY×Cd×0.69 …(2)
* RDELAY is 2.0MΩ(TYP.)
As an example, presuming that the delay capacitance is 0.68μF, tDR is :
2.0×106×0.68×10-6×0.69=938(ms)
* Note that the release delay time may remarkably be short when the delay capacitance is not discharged to the ground (=VSS)
level because time described in ③ is short.
⑧ While the input pin voltage is higher than the detect voltage (VIN > VDF), therefore, the output voltage maintains the
“High”(=VIN) level.
●Release Delay Time Chart
Delay Capacitance [Cd]
(μF)
0.01
0.022
0.047
0.1
0.22
0.47
1
Release Delay Time [tDR] (TYP.)
(ms)
13.8
30.4
64.9
138
304
649
1380
* The release delay time values above are calculate by using formula (2).
*1: The release delay time (tDR) is influenced by the release capacitance (Cd).
8/16
Release Delay Time [tDR] (MIN. ~ MAX.) *1
(ms)
11.0 ~ 16.6
24.3 ~ 36.4
51.9 ~ 77.8
110 ~ 166
243 ~ 364
519 ~ 778
1100 ~ 1660
XC6119
Series
■NOTES ON USE
1.
Please use this IC within the stated maximum ratings. For temporary, transitional voltage drop or voltage rising
phenomenon, the IC is liable to malfunction should the ratings be exceeded.
2. The input pin voltage drops by the resistance between power supply and the VIN pin, and by through current at operation of
the IC.
At this time, the operation may be wrong if the input pin voltage falls below the minimum operating voltage range.
In CMOS output, for output current, drops in the input pin voltage similarly occur.
Oscillation of the circuit may occur if the
drops in voltage, which caused by through current at operation of the IC, exceed the hysteresis voltage.
Note it especially
when you use the IC with the VIN pin connected to a resistor.
3. Note that a rapid and high fluctuation of the input pin voltage may cause a wrong operation.
4. Power supply noise may cause an operational function error. Care must be taken to put an external capacitor between
VIN-GND and test on the board carefully.
5. When there is a possibility of which the input pin voltage falls rapidly (e.g.: 6.0V to 0V) at release operation with the delay
capacitance pin (Cd) connected to a capacitor, use a schottky barrier diode connected between the VIN pin and the Cd pin
6.
as the Figure 3 shown below.
When N-channel open drain output is used, output voltages VOUT at voltage detection and release are determined by a
pull-up resistor tied to the output pin. A resistance value of the pull-up resistor can be selected with referring to the
followings. (Refer to Figure 4)
During detection, the formula is given as
VOUT=VPULL/(1+RPULL/RON)
where VPULL is pull-up voltage and RON (*1) is ON resistance of N-channel driver M5 (RON=VDS/IOUT1 from the electrical
characteristics table).
-3
For example, when VIN=2.0V (*2), RON = 0.5/0.8×10 =625Ω(MIN.) and if you want to get VOUT less than 0.1V when
VPULL=3.0V, RPULL can be calculated as follows;
RPULL=(VPULL /VOUT-1)×RON=(3/0.1-1)×625≒18ｋΩ
Therefore, pull-up resistance should be selected 18kΩ or higher.
(*1) VIN is smaller, RON is bigger
(*2) For the calculation, the lowest VIN should be used among of the VIN range
During release, the formula is given as
VOUT=VPULL/(1+RPULL/ROFF)
where VPULL is pull-up voltage ROFF is OFF resistance of N-channel driver M5 (ROFF=VOUT/ILEAK=15MΩ from the
electrical characteristics table)
For examples, if you want to get VOUT larger than 5.99V when VPULL is 6.0V, RPULL can be calculated as follows;
RPULL=(VPULL/VOUT-1)×ROFF=(6/5.99-1)×15×106≒25kΩ
Therefore, pull-up resistance should be selected 25kΩ or below.
7.
Torex places an importance on improving our products and their reliability. We request that users incorporate fail-safe
designs and post-aging protection treatment when using Torex products in their systems.
(No resistor needed for
CMOS output products)
Figure 3: Circuit example with the delay capacitance pin (Cd)
connected to a schottky barrier diode
Note: ROFF=VOUT/ILEAK
Figure 4: Circuit example of XC6109N Series
9/16
XC6119 Series
■TYPICAL PERFORMANCE CHARACTERISTICS
(1) Supply Current vs. Input Voltage
(2) Detect Voltage vs. Ambient Temperature
XC6119x25Ax
XC6119x25Ax
2.55
Detect Voltage: VDF (V)
Supply Current: ISS (μA)
2.0
Ta=85℃
25℃
1.5
1.0
-40℃
0.5
2.50
2.45
0.0
0
1
2
3
4
5
-50
6
-25
0
25
50
75
100
Ambient Temperature: Ta (℃)
Input Voltage: VIN (V)
(3) Hysteresis Voltage vs. Ambient Temperature
Hysteresis Voltage: VHYS (V)
XC6119x25Ax
0.20
0.15
0.10
0.05
-50
-25
0
25
50
75
100
Ambient Temperature: Ta (℃)
(4) Output Voltage vs. Input Voltage
XC6119N25Ax
XC6119C25Ax
Pull-up=VIN R=100kΩ
Output Voltage: VOUT (V)
Output Voltage: VOUT (V)
No Pull-up
4.0
3.0
2.0
Ta=85℃
25℃
1.0
-40℃
0.0
-1.0
0
0.5
1
1.5
2
Input Voltage: VIN (V)
10/16
2.5
3
4.0
3.0
Ta=85℃
2.0
25℃
1.0
-40℃
0.0
-1.0
0
0.5
1
1.5
2
Input Voltage: VIN (V)
2.5
3
XC6119
Series
■TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
(5) Output Current vs. Input Voltage
XC6119x50Ax
XC6119C08Ax
VDS(pch)=0.5V
Ta=-40℃
3.0
25℃
2.0
85℃
1.0
0.0
0
1
2
3
4
5
0.0
Output Current: IOUT (mA)
Output Current: IOUT (mA)
VDS(nch)=0.5V
4.0
-0.5
Ta=85℃
-1.0
25℃
-1.5
-2.0
6
0
1
Input Voltage: VIN (V)
Delay Resistance: Rdelay (MΩ)
Cd PIN Current: ICD (mA)
Ta=-40℃
25℃
1.5
1.0
85℃
0.5
0.0
2
3
4
5
6
3.5
3
2.5
2
1.5
1
-50
-25
Detect Delay Time: t DF (μs)
Release Delay Time: t DR (ms)
1000
100
10
tDR=Cd×2.0×106 ×0.69
0.01
0.1
Delay Capacitance: Cd (μF)
50
75
100
XC6119xxxAx
VIN(min)=0.7V VIN(max)=6.0V
tr=5μs Ta=25℃
0.001
25
(9) Detect Delay Time vs. Delay Capacitance
XC6119xxxAx
0.1
0.0001
0
Ambient Temperature: Ta (℃)
(8) Release Delay Time vs. Delay Capacitance
1
6
4
Input Voltage: VIN (V)
10000
5
VCD=0.0V VIN=6.0V
VDS=0.5V
1
4
XC6119xxxAx
3.0
0
3
(7) Delay Resistance vs. Ambient Temperature
XC6119x50Ax
2.0
2
Input Voltage: VIN (V)
(6) Cd Pin Sink Current vs. Input Voltage
2.5
-40℃
1
VIN(min)=0.7V VIN(max)=6.0V
tf=5μs Ta=25℃
100000
10000
1000
100
10
1
0.0001
0.001
0.01
0.1
1
Delay Capacitance: Cd (μF)
11/16
XC6119 Series
■TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
(10) Leak Current vs. Ambient Temperature
(11) Leak Current vs. Supply Voltage
XC6119N25Ax
XC6119N25Ax
VIN=6.0V
0.25
Leak Current: ILEAK (μA)
Leak Current: ILEAK (μA)
VIN=6.0V VOUT=6.0V
0.25
0.20
0.15
0.10
0.15
0.10
-50
-25
0
25
50
75
Ambient Temperature: Ta (℃)
12/16
0.20
100
0
1
2
3
4
5
Output Voltage: VOUT (V)
6
XC6119
Series
■PACKAGING INFORMATION
1.2±0.05
0.25±0.05
0.425±0.05
+0.02
0.38 -0.03
C0
.0
5
●USPN-4
Reference Pattern Layout
0.25
4
3
0.6
0.25
C0
.0
75
0.125
●USPN-4
0.25
1.1MAX
0.9±0.1
+0
0.3 -0.2
2.1±0.3
●USPN-4
+0.2
1.25 -0.1
●SSOT-24
1
0.55
2
0.125
Reference Metal Mask Design
0.1
0.2
0.2
4
3
1
0.55
2
0.1
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XC6119 Series
■MARKING RULE
3
②
④
③
① represents output configuration and integer number of detect voltage
①
4
●SSOT-24
CMOS Output (XC6119C Series)
MARK
A
B
C
D
E
F
VOLTAGE (V)
0.X
1.X
2.X
3.X
4.X
5.X
PRODUCT SERIES
XC6119C0**N*
XC6119C1**N*
XC6119C2**N*
XC6119C3**N*
XC6119C4**N*
XC6119C5**N*
N-channel Open Drain Output (XC6119N Series)
MARK
H
K
L
M
N
P
VOLTAGE (V)
0.X
1.X
2.X
3.X
4.X
5.X
PRODUCT SERIES
XC6119N0**N*
XC6119N1**N*
XC6119N2**N*
XC6119N3**N*
XC6119N4**N*
XC6119N5**N*
② represents decimal number of detect voltage
MARK
VOLTAGE (V)
PRODUCT SERIES
N
P
R
S
T
U
V
X
Y
Z
X.0
X.1
X.2
X.3
X.4
X.5
X.6
X.7
X.8
X.9
XC6119**0*N*
XC6119**1*N*
XC6119**2*N*
XC6119**3*N*
XC6119**4*N*
XC6119**5*N*
XC6119**6*N*
XC6119**7*N*
XC6119**8*N*
XC6119**9*N*
③④ represents production lot number
01 to 09, 0A to 0Z,11 to 9Z, A1 to A9,AA to Z9,ZA to ZZ repeated (G, I, J, O, Q, W excluded).
Note: No character inversion used.
14/16
1
2
SSOT-24
(TOP VIEW)
XC6119
Series
■ MARKING RULE (Continued)
●USPN-4
① represents product series.
MARK
B
1
PRODUCT SERIES
XC6119******-G
2
② represents output configuration and integer number of detect voltage
③
①
②
4
④
⑤
3
USPN-4
(TOP VIEW)
CMOS Output (XC6119C Series)
MARK
A
B
C
D
E
F
VOLTAGE (V)
0.X
1.X
2.X
3.X
4.X
5.X
PRODUCT SERIES
XC6119C0**7*-G
XC6119C1**7*-G
XC6119C2**7*-G
XC6119C3**7*-G
XC6119C4**7*-G
XC6119C5**7*-G
N-channel Open Drain Output (XC6119N Series)
MARK
H
K
L
M
N
P
VOLTAGE (V)
0.X
1.X
2.X
3.X
4.X
5.X
PRODUCT SERIES
XC6119N0**7*-G
XC6119N1**7*-G
XC6119N2**7*-G
XC6119N3**7*-G
XC6119N4**7*-G
XC6119N5**7*-G
③ represents decimal number of detect voltage
MARK
VOLTAGE (V)
PRODUCT SERIES
N
P
R
S
T
U
V
X
Y
Z
X.0
X.1
X.2
X.3
X.4
X.5
X.6
X.7
X.8
X.9
XC6119**0*7*-G
XC6119**1*7*-G
XC6119**2*7*-G
XC6119**3*7*-G
XC6119**4*7*-G
XC6119**5*7*-G
XC6119**6*7*-G
XC6119**7*7*-G
XC6119**8*7*-G
XC6119**9*7*-G
④⑤ represents production lot number
01 to 09, 0A to 0Z,11 to 9Z, A1 to A9,AA to Z9,ZA to ZZ repeated (G, I, J, O, Q, W excluded).
Note: No character inversion used.
15/16
XC6119 Series
1. The products and product specifications contained herein are subject to change without
notice to improve performance characteristics.
Consult us, or our representatives
before use, to confirm that the information in this datasheet is up to date.
2. We assume no responsibility for any infringement of patents, patent rights, or other
rights arising from the use of any information and circuitry in this datasheet.
3. Please ensure suitable shipping controls (including fail-safe designs and aging
protection) are in force for equipment employing products listed in this datasheet.
4. The products in this datasheet are not developed, designed, or approved for use with
such equipment whose failure of malfunction can be reasonably expected to directly
endanger the life of, or cause significant injury to, the user.
(e.g. Atomic energy; aerospace; transport; combustion and associated safety
equipment thereof.)
5. Please use the products listed in this datasheet within the specified ranges.
Should you wish to use the products under conditions exceeding the specifications,
please consult us or our representatives.
6. We assume no responsibility for damage or loss due to abnormal use.
7. All rights reserved. No part of this datasheet may be copied or reproduced without the
prior permission of TOREX SEMICONDUCTOR LTD.
16/16