20160325163105133

Preliminary
APX7320
Three-Phase Full-wave Sine-wave Brushless Motor Driver
Features
•
•
•
•
General Description
The APX7320 is a three-phase full-wave sine-wave
brushless motor drive by 1-hall or 3-hall (sensor or IC).
Three-Phase Full-Wave Sine-Wave Driver
1-Hall or 3-Hall Drive
This IC built-in linear or direct PWM input speed control,
leading angle setting, current limit, over current protec-
Wide Input Voltage: 6V to 30V
VSP Pin Linear or Direct PWM input
tion and soft start features suitable for the three-phase
brushless DC motors. The APX7320 is available in
Speed Control
•
•
•
•
•
•
Rotation Direction Selectable
TSSOP-28P package (see Pin Configuration).
Built-in 5V LDO Regulator
Built-in Charge Pump Circuit
Built-in Current Limit Circuit
Built-in Over Current Protection
Built-in Lock Protection and Auto Restart
Function
•
•
•
•
•
Soft Start Function
FG Output
Built-in Thermal Shutdown Protection
TSSOP-28P Package
Lead Free and Green Device Available
Pin Configuration
(RoHS Compliant)
VLAL 1
28 VCP
VLA_LIM 2
Applications
27 VCC
HUP 3
26 VM
HUM 4
25 PGND
HVP 5
24 UO
HVM 6
•
•
Home Appliance Cooling Fan
HWP 7
Instrumentation Fan
VLAH 9
HWM 8
23 UO
Exposed
Pad
(SGND)
5VREG 10
22 VO
21 VO
20 WO
19 WO
FG 11
18 VLIM
MIN 12
17 S-S
FR 13
16 CT
VSP 14
15 START
TSSOP-28P
= Thermal Pad (SGND must connected to the GND plane
for the IC circuit and better heat dissipation)
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright  ANPEC Electronics Corp.
Rev. P.1 - Aug., 2015
1
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Preliminary
APX7320
Ordering and Marking Information
Package Code
R: TSSOP - 28P
Operating Ambient Temperature Range
I : -40 to 90 oC
Handling Code
TR : Tape & Reel
Assembly Material
G: Halogen and Lead Free Device
APX7320
Assembly Material
Handling Code
Temperature Range
Package Code
APX7320 R :
APX7320
XXXXX
XXXXX - Date Code
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Absolute Maximum Ratings
Symbol
(Note1)
Parameter
Ratings
Unit
VCC
VCC Pin Supply Voltage (VCC to SGND)
-0.3 to 34
V
VM
VM Pin Supply Voltage (VM to PGND)
-0.3 to 34
V
-0.3 to V CC+6V
V
VVCP
IOUT
VUO, VO, WO
VHP, HM
VVLA (H, L, LIM)
VCP Pin Output Voltage (VCP to SGND)
UO, VO, WO Pin Maximum Output Peak Current
4.5
A
VPGND-0.3 to VCC
V
HUP, HUM, HVP, HVM, HWP and HWM Pins Input Voltage
-0.3 to 6
V
UO, VO and WO Pins Output Voltage
VLAH, VLAL and VLA_LIM Pins Input Voltage (to SGND)
-0.3 to 6
V
VVSP
VSP Pin Input Voltage (VSP to SGND)
-0.3 to 6
V
V MIN
MIN Pin Input Voltage (MIN to SGND)
-0.3 to 6
V
VFR
FR Pin Input Voltage (FR to SGND)
-0.3 to 6
V
V VLIM
VLIM Pin input Voltage (VLIM to SGND)
-0.3 to 6
V
I5VREG
5VREG Pin Output Source Current
0 to -30
mA
VFG
FG Pin Output Voltage
I FG
FG Pin Maximum Output Sink Current
TJ
Maximum Junction Temperature
-0.3 to 34
V
10
mA
o
150
TSTG
Storage Temperature
TSDR
Maximum Lead Soldering Temperature, 10 Seconds
C
-65 to 150
o
260
o
C
C
Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
Copyright  ANPEC Electronics Corp.
Rev. P.1- Aug., 2015
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Preliminary
APX7320
Thermal Characteristics
Symbol
Parameter
Thermal Resistance-Junction to Ambient
Typical Value
Unit
(Note 3)
?JA
50
o
20
o
C/W
TSSOP-28P
Thermal Resistance-Junction to Case (Note 4)
?JC
C/W
TSSOP-28P
Power Dissipation, T A=25oC
PD
2.5
W
Note 3: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad
of TSSOP-28P is soldered directly on the PCB.
Note 4: The case temperature is measured at the center on the top of the TSSOP-28P package.
Recommended Operation Conditions
Symbol
VCC
(Note3)
Parameter
Range
Unit
6 to 30
V
HUP, HUM, HVP, HVM, HWP and HWM Pins Input Voltage
0 to V 5VREG
V
VCC Pin Supply Voltage Range
V HP, HM (U, V, W)
VVLA (H, L, LIM)
VLAH, VLAL and VLA_LIM Pins Input Voltage
0 to V 5VREG
V
VVSP
VSP Pin Input Voltage
0 to V 5VREG
V
V MIN
MIN Pin Input Voltage
0 to V 5VREG
V
V VLIM
VLIM Pin Input Voltage
0 to V 5VREG
V
FR Pin Input Voltage Range
0 to V 5VREG
VFR
TA
TJ
Ambient Temperature
Junction Temperature
V
-40 to 90
o
-40 to 125
o
C
C
Note 5: Refer to the typical application circuit.
Electrical Characteristics (VCC = 24V, TA = 25oC, unless otherwise specified)
Symbol
Parameter
Test Conditions
APX7320
Min
Typ
Max
Unit
SUPPLY CURRENT
V5VREG
ICC
5VREG Pin Output Voltage
I5VREG = -25mA
4.6
4.8
5.5
V
Operating Current
Rotation Mode
5.5
7
8.5
mA
OUTPUT DRIVERS
VOL
Low-side Output Saturation Voltage
VCC=24V; I OUT =1A
-
0.12
0.18
V
VOH
High-side Output Saturation Voltage
VCC=24V; I OUT =1A
-
0.12
0.18
V
VFG
FG Pin Low Voltage
IFG=5mA
-
0.2
0.3
V
IFGL
FG Pin Off Leakage Current
VFG=24V
-
0.1
1
µA
FOUT
Output Switching Frequency
30
38
45
kHz
Copyright  ANPEC Electronics Corp.
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Preliminary
APX7320
Electrical Characteristics (VCC = 24V, TA = 25oC, unless otherwise specified)
Symbol
Parameter
Test Conditions
APX7320
Unit
Min
Typ
Max
0.3
-
V5VREG-2
V
0
-
V5VREG
V
±1
± 7.5
± 15
mV
HALL AMPLIFIER
VICM1
HALL Common-mode Input Voltage 1
Hall element application
VICM2
HALL Common-mode Input Voltage 2
Hall IC application
VHYS
HALL Input Hysteresis Voltage
LOCK PROTECTION
VCTH
CT Pin High Level Voltage
2.7
3
3.3
V
VCTL
CT Pin Low Level Voltage
0.9
1
1.1
V
ICT1
CT Charge Current
VCT=0.5V
1.5
2
2.5
µA
ICT2
CT Discharge Current
VCT=3.5V
0.3
0.4
0.5
µA
R CT
CT Charge/Discharge Current Ratio
4
5
6
-
START UP OSCILLATOR
VSTARTH
START Pin High Level Voltage
1.2
1.6
2
V
VSTARTL
START Pin Low Level Voltage
0.6
0.8
1
V
IS TART1
START Pin Charge Current
5.5
7
8.5
µA
5.5
7
8.5
µA
1.2
1.6
2
V
IS TART2
START Pin Discharge Current
VSTART=0V
VSTART=2V
SOFT START OSCILLATOR
VS-S H
S-S Pin High Level Voltage
VS-SL
S-S Pin Low Level Voltage
0.6
0.8
1
V
IS-S1
S-S Pin Charge Current
VS-S=0V
5.5
7
8.5
µA
IS-S2
S-S Pin Discharge Current
VS-S=2V
5.5
7
8.5
µA
FR
VFRH
FR Pin High Level Voltage
2.5
-
V5VREG
V
VFRL
FR Pin Low Level Voltage
0
-
1
V
-
2.5
-
µA
IFR
FR Pin Bias Current
VFR=0V
VSP VOLTAGE MODE
VSPH
VSP Voltage of Maximum Output Duty
5VREG* 5VREG* 5VREG*
0.85
0.9
0.95
V
VSPL
VSP Voltage of Minimum Output Duty
5VREG* 5VREG* 5VREG*
0.285
0.3
0.315
V
5VREG* 5VREG* 5VREG*
0.14
0.16
0.18
V
100
200
mV
5.5
V
-
1
V
-
0
-
°
VVLAH= 1/2*V5VREG
26.5
30
33.5
°
VVLAH= V5VREG
54.5
58
61.5
°
V SPSD
VSP Voltage of Output Shut-down
VSPHYS
VSPSD Hysteresis
VMIN>0V, OUTPUT OFF
-
VSP DIRECT PWM MODE (MIN=V5VREG)
VPWMH
VSP High Level Voltage for PWM
Mode
2.5
VPWMH
VSP Low Level Voltage for PWM Mode
0
-
LEAD ANGLE
TLAH1
TLAH2
TLAH3
Lead Angle Correction
(VSP=V 5VREG,V VLAL=0V,VVLA_LIM=
floating)
Copyright  ANPEC Electronics Corp.
Rev. P.1- Aug., 2015
VVLAH= 0V
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Preliminary
APX7320
Electrical Characteristics (VCC = 24V, TA = 25oC, unless otherwise specified)
Symbol
Parameter
Test Conditions
APX7320
Min
Typ
Max
Unit
CURRENT PROTECTION
ILIM
IOCP
Current Limit Level
VLIM= 0V to 1V
-
1
-
A
Current Limit Level
VLIM= 3V to V5VREG
-
3
-
A
-
4.5
-
A
-
165
-
o
-
o
Over Current Protection
THERMAL PROTECTION
Thermal Protection Temperature
Thermal Protection Hysteresis
Copyright  ANPEC Electronics Corp.
Rev. P.1- Aug., 2015
-
5
30
C
C
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Preliminary
APX7320
Pin Description
PIN
NO.
NAME
1
VLAL
2
VLA_LIM
FUNCTION
Leading Angle Setting Input Pin. Low bound lead angle (LAL) setting at 0% output duty.
Leading Angle Setting Input Pin. Maximum lead angle (LAL_LIM) clamp setting.
3
HUP
Hall Input + of U-phase. Connect to hall element positive terminal or the output of hall IC.
4
HUM
Hall Input - of U-phase. Connect to hall element negative terminal.
5
HVP
Hall Input + of V-phase. Connect to hall element positive terminal or the output of hall IC.
6
HVM
Hall Input - of V-phase. Connect to hall element negative terminal or pull up to 5VREG for 1-Hall
application.
7
HWP
Hall Input + of W-phase. Connect to hall element positive terminal or the output of hall IC.
8
HWM
Hall Input - of W-phase. Connect to hall element negative terminal or pull up to 5VREG for 1-Hall
application.
Leading Angle Setting Input Pin. High bound lead angle (LAH) setting at 100% output duty.
9
VLAH
10
5VREG
11
FG
Rotation Speed Output.
12
MIN
Minimum Speed Setting. VSP pin will be changed to direct PWM mode when MIN pin connect to 5VREG.
13
FR
5V Regulator Output. This is a 5V constant-voltage output for application circuit biases.
Rotation Direction Control.
Low Level Input (short to GND): U à V à W (Forward)
High Level Input (short to 5VREG): U à W à V (Reverse)
14
VSP
15
START
16
CT
Shutdown Time and Restart Time Setting. Connect a capacitor to SGND to set shutdown time and restart
time in lock mode.
17
S-S
Soft-Start Time Setting. Connect a capacitor to SGND to set soft-start time to reduce the large current at
power on and lock-restart mode.
18
VLIM
19
WO
Driver Output Pin. Output signal for driving motor phase W. Pin19 and 20 must be short for maximum
current rating.
20
WO
Driver Output Pin. Output signal for driving motor phase W. Pin19 and 20 must be short for maximum
current rating.
21
VO
Driver Output Pin. Output signal for driving motor phase V. Pin21 and 22 must be short for maximum
current rating.
22
VO
Driver Output Pin. Output signal for driving motor phase V. Pin21 and 22 must be short for maximum
current rating.
23
UO
Driver Output Pin. Output signal for driving motor phase U. Pin23 and 24 must be short for maximum
current rating.
24
UO
Driver Output Pin. Output signal for driving motor phase U. Pin23 and 24 must be short for maximum
current rating.
25
PGND
26
VM
Supply Voltage for Output Stage Input Pin.
27
VCC
Supply Voltage Input Pin.
28
VCP
Charge Pump Output. A capacitor must be connected to VCC.
Exposed
Pad
SGND
Speed Control Input Pin. Linear voltage or direct PWM input.
Start-up Time Setting Input Pin. Connect a capacitor to SGND to set the start-up timing.
Current Limit Setting Input Pin.
Power Stage GND.
Control Stage GND.
Copyright  ANPEC Electronics Corp.
Rev. P.1- Aug., 2015
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Preliminary
APX7320
Block Diagram
Charge
Pump
5VREG
VCP
HUP
VCC
HUM
HVP
HVM
5V
Regulator
Hall
Hysteresis
Amp.
VM
TSD
HWP
HWM
UO
VO
VLAL
VLA_LIM
VLAH
Control
Circuit
ADC
Driver
WO
PGND
MIN
VSP
FR
Current Limit
Circuit
FG
Soft
Start
Start up
Clock
VLIM
S-S
Lock
Re-start
SGND
CT
START
Copyright  ANPEC Electronics Corp.
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Preliminary
APX7320
Typical Application Circuit
Circuit 1: 3-Hall Input Application
VCC
5VREG
VCP
HUP
H
0.1μF
VCC
VIN
HUM
HVP
VM
HVM
PGND
H
HWP
H
UO
HWM
UO
VO
5VREG
1μF
VO
WO
VLAL
WO
5VREG
VLA_LIM
VLAH
VLIM
MIN
S-S
FG
CT
CS-S : 2.2nF
CCT : 1μ
F
VSP
START
FR
SGND
CSTART : 2.2nF
Note: The capacitance of CS-S , CSTART and CCT can be fine tune for different parameter of motor.
Copyright  ANPEC Electronics Corp.
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Preliminary
APX7320
Typical Application Circuit
Circuit 2: 1-Hall Input Application
VCC
5VREG
VCP
HUP
H
0.1μF
VCC
VIN
HUM
HVP
VM
HVM
PGND
HWP
UO
HWM
UO
VO
5VREG
1μF
VO
WO
VLAL
WO
5VREG
VLA_LIM
VLAH
VLIM
MIN
S-S
FG
CT
CS-S : 2.2nF
CCT : 1μ
F
VSP
START
FR
SGND
CSTART : 2.2nF
Note: The capacitance of CS-S , CSTART and CCT can be fine tune for different parameter of motor.
Copyright  ANPEC Electronics Corp.
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Preliminary
APX7320
Function Description
VSP and MIN Output Duty Control
The APX7320 has two input pin VSP and MIN to control output duty of driver for the rotation speed of motor. The input
of MIN pin is for the minimum output duty setting, and the VSP is for motor speed control.
Output Duty
Output Duty
100%
100%
75%
75%
50%
50%
MIN=3.75V
MIN=2.5V
25%
MIN=3.75V
MIN=2.5V
25%
MIN=1.25V
MIN=1.25V
MIN=0V
MIN=0V
VSP
0%
0
0.8
1.5
4.5
5
VSP
0.8
1.5
VSP 5V to 0V
4.5
5
VSP 0V to 5V
Figure1: Voltage Mode Output Duty Control
VSP Direct PWM Control
The APX7320 also support direct PWM input signal speed control. When the MIN pin pulled up to 5VREG, the VSP will
be PWM input pin to control the output duty directly.
Output Duty
100%
75%
50%
25%
PWM Duty
0%
0 DISD
100%
Figure2: Direct PWM Mode Output Duty Control
Copyright  ANPEC Electronics Corp.
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Preliminary
APX7320
Function Description
Lead Angle Control
The APX7320 built in automatic lead angle controlled by the duty variation of output. The lead angle can be adjusted
between 0oC to 58oC in 32 separate steps according to the input voltages of VLAH, VLAL and VLA_LIM pins, which work
with 0V to V5VREG. The lead angle control range is the minimum value LAL (set by VLAL) to the maximum value LAH (set
by VLAH) for the output duty 0% to 100%. The VLA_LIM pin input voltage is used to clamp the maximum lead angle of
driver operation.
LA
LA
58°
58°
LAH
LA_LIM
VLAL<VLA_LIM<VLAH
LAL
0°
0
5
VLAH
/VLAL
/VLA_LIM
0°
0
Output Duty
MIN_DUTY
100%
LA
58°
LAH
LA_LIM
VLAL<VLA_LIM<VLAH
LA_MIN
LAL
0°
0
VSP
0.8
1.5
4.5
5
Figure3: Lead Angle Control
Copyright  ANPEC Electronics Corp.
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Preliminary
APX7320
Function Description
Hall Element & Hall IC
The APX7320 hall signal input pin offers two types of Hall element and Hall IC application, the circuit design will be
more flexible.
Hall Element
HALL IC
5VREG
5VREG
5VREG
HUM,HVM,HWM
HUP
HALL
HUM
HVP
HALL
HVM HWP
HALL
HALL
IC
HWM
HUP
HALL
IC
HVP
HALL
IC
HWP
Figure 4: HALL Input Circuits
Copyright  ANPEC Electronics Corp.
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Preliminary
APX7320
Function Description
Forward Rotation Timing Chard (FR=GND, VLAH=0V)
HUP
HUM
HVP
Hall input signal
HVM
HWP
HWM
FG output signal
FG
SU
Sine wave Modulation
waveform of UO,VO,WO
SV
(in side the IC)
SW
UO
Output PWM signal
for sine wave drive
(UO,VO,WO)
VO
WO
Figure 5: Forward Rotation Input and Output timing chards
Copyright  ANPEC Electronics Corp.
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Preliminary
APX7320
Function Description
Reverse Rotation Timing Chard (FR=5VREG, VLAH=0V)
HUP
HUM
HVP
Hall input signal
HVM
HWP
HWM
FG output signal
FG
SU
Sine wave Modulation
waveform of UO,VO,WO
SV
(in side the IC)
SW
UO
Output PWM signal
for sine wave drive
(UO,VO,WO)
VO
WO
Figure 5: Reverse Rotation Input and Output timing chards
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Preliminary
APX7320
Function Description
Sine Wave Modulation
This is a soft switch PWM output to make the phase current smoother, which can reduce the noise of motor in switch
interval. Using PWM duty control to simulate the idea sine wave output current.
Sine Wave
Modulation
(internal signal)
Sinusoidal PWM Output
(UO,VO,WO)
Figure 6: Sine Wave Modulation PWM Output
Lockup Protection and Automatic Restart
The APX7320 provides the lockup protection and automatic restart functions for preventing the coil burnout while the
fan motor is locked. When the lock-restart cycle repeated to 20 times, the output will be shut down until pull low VSP
pin or re-power on. Connecting the capacitor from CT pin to SGND can determine the shut down time and restart time.
Current Limit and Over Current Protection (OCP)
The APX7320 includes an internal current sense circuits for current limit and over-current protection (OCP). When the
total current of three phase over the current limit level, the high side driver will be turned off to stop supplying current
to the motor. If the total output current over the OCP current level, the OCP function will be enable to turn-off all of the
high side output driver to prevent output short through condition until pull low VSP pin or re-power on.
Thermal Protection
The APX7320 is designed with a thermal protection to protect the IC from the damage of over temperature. When
internal junction temperature reaches 165oC, the output devices will be switched off. When the IC’s junction temperature cools by 30 oC, the thermal sensor will turn the output devices on again resulting in a pulsed output during
continuous thermal overload.
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Preliminary
APX7320
Application Information
Input Capacitor
For the noise reduction purpose, all of the capacitors in application circuit should be placed as close as possible to the
IC pin.
CT Capacitor
The capacitor that is connected from CT pin to GND determines the shutdown time and restart time.
Locked Detection Time =
Restart Time =
CCT × ( VCTH − 0.2V )
ICT1
CCT × ( VCTH − VCTL )
ICT1
Shutdown Time =
CCT × ( VCTH − VCTL )
ICT 2
For example:
VCC=24V, CCT=1µF
VCTL=1V, VCTH=3V, ICT1=2µA, ICT2=0.4µA
Locked Detection Time = 1.4s
Restart Time = 1s
Shutdown Time= 5s
The value of CCT must be considered with soft start up result.
START Capacitor
The START pin capacitor is used to set the force start up timing (TSTART) of one step (60oC) for sine-wave start up. Adjust
START capacitor can set the start up timing for different motor or loading of fan motor.
TSTART =
2 × (VSTARTH − VSTARTL ) × CSTART
× 32 × 32
ISTART
For example:
CSTART =2.2nF
VSTARTL=0.8V, VSTARTH=1.6V, ISTART=7µA
The force start up time is 515ms
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APX7320
Preliminary
Application Information
S-S Capacitor
The S-S capacitor is used to set the output duty change rate for soft start. The time (TS-S) is define the time of output duty
from 0% to 100%.
TS − S =
2 × (VS − SH − VS − SL ) × CS − S
× 32 × 256
IS − S
For example:
CS-S =2.2nF
VS-SL=0.8V, VS-SH=1.6V, IS-S=7µA
The time (TS-S) of duty change from 0% to 100% is 4.12s
The choices of CT pin and S-S pin capacitors should be considered that fan must start up during restart time at lock
mode. When the CCT is determined and the fan can’t start up at power-on or lock-restart mode, decrease the CS-S
capacitance can let the fan start up successfully but it will reduce the soft start time.
FIL Capacitor
The capacitor connects between HUP and HUM (HVP and HVM, HWP and HWM) pin to filter the noise when phase
change to make sure phase change correctly. Its capacitance from 1nF to 10nF is recommended.
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Preliminary
APX7320
Package Information
TSSOP-28P
D
SEE VIEW A
E2
EXPOS
ED PAD
E1
E
D1
c
0.25
b
S
Y
M
B
O
L
VIEW A
L
GAUGE PLANE
SEATING PLANE
0
A1
A2
A
e
TSSOP-28P
INCHES
MILLIMETERS
MIN.
MAX.
A
MIN.
MAX.
1.20
0.047
A1
0.05
0.15
0.002
0.006
A2
0.80
1.05
0.031
0.041
b
0.19
0.30
0.007
0.012
0.008
c
0.09
0.20
0.004
D
9.60
9.80
0.378
0.386
D1
4.50
6.00
0.177
0.236
0.260
E
6.20
6.60
0.244
E1
4.30
4.50
0.169
0.177
E2
2.50
3.50
0.098
0.138
0.75
0.018
8o
0o
e
0.65 BSC
L
0.45
0
0o
0.026 BSC
0.030
8o
Note : 1. Followed from JEDEC MO-153 AET.
2. Dimension "D" does not include mold flash, protrusions
or gate burrs. Mold flash, protrusion or gate burrs shall not
exceed 6 mil per side.
3. Dimension "E1" does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 10 mil per side.
Copyright  ANPEC Electronics Corp.
Rev. P.1- Aug., 2015
18
www.anpec.com.tw
Preliminary
APX7320
Carrier Tape & Reel Dimensions
P0
P2
P1
A
B0
W
F
E1
OD0
K0
A0
A
OD1 B
B
T
SECTION A-A
SECTION B-B
H
A
d
T1
Application
TSSOP-28P
A
H
T1
C
d
D
W
E1
F
330.0±2.00
50 MIN.
16.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
16.0±0.30
1.75±0.10
7.50±0.10
P0
P1
P2
D0
D1
T
A0
B0
K0
4.00±0.10
12.00±0.10
2.00±0.10
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.40
6.9±0.20 10.20.±0.20
1.50±0.20
(mm)
Devices Per Unit
Package Type
TSSOP-28P
Copyright  ANPEC Electronics Corp.
Rev. P.1- Aug., 2015
Unit
Tape & Reel
Quantity
2000
19
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APX7320
Preliminary
Taping Direction Information
TSSOP-28P
USER DIRECTION OF FEED
Classification Profile
Copyright  ANPEC Electronics Corp.
Rev. P.1- Aug., 2015
20
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Preliminary
APX7320
Classification Reflow Profiles
Profile Feature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
3 °C/second max.
3°C/second max.
183 °C
60-150 seconds
217 °C
60-150 seconds
See Classification Temp in table 1
See Classification Temp in table 2
Time (tP)** within 5°C of the specified
classification temperature (Tc)
20** seconds
30** seconds
Average ramp-down rate (Tp to Tsmax)
6 °C/second max.
6 °C/second max.
6 minutes max.
8 minutes max.
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
Average ramp-up rate
(Tsmax to TP)
Liquidous temperature (TL)
Time at liquidous (tL)
Peak
(Tp)*
package
body
Temperature
Time 25°C to peak temperature
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
3
Package
Thickness
<2.5 mm
Volume mm
<350
235 °C
Volume mm
≥350
220 °C
≥2.5 mm
220 °C
220 °C
3
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness
<1.6 mm
1.6 mm – 2.5 mm
≥2.5 mm
Volume mm
<350
260 °C
260 °C
250 °C
3
Volume mm
350-2000
260 °C
250 °C
245 °C
3
Volume mm
>2000
260 °C
245 °C
245 °C
3
Reliability Test Program
Test item
SOLDERABILITY
HOLT
PCT
TCT
ESD
Latch-Up
Copyright  ANPEC Electronics Corp.
Rev. P.1- Aug., 2015
Method
JESD-22, B102
JESD-22, A108
JESD-22, A102
JESD-22, A104
MIL-STD-883-3015.7
JESD 78
21
Description
5 Sec, 245°C
1000 Hrs, Bias @ Tj=125°C
168 Hrs, 100%RH, 2atm, 121°C
500 Cycles, -65°C~150°C
VHBM≧2KV, VMM≧200V
10ms, 1tr≧100mA
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APX7320
Preliminary
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
Copyright  ANPEC Electronics Corp.
Rev. P.1- Aug., 2015
22
www.anpec.com.tw