PCS2I99448 September 2006 rev 0.4 3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer Features The PCS2I99448 is specifically designed to distribute • 12 LVCMOS compatible clock outputs LVCMOS compatible clock signals up to a frequency of • Selectable LVCMOS and differential LVPECL 350MHz. Each output provides a precise copy of the input signal with a near zero skew. The outputs buffers support compatible clock inputs driving of 50Ω terminated transmission lines on the incident • Maximum clock frequency of 350MHz • Maximum clock skew of 150pS • Synchronous output stop in logic low state edge: each output is capable of driving either one parallel terminated or two series terminated transmission lines. eliminates output runt pulses Two selectable, independent clock inputs are available, providing support of LVCMOS and differential LVPECL • High–impedance output control clock distribution systems. The PCS2I99448 CLK_STOP • 3.3V or 2.5V power supply control is synchronous to the falling edge of the input clock. • Drives up to 24 series terminated clock lines It allows the start and stop of the output clock signal only in • Ambient temperature range -40°C to +85°C a logic low state, thus eliminating potential output runt • 32–Lead LQFP & TQFP packaging pulses. Applying the OE control will force the outputs into • Supports • clock distribution in networking, high–impedance mode. telecommunication and computing applications All inputs have an internal pull–up or pull–down resistor Pin and Function compatible to MPC9448 and preventing unused and open inputs from floating. The device supports a 2.5V or 3.3V power supply and an MPC948 ambient temperature range of –40°C to +85°C. The Functional Description PCS2I99448 The PCS2I99448 is a 3.3V or 2.5V compatible, 1:12 clock performance–enhanced to the MPC948. is pin and function compatible fanout buffer targeted for high performance clock tree applications. With output frequencies up to 350 MHz and output skews less than 150 pS, the device meets the needs of most demanding clock applications. PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200, Campbell, CA 95008 • Tel: 408-879-9077 • Fax: 408-879-9018 www.pulsecoresemi.com Notice: The information in this document is subject to change without notice. but PCS2I99448 September 2006 rev 0.4 Block Diagram VCC PCLK PCLK 0 CCLK 1 Q0 CLK Q1 STOP Q2 Q3 Q4 VCC Q5 Q6 CLK_SEL VCC Q7 SYNC CLK_STOP Q8 Q9 Q10 VCC OE Q11 (All input resistors have a value of 25KΩ) GND Q4 VCC Q5 GND Q6 VCC Q7 Pin Diagram 24 23 22 21 20 19 18 17 Q3 25 16 GND VCC 26 15 Q8 Q2 27 14 VCC GND 28 13 Q9 Q1 29 12 GND VCC 30 11 Q10 Q0 31 10 VCC GND 32 9 Q11 1 2 3 4 5 6 7 8 CLK_SEL CCLK PCLK PCLK CLK_STOP OE VCC GND PCS2I99448 3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer Notice: The information in this document is subject to change without notice. 2 of 15 PCS2I99448 September 2006 rev 0.4 Table 1. FUNCTION TABLE Control Default CLK_SEL 1 0 1 PECL differential input selected CCLK input selected 1 OE 1 Outputs disabled (high-impedance state) CLK_STOP 1 Outputs synchronously stopped in logic low state Outputs enabled Outputs active Note: 1. OE=0 will high-impedance tristate all outputs independent on CLK_STOP. Table 2. PIN CONFIGURATION Pin# Pin Name 4,3 PCLK, PCLK I/O Type Function Input LVPECL LVPECL Clock Inputs 2 CCLK Input LVCMOS Alternative clock signal input 1 CLK_SEL Input LVCMOS Clock input select Input LVCMOS Clock output enable/disable Input LVCMOS Output enable/disable (high–impedance tristate) Q0 – Q11 Output LVCMOS Clock output 8,12,16,20,24,28,32 GND Supply Ground 7,10,14,18,22,26,30 VCC Supply VCC 5 CLK_STOP 6 OE 31,29,27,25,23,21,19,17,15,13,11,9 Negative power supply (GND) for I/O and core. Positive power supply for I/O and core. All VCC pins must be connected to the positive power supply for correct operation Table 3. ABSOLUTE MAXIMUM RATINGS1 Symbol Parameter Min Max Unit VCC Supply Voltage -0.3 3.9 V VIN DC Input Voltage -0.3 VCC + 0.3 V DC Output Voltage -0.3 VCC + 0.3 V DC Input Current ±20 mA IOUT DC Output Current ±50 mA TStor Storage Temperature Range 125 °C VOUT IIN -65 Note: 1. These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect device reliability. 3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer Notice: The information in this document is subject to change without notice. 3 of 15 PCS2I99448 September 2006 rev 0.4 Table 4. GENERAL SPECIFICATIONS Symbol Characteristic Min Typ Max Unit Condition VTT Output Termination Voltage V MM ESD Protection (Machine Model) 200 V HBM ESD Protection (Human Body Model) 2000 V LU Latch–up Immunity 200 mA CPD Power Dissipation Capacitance 10 pF Per Output CIN Input Capacitance 4.0 pF Inputs VCC÷2 Table 5. DC CHARACTERISTICS (VCC = 3.3V ± 5%, TA = –40°C to +85°C) Symbol Characteristic Min Typ Max Unit Condition VIH Input HIGH Voltage 2.0 VCC + 0.3 V LVCMOS VIL Input LOW Voltage -0.3 0.8 V LVCMOS VPP Peak–to–Peak Input Voltage PCLK 250 mV LVPECL Common Mode Range PCLK 1.1 VCC - 0.6 V LVPECL 300 µA VIN = VCC or GND V IOH = –24mA3 V V IOL = 24mA3 IOL = 12mA VCMR1 IIN Input Current 2 VOH Output HIGH Voltage VOL Output LOW Voltage ZOUT Output Impedance ICCQ 4 Maximum Quiescent Supply Current 2.4 0.55 0.30 17 Ώ 2.0 mA All VCC Pins Note: 1. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (DC) specification. 2. Input pull-up / pull-down resistors influence input current. 3. The PCS2I99448 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50Ω series terminated transmission lines (for VCC=3.3V) or one 50Ω series terminated transmission line (for VCC=2.5V). 4. ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open. 3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer Notice: The information in this document is subject to change without notice. 4 of 15 PCS2I99448 September 2006 rev 0.4 Table 6. AC CHARACTERISTICS (VCC = 3.3V ± 5%, TA = –40°C to +85°C)1 Symbol fref Characteristics fMAX Input Frequency Maximum Output Frequency VPP Min Peak-to-peak input voltage PCLK VCMR2 Common Mode Range PCLK tP, REF Reference Input Pulse Width tr, tf Max Unit 0 0 Typ 350 350 MHz MHz 400 1000 mV LVPECL 1.3 VCC-0.8 V LVPECL 1.4 nS CCLK Input Rise/Fall Time tPLH/HL tPLH/HL Propagation delay tPLZ, HZ tPZL, LZ Output Disable Time Output Enable Time tS Hold time tsk(O) Output-to-output Skew tsk(PP) Device-to-device Skew tSK(P) Output pulse skew4 DCQ Output Duty Cycle tr, tf Output Rise/Fall Time nS nS 1.6 3.6 CCLK to any Q 1.3 3.3 nS 11 11 nS nS PCLK to CLK_STOP tH 1.03 PCLK to any Q CCLK to CLK_STOP Setup time Condition 0.0 0.8 to 2.0V nS 0.0 nS CCLK to CLK_STOP 1.0 nS PCLK to CLK_STOP 1.5 nS 150 pS 2.0 300 nS Using CCLK Using PCLK 400 pS 55 % DCREF = 50% 1.0 nS 0.55 to 2.4V PCLK or CCLK to any Q fQ<170 MHz 45 50 0.1 pS Note: 1. AC characteristics apply for parallel output termination of 50Ω to VTT. 2. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts tPLH/HL and tSK(PP). 3. Violation of the 1.0 nS maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse width, output duty cycle and maximum frequency specifications. 4. Output pulse skew is the absolute difference of the propagation delay times: | tpLH - tpHL |. Table 7. DC CHARACTERISTICS (VCC = 2.5V ± 5%, TA = –40°C to +85°C) Symbol VIH VIL Characteristics Min Input high voltage Input low voltage VPP 1 VCMR IIN Typ 1.7 -0.3 Peak-to-peak input voltage PCLK 250 Common Mode Range PCLK 1.0 Input current2 VOH Output High Voltage VOL Output Low Voltage ZOUT ICCQ4 Output impedance Maximum Quiescent Supply Current Max Unit VCC + 0.3 0.7 V LVCMOS V LVCMOS mV LVPECL VCC-0.7 V 300 µA Condition V LVPECL VIN=GND or VIN=VCC IOH= -15 mA3 0.6 V IOL= 15 mA3 2.0 Ω mA All VCC Pins 1.8 19 Note: 1. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (DC) specification. 2. Input pull-up / pull-down resistors influence input current. 3. The PCS2I99448 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives one 50Ω series terminated transmission lines at VCC=2.5V. 4. ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open. 3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer Notice: The information in this document is subject to change without notice. 5 of 15 PCS2I99448 September 2006 rev 0.4 Table 8. AC CHARACTERISTICS (VCC = 2.5V ± 5%, TA = –40°C to +85°C)1 Symbol Max Unit Input Frequency 0 350 MHz fMAX Maximum Output Frequency 0 350 MHz VPP Peak-to-peak input voltage PCLK 400 1000 mV LVPECL Common Mode Range PCLK 1.2 VCC-0.8 V LVPECL fref VCMR2 tP, REF tr, tf Characteristics Reference Input Pulse Width Propagation delay tPLZ, HZ tPZL, LZ Output Disable Time Output Enable Time tH 1.4 tSK(p) Condition nS 1.03 nS PCLK to any Q 1.5 4.2 nS CCLK to any Q 1.7 4.4 nS 11 11 0.0 nS nS nS PCLK to CLK_STOP 0.0 nS CCLK to CLK_STOP 1.0 nS 1.5 nS 0.8 to 2.0V CCLK to CLK_STOP Setup time Hold time PCLK to CLK_STOP tsk(O) tsk(PP) Typ CCLK Input Rise/Fall Time tPLH/HL tPLH/HL tS Min Output-to-output Skew Device-to-device Skew 4 Output pulse skew DCQ Output Duty Cycle tr, tf Output Rise/Fall Time PCLK or CCLK to any Q Using CCLK Using PCLK 150 2.7 pS nS 200 300 pS pS fQ< 350 MHz and using CLK 45 50 55 % fQ<200 MHz and using PCLK 45 50 55 % 1.0 nS 0.1 DCREF = 50% 0.6 to 1.8V Note: 1. AC characteristics apply for parallel output termination of 50Ω to VTT. 2. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts tPLH/HL and tSK(PP). 3. Violation of the 1.0nS maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse width, output duty cycle and maximum frequency specifications. 4. Output pulse skew is the absolute difference of the propagation delay times: | tpLH - tpHL |. 3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer Notice: The information in this document is subject to change without notice. 6 of 15 PCS2I99448 September 2006 rev 0.4 APPLICATIONS INFORMATION The waveform plots in Figure 3 “Single versus Dual Line Termination Waveforms” show the simulation results of an output driving a single line versus two lines. In both CCLK or PCLK CLK _ STOP 3.0 Q0 to Q11 Timing Diagram Figure 1. Output Clock Stop (CLK_STOP) Driving Transmission Lines The PCS2I99448 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user, the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of 17Ω (VCC=3.3V), the outputs can drive either parallel or series terminated transmission lines. In most high performance clock networks, point–to–point distribution of signals is the method of choice. In a point–to–point scheme, either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50Ω resistance to VCC÷2. PCS2I99448 OUTPUT BUFFER 17Ω PCS2I99448 OUTPUT BUFFER Z0=50Ω RS=33Ω Z0=50Ω RS=33Ω 17Ω RS=33Ω Z0=50Ω Figure 2. Single versus Dual Transmission Lines This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the PCS2I99448 clock driver. For the series terminated case, however, there is no DC current draw; thus, the outputs can drive multiple series terminated lines. Figure 2 “Single versus Dual Transmission Lines” illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme, the fanout of the PCS2I99448 clock driver is effectively doubled due to its capability to drive multiple lines at VCC=3.3V. VOLTAGE (V) 2.5 OutA tD = 3.8956 OutB tD = 3.9386 2.0 In 1.5 1.0 0.5 0 2 4 6 8 10 12 14 TIME (nS) Figure 3 . Single versus Dual Line Termination Waveforms cases, the drive capability of the PCS2I99448 output buffer is more than sufficient to drive 50Ω transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43pS exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output–to–output skew of the PCS2I99448. The output waveform in Figure 3 “Single versus Dual Line Termination Waveforms” shows a step in the waveform; this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 33Ω series resistor plus the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: VL = VS ( Z0 ÷ (RS+R0 +Z0)) Z0 = 50Ω|| 50Ω RS = 33Ω|| 33Ω R0 = 17Ω VL = 3.0 ( 25 ÷ (16.5+17+25) = 1.28V At the load end the voltage will double, due to the near unity reflection coefficient, to 2.5V. It will then increment towards the quiescent 3.0V in steps separated by one round trip delay (in this case 4.0nS). Since this step is well above the threshold region it will not cause any false clock triggering; however, designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving 3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer Notice: The information in this document is subject to change without notice. 7 of 15 PCS2I99448 September 2006 rev 0.4 multiple lines, the situation in Figure 4 “Optimized Dual Line Termination” should be used. In this case, the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched. PCS2I99448 OUTPUT BUFFER RS=16Ω 17Ω RS=16Ω Increased power consumption will increase the die junction temperature and impact the device reliability (MTBF). According to the system-defined tolerable MTBF, the die junction temperature of the PCS2I99448 needs to be controlled and the thermal impedance of the board/package should be optimized.The power dissipated in the PCS2I99448 is represented in equation 1. Z0=50Ω Where ICCQ is the static current consumption of the PCS2I99448, CPD is the power dissipation capacitance per output, (Μ)ΣCL represents the external capacitive output load, N is the number of active outputs (N is always 12 in case of the PCS2I99448). The PCS2I99448 supports driving transmission lines to maintain high signal integrity and tight timing parameters. Any transmission line will hide the lumped capacitive load at the end of the board trace, therefore, ΣCL is zero for controlled transmission line systems and can be eliminated from equation 1. Using parallel termination output termination results in equation 2 for power dissipation. Z0=50Ω 17Ω + 16Ω || 16Ω = 50Ω || 50Ω 25Ω = 25Ω Figure 4. Optimized Dual Line Termination Power Consumption of the PCS299448 and Thermal Management The PCS2I99448 AC specification is guaranteed for the entire operating frequency range up to 350MHz. The PCS2I99448 power consumption and the associated long-term reliability may decrease the maximum frequency limit, depending on operating conditions such as clock frequency, supply voltage, output loading, ambient temperature, vertical convection and thermal conductivity of package and board. This section describes the impact of these parameters on the junction temperature and gives a guideline to estimate the PCS2I99448 die junction temperature and the associated device reliability. In equation 2, P stands for the number of outputs with a parallel or thevenin termination, VOL, IOL, VOH and IOH are a function of the output termination technique and DCQ is the clock signal duty cycle. If transmission lines are used ΣCL is zero in equation 2 and can be eliminated. In general, the use of controlled transmission line techniques eliminates the impact of the lumped capacitive loads at the end lines and greatly reduces the power dissipation of the device. Equation 3 describes the die junction temperature TJ as a function of the power consumption. Table 9. Die junction temperature and MTBF Junction temperature (°C) MTBF (Years) 100 20.4 110 9.1 120 130 4.2 2.0 Where Rthja is the thermal impedance of the package (junction to ambient) and TA is the ambient temperature. According to Table 9, the junction temperature can be used to estimate the long-term device reliability. Further, combining equation 1 and equation 2 results in a maximum operating frequency for the PCS2I99448 in a series terminated transmission line system, equation 4. PTOT = I CCQ + VCC ⋅ f CLOCK ⋅ N ⋅ C PD + ∑ C L ⋅ VCC M Equation 1 PTOT = VCC ⋅ I CCQ + VCC ⋅ f CLOCK ⋅ N ⋅ C PD + ∑ C L + ∑ DC Q ⋅ I OH (VCC − VOH ) + (1 − DC Q ) ⋅ I OL ⋅ VOL M P T J = T A + PTOT ⋅ Rthja [ f CLOCKMAX = C PD T − TA 1 ⋅ JMAX − (I CCQ ⋅ VCC ) 2 ⋅ N ⋅ VCC Rthja 3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer Notice: The information in this document is subject to change without notice. ] Equation 2 Equation 3 Equation 4 8 of 15 PCS2I99448 September 2006 rev 0.4 TJ, MAX should be selected according to the MTBF system requirements and Table 9. Rthja can be derived from Table 10. The Rthja represent data based on 1S2P boards, using 2S2P boards will result in lower thermal impedance than indicated below. If the calculated maximum frequency is below 350 MHz, it becomes the upper clock speed limit for the given application conditions. The following eight derating charts describe the safe frequency operation range for the PCS2I99448. The charts were calculated for a maximum tolerable die junction temperature of 110°C (120°C), corresponding to an estimated MTBF of 9.1 years (4 years), a supply voltage of 3.3V and series terminated transmission line or capacitive loading. Depending on a given set of these operating conditions and the available device convection a decision on the maximum operating frequency can be made. Table 10. Thermal package impedance of the 32LQFP Convection, Rthja (1P2S Rthja (2P2S board), °C/W board), °C/W LFPM Still air 100 lfpm 200 lfpm 300 lfpm 400 lfpm 500 lfpm 86 76 71 68 66 60 61 56 54 53 52 49 fMAX (AC) 300 TA = 85°C 250 200 150 Safe operation 100 300 TA = 75°C 250 200 TA = 85°C 150 100 Safe operation 50 50 0 0 500 400 300 200 100 Convection Ifpm 500 0 fMAX (AC) 350 250 200 150 Safe operation 100 300 200 100 Convection Ifpm 0 fMAX (AC) 350 Operating frequency (MHz) 300 400 Figure 6. Maximum PCS2I99448 frequency VCC= 3.3V, MRBF 9.1 years, 4pF load per line, 2s2p board Figure 5. Maximum PCS2I99448 frequency VCC = 3.3V, MTBF 9.1 years, driving series terminated transmission lines, 2s2p board Operating frequency (MHz) fMAX (AC) 350 Operating frequency (MHz) Operating frequency (MHz) 350 50 300 TA = 85°C 250 200 150 Safe operation 100 50 0 0 500 400 300 200 100 Convection Ifpm 0 Figure 7. No maximum frequency limitation for VCC = 3.3V, MTBF 4 years, driving series terminated transmission lines, 2s2p board 500 400 300 200 100 Convection Ifpm 0 Figure 8. Maximum PCS2I99448 frequency VCC = 3.3V, MRBF 4 years, 4pF load per line, 2s2p board 3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer Notice: The information in this document is subject to change without notice. 9 of 15 PCS2I99448 September 2006 rev 0.4 The Following Figures illustrate the Measurement Reference for the PCS2I99448 Clock Driver Circuit Z0=50Ω Z0=50Ω Pulse Generator Z=50Ω RT=50Ω RT=50Ω VTT TT Figure 9. CCLK PCS2I99448 AC Test Reference for VCC = 3.3V and VCC Z0=50Ω Z0=50Ω Differential Pulse Generator Z=50Ω RT=50Ω RT=50Ω VTT VTT Figure 10. PCLK PCS2I99448 AC Test Reference 3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer Notice: The information in this document is subject to change without notice. 10 of 15 PCS2I99448 September 2006 rev 0.4 PCLK VPP PCLK VCC CCLK VCMR VCC ÷2 GND VCC VCC ÷2 QX tP(LH) VCC QX VCC ÷2 GND tP(HL) tP(LH) Figure 11. Propagation Delay (tPD) Test Reference GND tP(HL) Figure 12. Propagation Delay (tPD) Test Reference VCC VCC ÷2 VCC CCLK VCC ÷2 GND GND VCC VCC ÷2 tSK(LH) tSK(HL) GND VCC QX VCC ÷2 tP(LH) The pin-to-pin skew is defined as the worst case difference in propagation between any similar delay path within a single device GND tP(HL) tSK(P) =| tPHL - tPHL | Figure 14. Output Pulse Skew (tSK(P) Test Reference Figure 13. Output–to–Output Skew tSK(LH, HL) VCC VCC ÷2 VCC = 3.3V VCC = 2.5V GND 2.4 0.5 tP tR tF T0 DC (tP ÷T0 Χ 100%) 1.8V 0.6V Figure 16. Output Transition Time Test Reference The time from the output controlled edge to the non-controlled edge, divided by the time output controlled edge, expressed as a percentage. Figure 15. Output Duty Cycle (DC) VCC CCLK PCLK VCC ÷2 GND TJIT(CC) = |TN -TN + 1| TN TN + 1 VCC CLK_STOP The variation in cycle time of a single between adjacent cycles, over a random sample of adjacent cycle pairs VCC ÷2 GND tS tH Figure 17. Cycle–to–Cycle Jitter Reference Figure 18. Setup and Hold Time (tS, tH) Test 3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer Notice: The information in this document is subject to change without notice. 11 of 15 PCS2I99448 September 2006 rev 0.4 Package Information 32-lead TQFP SECTION A-A Symbol Dimensions Inches Millimeters Min Max Min Max A …. 0.0472 … 1.2 A1 0.0020 0.0059 0.05 0.15 A2 0.0374 0.0413 0.95 1.05 9.2 D 0.3465 0.3622 8.8 D1 0.2717 0.2795 6.9 7.1 E 0.3465 0.3622 8.8 9.2 E1 0.2717 0.2795 6.9 7.1 L 0.0177 0.0295 0.45 0.75 L1 0.03937 REF 1.00 REF T 0.0035 0.0079 0.09 0.2 T1 0.0038 0.0062 0.097 0.157 b 0.0118 0.0177 0.30 0.45 b1 0.0118 0.0157 0.30 0.40 R0 0.0031 0.0079 0.08 0.2 a 0° 7° 0° 7° e 0.031 BASE 0.8 BASE 3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer Notice: The information in this document is subject to change without notice. 12 of 15 PCS2I99448 September 2006 rev 0.4 32-lead LQFP SECTION A-A Dimensions Symbol Inches Min Max Millimeters Min Max A …. 0.0630 … 1.6 A1 0.0020 0.0059 0.05 0.15 A2 0.0531 0.0571 1.35 1.45 D 0.3465 0.3622 8.8 9.2 D1 0.2717 0.2795 6.9 7.1 E 0.3465 0.3622 8.8 9.2 E1 0.2717 0.2795 6.9 7.1 L 0.0177 0.0295 0.45 0.75 L1 0.03937 REF 1.00 REF T 0.0035 0.0079 0.09 0.2 T1 0.0038 0.0062 0.097 0.157 b 0.0118 0.0177 0.30 0.45 b1 0.0118 0.0157 0.30 0.40 R0 0.0031 0.0079 0.08 0.20 e a 0.031 BASE 0° 7° 0.8 BASE 0° 7° 3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer Notice: The information in this document is subject to change without notice. 13 of 15 PCS2I99448 September 2006 rev 0.4 Ordering Information Part Number Marking Package Type Operating Range PCS2P99448G-32-LT PCS2P99448GL 32-pin LQFP, Tray, Green PCS2P99448G-32-LR PCS2P99448GL 32-pin LQFP –Tape and Reel, Green Commercial Commercial PCS2P99448G-32-ET PCS2P99448GE 32-pin TQFP, Tray, Green Commercial PCS2P99448G-32-ER PCS2P99448GE 32-pin TQFP –Tape and Reel, Green Commercial PCS2I99448G-32-LT PCS2I99448GL 32-pin LQFP, Tray, Green Industrial PCS2I99448G-32-LR PCS2I99448GL 32-pin LQFP –Tape and Reel, Green Industrial PCS2I99448G-32-ET PCS2I99448GE 32-pin TQFP, Tray, Green Industrial PCS2I99448G-32-ER PCS2I99448GE 32-pin TQFP –Tape and Reel, Green Industrial Device Ordering Information P C S 2 I 9 9 4 4 8 G - 3 2 - L R R = Tape & Reel, T = Tube or Tray O = SOT S = SOIC T = TSSOP A = SSOP V = TVSOP B = BGA Q = QFN U = MSOP E = TQFP L = LQFP U = MSOP P = PDIP D = QSOP X = SC-70 DEVICE PIN COUNT G = GREEN PACKAGE, LEAD FREE, and RoHS PART NUMBER X= Automotive I= Industrial P or n/c = Commercial (-40C to +125C) (-40C to +85C) (0C to +70C) 1 = Reserved 2 = Non PLL based 3 = EMI Reduction 4 = DDR support products 5 = STD Zero Delay Buffer 6 = Power Management 7 = Power Management 8 = Power Management 9 = Hi Performance 0 = Reserved PulseCore Semiconductor Mixed Signal Product Licensed under US patent #5,488,627, #6,646,463 and #5,631,920. 3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer Notice: The information in this document is subject to change without notice. 14 of 15 PCS2I99448 September 2006 rev 0.4 PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200 Campbell, CA 95008 Tel: 408-879-9077 Fax: 408-879-9018 www.pulsecoresemi.com Copyright © PulseCore Semiconductor All Rights Reserved Preliminary Information Part Number: PCS2I99448 Document Version: 0.4 Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to PulseCore Semiconductor, dated 11-11-2003 © Copyright 2006 PulseCore Semiconductor Corporation. All rights reserved. Our logo and name are trademarks or registered trademarks of PulseCore Semiconductor. All other brand and product names may be the trademarks of their respective companies. PulseCore reserves the right to make changes to this document and its products at any time without notice. PulseCore assumes no responsibility for any errors that may appear in this document. The data contained herein represents PulseCore’s best data and/or estimates at the time of issuance. PulseCore reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. PulseCore does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of PulseCore products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in PulseCore’s Terms and Conditions of Sale (which are available from PulseCore). All sales of PulseCore products are made exclusively according to PulseCore’s Terms and Conditions of Sale. The purchase of products from PulseCore does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of PulseCore or third parties. PulseCore does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of PulseCore products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify PulseCore against all claims arising from such use. 3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer Notice: The information in this document is subject to change without notice. 15 of 15