IRF9240 Data Sheet February 1999 -11A, -200V, 0.500 Ohm, P-Channel Power MOSFET This P-Channel enhancement mode silicon gate power field effect transistor is an advanced power MOSFET designed, tested, and guaranteed to withstand a specified level of energy in the breakdown avalanche mode of operation. All of these power MOSFETs are designed for applications such as switching regulators, switching convertors, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. These types can be operated directly from integrated circuits. Formerly developmental type TA17522. Ordering Information PART NUMBER IRF9240 2279.2 Features • -11A, -200V • rDS(ON) = 0.500Ω • Single Pulse Avalanche Energy Rated • SOA is Power Dissipation Limited • Nanosecond Switching Speeds • Linear Transfer Characteristics • High Input Impedance • Related Literature - TB334, “Guidelines for Soldering Surface Mount Components to PC Boards” Symbol PACKAGE TO-204AA File Number BRAND D IRF9240 NOTE: When ordering, use the entire part number. G S Packaging JEDEC TO-204AA DRAIN (FLANGE) SOURCE (PIN 2) GATE (PIN 1) 5-26 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 IRF9240 Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified Drain to Source Breakdown Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulse Avalanche Energy Rating (Note 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG aximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tpkg IRF9240 -200 -200 -11 -7 -44 ±20 125 1 790 -55 to 150 UNITS V V A A A V W W/oC mJ oC 300 260 oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to TJ = 125oC. Electrical Specifications TC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS -200 - - V VGS = VDS, ID = -250µA -2 - -4 V VDS = Rated BVDSS, VGS = 0V - - -25 µA - - -250 µA -11 - - A Drain to Source Breakdown Voltage BVDSS ID = -250µA, VGS = 0V, (Figure10) Gate Threshold Voltage VGS(TH) Zero Gate Voltage Drain Current IDSS VDS = 0.8 x Rated BVDSS, VGS = 0V, TC = 125oC On-State Drain Current (Note 2) Gate to Source Leakage Current On Resistance (Note 2) ID(ON) IGSS rDS(ON) Forward Transconductance (Note 2) Turn-On Delay Time gfs td(ON) Rise Time tr Turn-Off Delay Time td(OFF) Fall Time tf Total Gate Charge (Gate to Source + Gate to Drain) Qg(TOT) VDS > ID(ON) x rDS(ON)MAX, VGS = -10V, (Figure 7) VGS = ±20V - - ±100 nA ID = -6A, VGS = -10V, (Figures 8, 9) - 0.35 0.500 Ω VDS > ID(ON) x rDS(ON)MAX, ID = -6A, (Figure 12) 4 6 - S VDD = 1.00 x Rated BVDSS, ID ≈ 11A, RG = 9.1Ω, VGS = 10V, (Figure 17, 18) RL = 17.5Ω for BVDSS = 150V RL = 9.6Ω for BVDSS = 200V MOSFET Switching Times are Essentially Independent of Operating Temperature - 18 22 ns - 45 68 ns - 75 90 ns - 29 44 ns VGS = -10V, ID = -11A, VDS = 0.8 x Rated BVDSS, (Figures 14, 19, 20)) Gate Charge is Essentially Independent of Operating Temperature - 70 90 nC - 55 - nC - 15 - nC VDS = -25V, VGS = 0V, f = 1MHz, (Figure 11) - 1100 - pF pF Gate to Source Charge Qgs Gate to Drain “Miller” Charge Qgd Input Capacitance CISS Output Capacitance COSS - 375 - Reverse Transfer Capacitance CRSS - 150 - pF - 5.0 - nH - 12.5 - nH - - 1 oC/W - - 62.5 oC/W Internal Drain Inductance LD Measured Between the Contact Screw on the Flange that is Closer to Source and Gate Pins and the Center of Die Internal Source Inductance LS Measured From the Source Lead, 6mm (0.25in) From the Flange and the Source Bonding Pad Modified MOSFET Symbol Showing the Internal Devices Inductances D LD G LS S Thermal Resistance Junction to Case RθJC Thermal Resistance Junction to Ambient RθJA 5-27 Typical Socket Mount IRF9240 Source to Drain Diode Specifications PARAMETER SYMBOL Continuous Source to Drain Current Pulse Source to Drain Current (Note 3) MIN TYP MAX UNITS - - -11 A - - -44 A VSD TC = 25oC, ISD = -11A, VGS = 0V, (Figure13) - - -1.5 V trr TJ = 150oC, ISD = -11A, dISD/dt = 100A/µs - 270 - ns QRR TJ = 150oC, ISD = -11A, dISD/dt = 100A/µs - 2 - µC ISD ISDM TEST CONDITIONS Modified MOSFET Symbol Showing the Integral Reverse P-N Junction Diode D G S Source to Drain Diode Voltage (Note 2) Reverse Recovery Time Reverse Recovery Charge NOTES: 2. Pulse test: pulse width ≤ 300µs, duty cycle ≤ 2%. 3. Repetitive rating: pulse width limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3). 4. VDD = 50V, starting TJ = 25oC, L = 9.8mH, RG = 25Ω, peak IAS = 11A (Figures 15, 16). Typical Performance Curves Unless Otherwise Specified -15 ID, DRAIN CURRENT (A) 1.0 0.8 0.6 0.4 -10 -5 0.2 0 0.0 0 25 50 75 100 TA , CASE TEMPERATURE (oC) 125 0 150 50 100 150 TC, CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE ZθJC, NORMALIZED TRANSIENT THERMAL IMPEDANCE POWER DISSIPATION MULTIPLIER 1.2 FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 1 0.5 0.2 PDM 0.1 0.1 0.05 0.02 0.01 0.01 10-5 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJC x RθJC + TC SINGLE PULSE 10-4 10-3 10-2 10-1 t 1, RECTANGULAR PULSE DURATION (s) FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE 5-28 1 10 IRF9240 Typical Performance Curves Unless Otherwise Specified (Continued) -100 -50 VGS = -10V ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) VGS = -11V 10µs 100µs 1ms -10 10ms OPERATION IN THIS AREA IS LIMITED BY rDS(ON) -1 -0.1 -1 100ms DC TC = 25oC TJ = MAX RATED SINGLE PULSE 80µs PULSE TEST VGS = -9V -40 -30 VGS = -8V -20 VGS = -7V VGS = -6V -10 -10 -100 VDS, DRAIN TO SOURCE VOLTAGE (V) 0 -1000 -16 -12 VGS = -6V -8 VGS = -5V -4 ID(ON), ON-STATE DRAIN CURRENT (A) ID, DRAIN CURRENT (A) VGS = -7V VGS = -4V -40 -50 80µs PULSE TEST VDS ≥ I D(ON) x rDS(ON)MAX -10 125oC 25oC -1.0 -55oC -0.1 0 -4 -2 -6 -8 -10 -2 -4 -6 -8 VGS, GATE TO SOURCE VOLTAGE (V) 0 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 6. SATURATION CHARACTERISTICS 0.8 2.5 5µs PULSE TEST VGS = -10V, ID = -11A 0.7 VGS = -10V 0.6 0.5 0.4 0.3 VGS = - 20V 0.2 0 0 -15 -10 FIGURE 7. TRANSFER CHARACTERISTICS NORMALIZED DRAIN TO SOURCE ON RESISTANCE DRAIN TO SOURCE ON RESISTANCE (Ω) -30 FIGURE 5. OUTPUT CHARACTERISTICS VGS = -8V VGS = -9V 0 -20 100 VGS = -10V 80µs PULSE TEST -10 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 4. FORWARD BIAS SAFE OPERATING AREA -20 VGS = -4V VGS = -5V -30 -45 -60 -75 ID, DRAIN CURRENT (A) 2.0 1.5 1.0 0.5 0 -40 0 40 80 120 160 TJ , JUNCTION TEMPERATURE (oC) NOTE: Heating effect of 5µs pulse is minimal. FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT 5-29 FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE IRF9240 Typical Performance Curves Unless Otherwise Specified (Continued) 2000 1.10 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS ≈ CDS + CGD ID = 250µA 1600 C, CAPACITANCE (pF) NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 1.15 1.05 1.00 0.95 1200 CISS 800 COSS 400 0.90 CRSS 0.85 -80 -40 0 40 80 120 0 160 10 0 TJ , JUNCTION TEMPERATURE (oC) 30 40 50 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE 10 -100 ISD, SOURCE TO DRAIN CURRENT (A) 80µs PULSE TEST gfs, TRANSCONDUCTANCE (S) 20 TJ = -55oC 8 TJ = 25oC TJ = 125oC 6 4 2 0 0 -10 -20 -30 I D , DRAIN CURRENT (A) -40 TJ = 25oC -1.0 -0.1 -0.4 -50 FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT -0.6 -0.8 -1.4 -1.0 -1.2 -1.6 VSD, SOURCE TO DRAIN VOLTAGE (V) FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE 0 VGS, GATE TO SOURCE (V) TJ = 150oC -10 ID = -11A FOR TEST CIRCUIT SEE FIGURES 19, 20 -5 VDS = -40V VDS = -100V VDS = -160V -10 0 20 40 60 80 Qg(TOT), TOTAL GATE CHARGE (nC) FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE 5-30 -1.8 IRF9240 Test Circuits and Waveforms VDS tAV L 0 VARY tP TO OBTAIN - RG REQUIRED PEAK IAS + VDD DUT 0V VDD tP VGS IAS IAS VDS tP 0.01Ω BVDSS FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS tON tOFF td(OFF) td(ON) tr 0 RL - DUT VGS + 10% 10% VDS VDD RG tf VGS 0 90% 90% 10% 50% 50% PULSE WIDTH 90% FIGURE 17. SWITCHING TIME TEST CIRCUIT FIGURE 18. RESISTIVE SWITCHING WAVEFORMS -VDS (ISOLATED SUPPLY) CURRENT REGULATOR 0 VDS DUT 12V BATTERY 0.2µF 50kΩ 0.3µF Qgs Qg(TOT) DUT G VGS Qgd D VDD 0 S IG(REF) IG CURRENT SAMPLING RESISTOR +VDS ID CURRENT SAMPLING RESISTOR FIGURE 19. GATE CHARGE TEST CIRCUIT 5-31 0 IG(REF) FIGURE 20. GATE CHARGE WAVEFORMS IRF9240 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. 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