RFG50N05L, RFP50N05L Data Sheet 50A, 50V, 0.022 Ohm, Logic Level, N-Channel Power MOSFETs These are logic-level N-channel power MOSFETs manufactured using the MegaFET process. This process, which uses feature sizes approaching those of LSI integrated circuits gives optimum utilization of silicon, resulting in outstanding performance. They were designed for use with logic-level (5V) driving sources in applications such as programmable controllers, automotive switching, switching regulators, switching converters, motor relay drivers and emitter switches for bipolar transistors. This performance is accomplished through a special gate oxide design which provides full rated conductance at gate bias in the 3V - 5V range, thereby facilitating true on-off power control directly from integrated circuit supply voltages. File Number 2424.3 Features • 50A, 50V • rDS(ON) = 0.022Ω • UIS SOA Rating Curve (Single Pulse) • Design Optimized for 5V Gate Drive • Can be Driven Directly from CMOS, NMOS, TTL Circuits • Compatible with Automotive Drive Requirements • SOA is Power Dissipation Limited • Nanosecond Switching Speeds • Linear Transfer Characteristics • High Input Impedance • Majority Carrier Device Formerly developmental type TA09872. Ordering Information PART NUMBER July 1999 PACKAGE BRAND RFG50N05L TO-247 RFG50N05L RFP50N05L TO-220AB RFP50N05L • Related Literature - TB334 “Guidelines for Soldering Surface Mount Components to PC Boards” Symbol D NOTE: When ordering, use the entire part number. Add the suffix 9A to obtain the TO-263AB variant in the tape and reel, i.e., RFP50N05L9A. G S Packaging JEDEC STYLE TO-247 JEDEC TO-220AB SOURCE DRAIN GATE DRAIN (BOTTOM SIDE METAL) SOURCE DRAIN GATE DRAIN (FLANGE) 6-212 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 RFG50N05L, RFP50N05L Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified RFG50N05L RFP50N05L UNITS Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS 50 50 V Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . VDGR 50 50 V Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM 50 130 50 130 A A Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS ±10 ±10 V Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Above TC = 25oC, Derate Linearly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 0.88 110 0.88 W W/oC Single Pulse Avalanche Energy Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Refer to UIS SOA Curve - Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG -55 to 150 -55 to 150 oC Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . .TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg 300 260 300 260 oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC. Electrical Specifications TC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Drain to Source Breakdown Voltage BVDSS ID = 250µA, VGS = 0V (Figure 10) 50 - - V Gate Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA (Figure 9) 1 - 2 V VDS = Rated BVDSS, VGS = 0 - - 25 µA VDS = 0.8 x Rated BVDSS, VGS = 0, TC = 150oC - - 250 µA VGS = ±10V, VDS = 0V - - ±100 nA ID = 50A, VGS = 5V (Figure 7) - - 0.022 Ω ID = 50A, VGS = 4V - - 0.027 Ω VGS = 5V, RGS = 2.5Ω, RL = 1Ω (Figures 12, 15, 16) - - 100 ns - 15 - ns tr - 50 - ns tD(OFF) - 50 - ns tf - 15 - ns t(OFF) - - 100 ns - - 140 nC - - 80 nC - - 6 nC Zero Gate Voltage Drain Current IDSS Gate to Source Leakage Current IGSS Drain to Source On Resistance (Note 2) rDS(ON) Turn-On Time t(ON) Turn-On Delay Time tD(ON) Rise Time Turn-Off Delay Time Fall Time Turn-Off Time Total Gate Charge QG(TOT) VGS = 0 to 10V Gate Charge at 5V QG(5) VGS = 0 to 5V Threshold Gate Charge QG(th) VGS = 0 to 1V VDD = 40V, ID = 50A RL = 0.8Ω (Figures 17, 18) Thermal Resistance Junction to Case RθJC - - 1.14 oC/W Thermal Resistance Junction to Ambient RθJA - - 80 oC/W Source to Drain Diode Specifications PARAMETER SYMBOL Source to Drain Diode Voltage (Note 2) Diode Reverse Recovery Time VSD trr TEST CONDITIONS MIN TYP MAX UNITS ISD = 50A - - 1.5 V ISD = 50A, dISD/dt = 100A/µs - - 1.25 ns NOTES: 2. Pulsed: pulse duration = 300µs maximum, duty cycle = 2%. 3. Repititive rating: pulse width limited by maximum junction temperature. 6-213 RFG50N05L, RFP50N05L Typical Performance Curves 50 POWER DISSIPATION MULTIPLIER 1.2 1.0 ID, DRAIN CURRENT (A) 40 0.8 0.6 0.4 30 20 10 0.2 0 25 0 0 25 50 75 100 125 150 50 TC, CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE 1000 TC = 25oC TJ = MAX RATED ID MAX CONTINUOUS DC OPERATION 10 OPERATION IN THIS AREA LIMITED BY rDS(ON) 1 0.1 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V) PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX. TC - 25oC VGS = 5V VGS = 4V 80 60 VGS = 3V 40 20 VGS = 2V 0 0 1.5 3.0 4.5 6.0 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 5. SATURATION CHARACTERISTICS 6-214 IDM 100 STARTING TJ = 25oC STARTING TJ = 150oC 0.1 1 10 FIGURE 4. UNCLAMPED INDUCTIVE SWITCHING SAFE OPERATING AREA ID(ON), DRAIN TO SOURCE CURRENT (A) IDS, DRAIN TO SOURCE CURRENT (A) 100 150 tAV, TIME IN AVALANCHE (ms) 140 VGS = 10V 125 IF R = 0 tAV = (L) (IAS) / (1.3 RATED BVDSS - VDD) IF R = 0 TAV = (L/R) IN [(IAS*R) / (1.3 RATED BVDSS - VDD) + 1] 10 0.01 100 FIGURE 3. FORWARD BIAS SAFE OPERATING AREA 120 100 FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE IAS, AVALANCHE CURRENT (A) IDS, DRAIN TO SOURCE CURRENT (A) 100 75 TC, CASE TEMPERATURE (oC) 7.5 140 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX. TC - 25oC 120 150oC 100 VDS = 15V 80 -55oC 25oC 60 40 20 0 0 1.5 3.0 4.5 6.0 VGS, GATE TO SOURCE VOLTAGE (V) FIGURE 6. TRANSFER CHARACTERISTICS 7.5 RFG50N05L, RFP50N05L Typical Performance Curves (Continued) 2.0 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX. VGS = 5V ID = 50A 2.5 NORMALIZED DRAIN TO SOURCE ON RESISTANCE 2.0 1.5 1.0 0.5 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX. ID = 50A, VGS = 5V 1.5 1.2 0.8 0.4 0 0 -50 0 50 100 150 4 5 6 VGS, GATE TO SOURCE VOLTAGE (V) TJ, JUNCTION TEMPERATURE (oC) FIGURE 7. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE FIGURE 8. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE 2.0 2.0 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE VGS = VDS, ID = 250µA NORMALIZED GATE THRESHOLD VOLTAGE 1.8 1.2 0.8 0.4 0 -50 0 50 100 TJ, JUNCTION TEMPERATURE (oC) 1.8 1.2 0.8 0.4 0 -50 0 50 DRAIN TO SOURCE VOLTAGE (V) 4000 100 CISS 3000 2000 COSS 1000 10 RL = 0Ω IG(REF) = 1.25mA 37.5 VDD = BVDSS 25 0.75BVDSS VDD = BVDSS 0.75BVDSS 5 GATE TO SOURCE VOLTAGE 0.50BVDSS 12.5 0.50BVDSS 0.25BVDSS 0.25BVDSS DRAIN TO SOURCE VOLTAGE CRSS 0 0 0 5 10 15 20 150 FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS ≈ CDS + CGD 5000 50 TJ, JUNCTION TEMPERATURE (oC) 6000 C, CAPACITANCE (pF) ID = 250µA 150 FIGURE 9. NORMALIZED GATE THRESHOLD VOLTAGE 0 7 25 VDS, DRAIN TO SOURCE (V) 20 IG(REF) IG(ACT) TIME-MICROSECONDS 80 IG(REF) IG(ACT) NOTE: Refer to Intersil Application Notes AN7254 and AN7260. FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE 6-215 FIGURE 12. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT GATE TO SOURCE VOLTAGE (V) NORMALIZED DRAIN TO SOURCE ON RESISTANCE 3.0 RFG50N05L, RFP50N05L Test Circuits and Waveforms VDS BVDSS L tP VARY tP TO OBTAIN REQUIRED PEAK IAS IAS + RG VDS VDD VDD - VGS DUT tP 0V IAS 0 0.01Ω tAV FIGURE 13. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 14. UNCLAMPED ENERGY WAVEFORMS tON tOFF td(ON) VDS td(OFF) tf tr VDS 90% 90% RL VGS + - DUT 10% 10% 0 VDD 90% RGS VGS VGS 0 FIGURE 15. SWITCHING TIME TEST CIRCUIT 50% 50% PULSE WIDTH 10% FIGURE 16. RESISTIVE SWITCHING WAVEFORMS VDS VDD RL Qg(TOT) VDS VGS = 10V VGS Qg(5) + VDD DUT IG(REF) VGS = 5V VGS - VGS = 1V 0 Qg(TH) IG(REF) 0 FIGURE 17. GATE CHARGE TEST CIRCUIT 6-216 FIGURE 18. GATE CHARGE WAVEFORMS RFG50N05L, RFP50N05L All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. 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