RFD20N03, RFD20N03SM
Data Sheet
20A, 30V, 0.025 Ohm, N-Channel Power
MOSFETs
The RFD20N03 and RFD20N03SM N-Channel power
MOSFETs are manufactured using the MegaFET process.
This process which uses feature sizes approaching those of
LSI integrated circuits, gives optimum utilization of silicon,
resulting in outstanding performance. They were designed
for use in applications such as switching regulators,
switching converters, motor drivers, and relay drivers. These
transistors can be operated directly from integrated circuits.
Formerly developmental type TA49235.
PACKAGE
File Number
4350.1
Features
• 20A, 30V
• rDS(ON) = 0.025Ω
• Temperature Compensating PSPICE® Model
• Thermal Impedance SPICE Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• 175oC Operating Temperature
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Ordering Information
PART NUMBER
July 1999
BRAND
RFD20N03
TO-251AA
F20N03
RFD20N03SM
TO-252AA
F20N03
Symbol
D
NOTE: When ordering, use the entire part number. Add the suffix 9A to
obtain the TO-252AA variant in tape and reel, e.g., RFD20N03SM9A.
G
S
Packaging
JEDEC TO-251AA
JEDEC TO-252AA
SOURCE
DRAIN
GATE
DRAIN
(FLANGE)
GATE
SOURCE
4-427
DRAIN
(FLANGE)
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
PSPICE® is a registered trademark of MicroSim Corporation.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
RFD20N03, RFD20N03SM
Absolute Maximum Ratings
TC = 25oC, Unless Otherwise Specified
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
Drain Current
Continuous (Figure 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM
Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .EAS
Power Dissipation (Figure 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PD
Derate Above 25oC (Figure 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL
Package Body for 10s, See Techbrief 334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
UNITS
V
V
V
30
30
±20
20
Figure 5
Figure 6
90
0.60
-55 to 175
A
W
W/oC
oC
300
260
oC
oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ = 25oC to 150oC.
Electrical Specifications
TC = 25oC, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Drain to Source Breakdown Voltage
BVDSS
ID = 250µA, VGS = 0V (Figure 11)
30
-
-
V
Gate to Source Threshold Voltage
VGS(TH)
VGS = VDS, ID = 250µA (Figure 10)
2
-
4
V
VDS = 30V, VGS = 0V
-
-
1
µA
VDS = 30V, VGS = 0V, TC = 150oC
-
-
50
µA
VGS = ±20V
-
-
100
nA
ID = 20A, VGS = 10V (Figure 9)
-
0.022
0.025
Ω
VDD = 15V, ID ≅ 20A,
RL =0.75Ω, VGS = 10V,
RGS = 9.1Ω
-
-
60
ns
-
10
-
ns
tr
-
30
-
ns
td(OFF)
-
12
-
ns
tf
-
32
-
ns
tOFF
-
-
66
ns
-
60
75
nC
-
28
40
nC
-
2.4
2.9
nC
-
1150
-
pF
-
550
-
pF
-
110
-
pF
Zero Gate Voltage Drain Current
IDSS
Gate to Source Leakage Current
Drain to Source On Resistance
IGSS
rDS(ON)
Turn-On Time
tON
Turn-On Delay Time
td(ON)
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
Total Gate Charge
Qg(TOT)
VGS = 0V to 20V
Gate Charge at 10V
Qg(10)
VGS = 0V to 10V
Threshold Gate Charge
Qg(TH)
VGS = 0V to 2V
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
VDD = 15V, ID ≅ 20A,
RL = 0.75Ω
Ig(REF) = 1.0mA
(Figure 13)
VDS = 25V, VGS = 0V, f = 1MHz
(Figure 12)
Thermal Resistance Junction to Case
RθJC
(Figure 3)
-
-
1.66
oC/W
Thermal Resistance Junction to Ambient
RθJA
TO-251, TO-252
-
-
100
oC/W
MIN
TYP
MAX
UNITS
ISD = 20A
-
-
1.25
V
trr
ISD = 20A, dISD/dt = 100A/µs
-
-
70
ns
QRR
ISD = 20A, dISD/dt = 100A/µs
-
-
145
nC
Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage
Reverse Recovery Time
Reverse Recovered Charge
4-428
SYMBOL
VSD
TEST CONDITIONS
RFD20N03, RFD20N03SM
Typical Performance Curves
25
POWER DISSIPATION MULTIPLIER
1.2
ID, DRAIN CURRENT (A)
1.0
0.8
0.6
0.4
0.2
20
15
10
5
0
0
0
25
50
75
100
125
TC , CASE TEMPERATURE (oC)
150
25
175
50
75
100
125
150
175
TC, CASE TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
2
THERMAL IMPEDANCE
ZθJC, NORMALIZED
1
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
PDM
0.1
t1
t2
SINGLE PULSE
0.01
10-5
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
10-4
10-2
10-3
10-1
t, RECTANGULAR PULSE DURATION (s)
100
101
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
500
TJ = MAX RATED
TC = 25oC
100
100µs
1ms
10
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
VGS = 20V
IDM, PEAK CURRENT (A)
ID, DRAIN CURRENT (A)
500
10ms
100ms
DC
TC = 25oC FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
I
100
= I25
175 - TC
150
VGS = 10V
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
VDSS(MAX) = 30V
1
1
10
VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
4-429
100
10
10-5
10-4
10-3
10-2
10-1
100
t, PULSE WIDTH (s)
FIGURE 5. PEAK CURRENT CAPABILITY
101
RFD20N03, RFD20N03SM
Typical Performance Curves
100
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) + 1]
VGS = 20V
VGS = 10V
ID, DRAIN CURRENT (A)
IAS, AVALANCHE CURRENT (A)
300
(Continued)
100
STARTING TJ = 25oC
STARTING TJ = 150oC
10
0.001
1
0.01
0.1
tAV, TIME IN AVALANCHE (ms)
80
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TC = 25oC
VGS = 7V
60
40
VGS = 6V
20
VGS = 5V
0
10
0
1
2
3
4
5
VDS, DRAIN TO SOURCE VOLTAGE (V)
NOTE: Refer to Intersil Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY
80
2.0
-55oC
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
25oC
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
ID(ON), ON-STATE DRAIN CURRENT (A)
100
FIGURE 7. SATURATION CHARACTERISTICS
175oC
60
40
20
2
4
6
8
1.5
1.0
0.5
-80
0
0
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VGS = 10V, ID = 20A
10
-40
FIGURE 8. TRANSFER CHARACTERISTICS
80
120
160
200
1.2
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
VGS = VDS, ID = 250µA
NORMALIZED GATE
THRESHOLD VOLTAGE
40
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
1.2
1.0
0.8
0.6
0.4
-80
0
TJ, JUNCTION TEMPERATURE (oC)
VGS, GATE TO SOURCE VOLTAGE (V)
-40
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (oC)
200
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
4-430
ID = 250µA
1.1
1.0
0.9
0.8
-80
-40
0
40
80
120
160
TJ , JUNCTION TEMPERATURE (oC)
200
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
RFD20N03, RFD20N03SM
Typical Performance Curves
(Continued)
10
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS ≈ CDS + CGD
C, CAPACITANCE (pF)
1500
CISS
1200
900
COSS
600
CRSS
300
VGS , GATE TO SOURCE VOLTAGE (V)
1800
0
0
10
20
VDD = 15V
8
6
4
2
0
30
WAVEFORMS IN
DESCENDING ORDER:
ID = 20A
ID = 15A
ID = 10A
ID = 5A
0
6
VDS , DRAIN TO SOURCE VOLTAGE (V)
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
12
18
Qg, GATE CHARGE (nC)
24
30
FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT
Test Circuits and Waveforms
VDS
BVDSS
L
tP
VARY tP TO OBTAIN
REQUIRED PEAK IAS
IAS
+
RG
VDS
VDD
VDD
-
VGS
DUT
tP
0V
IAS
0
0.01Ω
tAV
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
VDS
VDD
RL
Qg(TOT)
VDS
VGS = 20V
VGS
Qg(10)
+
VDD
DUT
Ig(REF)
VGS = 10V
VGS
-
VGS = 2V
0
Qg(TH)
Ig(REF)
0
FIGURE 16. GATE CHARGE TEST CIRCUIT
4-431
FIGURE 17. GATE CHARGE WAVEFORM
RFD20N03, RFD20N03SM
Test Circuits and Waveforms
(Continued)
tON
VDS
tOFF
td(ON)
td(OFF)
tf
tr
RL
VDS
90%
90%
+
VGS
-
VDD
10%
10%
0
90%
DUT
RGS
VGS
VGS
0
FIGURE 18. SWITCHING TIME TEST CIRCUIT
4-432
10%
50%
50%
PULSE WIDTH
FIGURE 19. RESISTIVE SWITCHING WAVEFORMS
RFD20N03, RFD20N03SM
PSPICE Electrical Model
SUBCKT RFD20N03, RFD20N03SM 2 1 3 ;
rev 28 Jul 97
CA 12 8 1.3e-9
CB 15 14 1.3e-9
CIN 6 8 9.9e-10
LDRAIN
DPLCAP
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
DRAIN
2
5
10
RLDRAIN
RSLC1
51
5
51
ESLC
11
-
RDRAIN
6
8
ESG
EVTHRES
+ 19 8
+
LGATE
GATE
1
LDRAIN 2 5 1.00e-9
LGATE 1 9 3.57e-9
LSOURCE 3 7 4.25e-9
+
17
EBREAK 18
50
-
IT 8 17 1
EVTEMP
RGATE +
18 22
9
20
21
DBODY
-
16
MWEAK
6
MMED
MSTRO
RLGATE
LSOURCE
CIN
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
8
SOURCE
3
7
RSOURCE
RLSOURCE
S1A
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 5e-4
RGATE 9 20 1.24
RLDRAIN 2 5 10
RLGATE 1 9 28.6
RLSOURCE 3 7 26.9
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 6.2e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A
S1B
S2A
S2B
+
RSLC2
EBREAK 11 7 17 18 33.15
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
DBREAK
12
S2A
13
8
S1B
CA
RBREAK
15
14
13
17
18
RVTEMP
S2B
13
CB
6
8
VBAT
5
8
EDS
-
-
IT
14
+
+
EGS
19
-
+
8
22
RVTHRES
6 12 13 8 S1AMOD
13 12 13 8 S1BMOD
6 15 14 13 S2AMOD
13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*120),3))}
.MODEL DBODYMOD D (IS = 9e-13 RS = 6.4e-3 IKF=7.4 TIKF=0.005 N=1.02 TRS1 = 3.5e-3 TRS2 =-1e-5 CJO = 1.78e-9 TT = 4.0e-8 M = 0.4053)
.MODEL DBREAKMOD D (RS = 0.1 N=3.5 IKF=-1e-3 TRS1 = -1e-3 TRS2 =1e-6)
.MODEL DPLCAPMOD D (CJO = 1.3e-9 IS = 1e-30 N = 10 M = 0.62)
.MODEL MMEDMOD NMOS (VTO = 3.17 KP = 1.3 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 1.24)
.MODEL MSTROMOD NMOS (VTO = 3.68 KP = 13 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 2.68 KP = 0.009 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 12.4 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 8e-4 TC2 = 4.5e-7)
.MODEL RDRAINMOD RES (TC1 = 3.5e-2 TC2 = 4.5e-4)
.MODEL RSLCMOD RES (TC1 = 1e-3 TC2 = 1e-6)
.MODEL RSOURCEMOD RES (TC1 = 0 TC2 = 0)
.MODEL RVTHRESMOD RES (TC = -1.2e-3 TC2 = -2e-5)
.MODEL RVTEMPMOD RES (TC1 = -3.5e-3 TC2 = 1e-7)
.MODEL S1AMOD VSWITCH (RON = 1e-5
.MODEL S1BMOD VSWITCH (RON = 1e-5
.MODEL S2AMOD VSWITCH (RON = 1e-5
.MODEL S2AMOD VSWITCH (RON = 1e-5
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
VON = -8.60 VOFF= -2.50)
VON = -2.50 VOFF= -8.60)
VON = 0.00 VOFF= 0.30)
VON = 0.30 VOFF= 0.00)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
4-433
RFD20N03, RFD20N03SM
SPICE Thermal Model
7
REV 28 July 97
JUNCTION
RFD20N03, RFD20N03SM
CTHERM1 7 6 9.9e-7
CTHERM2 6 5 1.5e-3
CTHERM3 5 4 2.2e-3
CTHERM4 4 3 5.7e-3
CTHERM5 3 2 7.5e-2
CTHERM6 2 1 5.4e-1
RTHERM1
CTHERM1
6
RTHERM1 7 6 8e-3
RTHERM2 6 5 2.3e-2
RTHERM3 5 4 9.0e-2
RTHERM4 4 3 6.9e-1
RTHERM5 3 2 6.1e-1
RTHERM6 2 1 8.0e-2
RTHERM2
CTHERM2
5
RTHERM3
CTHERM3
4
RTHERM4
CTHERM4
3
RTHERM5
CTHERM5
2
RTHERM6
CTHERM6
1
CASE
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
4-434