IRF740 Data Sheet July 1999 10A, 400V, 0.550 Ohm, N-Channel Power MOSFET This N-Channel enhancement mode silicon gate power field effect transistor is an advanced power MOSFET designed, tested, and guaranteed to withstand a specified level of energy in the breakdown avalanche mode of operation. All of these power MOSFETs are designed for applications such as switching regulators, switching converters, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. They can be operated directly from integrated circuits. Ordering Information IRF740 PACKAGE TO-220AB 2311.3 Features • 10A, 400V • rDS(ON) = 0.550Ω • Single Pulse Avalanche Energy Rated • SOA is Power Dissipation Limited • Nanosecond Switching Speeds • Linear Transfer Characteristics • High Input Impedance • Related Literature - TB334 “Guidelines for Soldering Surface Mount Components to PC Boards” Formerly developmental type TA17424. PART NUMBER File Number BRAND Symbol D IRF740 NOTE: When ordering, include the entire part number. G S Packaging JEDEC TO-220AB TOP VIEW SOURCE DRAIN GATE DRAIN (FLANGE) 4-239 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 IRF740 Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulse Avalanche Energy Rating (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg IRF740 400 400 10 6.3 40 ±20 125 1.0 520 -55 to 150 UNITS V V A A A V W W/oC mJ oC 300 260 oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC. Electrical Specifications TC = 25oC, Unless Otherwise Specified MIN TYP MAX UNITS Drain to Source Breakdown Voltage PARAMETER SYMBOL BVDSS VGS = 0V, ID = 250µA (Figure 10) 400 - - V Gate to Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA 2.0 - 4.0 V - - 25 µA - - 250 µA 10 - - A Zero Gate Voltage Drain Current IDSS TEST CONDITIONS VDS = Rated BVDSS, VGS = 0V VDS = 0.8 x Rated BVDSS, VGS = 0V, TJ = 125oC On-State Drain Current (Note 2) Gate to Source Leakage Current Drain to Source On Resistance (Note 2) Forward Transconductance (Note 2) Turn-On Delay Time ID(ON) IGSS rDS(ON) gfs tD(ON) Rise Time tr Turn-Off Delay Time tD(OFF) Fall Time VDS > ID(ON) x rDS(ON)MAX , VGS = 10V VGS = ±20V - - ±500 nA VGS = 10V, ID = 5.2A (Figures 8, 9) - 0.47 0.550 Ω 5.8 8.9 - S - 15 21 ns - 25 41 ns - 52 75 ns - 25 36 ns - 41 63 nC - 6.5 - nC - 23 - nC - 1250 - pF VDS ≥ 50V, ID = 5.2A (Figure 12) VDD = 200V, ID ≈ 10A, RG = 9.1Ω, RL = 20Ω, VGS = 10V MOSFET Switching Times are Essentially Independent of Operating Temperature tf Total Gate Charge (Gate to Source + Gate to Drain) Gate to Source Charge Qg(TOT) Qgs VGS = 10V, ID = 10A, VDS = 0.8 x Rated BVDSS Ig(REF) = 1.5mA (Figure 14) Gate Charge is Essentially Independent of Operating Temperature Gate to Drain “Miller” Charge Qgd Input Capacitance CISS Output Capacitance COSS - 300 - pF Reverse-Transfer Capacitance CRSS - 80 - pF Modified MOSFET Symbol Showing the Internal Devices Measured From the Drain Inductances D Lead, 6mm (0.25in) From Package to Center of Die LD - 3.5 - nH - 4.5 - nH Measured From the Source Lead, 6mm (0.25in) From Header to Source Bonding Pad - 7.5 - nH - - 1.0 oC/W - - 62.5 oC/W Internal Drain Inductance LD Internal Source Inductance LS VGS = 0V, VDS = 25V, f = 1.0MHz (Figure 11) Measured From the Contact Screw on Tab to Center of Die G LS S Thermal Resistance Junction to Case RθCS Thermal Resistance Junction to Ambient RθJA 4-240 Free Air Operation IRF740 Source to Drain Diode Specifications PARAMETER SYMBOL Continuous Source to Drain Current ISD Pulse Source to Drain Current (Note 3) ISDM TEST CONDITIONS Modified MOSFET Symbol Showing the Integral Reverse P-N Junction Diode MIN TYP MAX UNITS - - 10 A - - 40 A - - 2.0 V 170 390 790 ns 1.6 4.5 8.2 µC D G S Source to Drain Diode Voltage (Note 2) VSD Reverse Recovery Time trr Reverse Recovered Charge QRR TJ = 25oC, ISD = 10A, VGS = 0V (Figure 13) TJ = 25oC, ISD = 10A, dISD/dt = 100A/µs TJ = 25oC, ISD = 10A, dISD/dt = 100A/µs NOTES: 2. Pulse Test: Pulse width ≤ 300µs, duty cycle ≤ 2%. 3. Repetitive Rating: Pulse width limited by Max junction temperature. See Transient Thermal Impedance curve (Figure 3). 4. VDD = 50V, starting TJ = 25oC, L = 9.1µH, RG = 25Ω, peak IAS = 10A. Typical Performance Curves Unless Otherwise Specified 10 ID, DRAIN CURRENT (A) 1.0 0.8 0.6 0.4 0.2 0 0 50 100 150 TC , CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE ZθJC, TRANSIENT THERMAL IMPEDANCE POWER DISSIPATION MULTIPLIER 1.2 8 6 4 2 0 25 50 75 100 125 TC , CASE TEMPERATURE (oC) 150 FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 1 0.5 0.2 0.1 0.1 0.05 0.02 0.01 10-2 10-3 10-5 PDM SINGLE PULSE t1 t2t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJC + TC 10-4 0.1 10-2 10-3 t1, RECTANGULAR PULSE DURATION (S) FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE 4-241 1 10 IRF740 Typical Performance Curves Unless Otherwise Specified (Continued) 15 100 ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 10µs 10 100µs 1ms OPERATION IN THIS REGION IS LIMITED BY rDS(ON) 1 10ms TC = 25oC TC = 150oC SINGLE PULSE 0.1 12 VGS = 5.5V 9 VGS = 5.0V 6 VGS = 4.5V 3 DC VGS = 4.0V 102 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 1 0 103 0 40 80 120 160 VDS, DRAIN TO SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A) PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VGS = 10V VGS = 6.0V VGS = 5.5V 12 9 VGS = 5.0V 6 VGS = 4.5V 3 VGS = 4.0V 0 0 2 4 6 8 VDS, DRAIN TO SOURCE VOLTAGE (V) 10 100 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VDS ≥ 50V 10 0.1 0 2 4 6 8 VGS, GATE TO SOURCE VOLTAGE (V) NORMALIZED DRAIN TO SOURCE ON RESISTANCE VOLTAGE ON RESISTANCE rDS(ON), DRAIN TO SOURCE 3.0 4 VGS = 10V 2 VGS = 20V 1 0 25 10 20 30 40 TC , CASE TEMPERATURE (oC) FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT 4-242 10 FIGURE 7. TRANSFER CHARACTERISTICS PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 3 TJ = 25oC TJ = 150oC 1 FIGURE 6. SATURATION CHARACTERISTICS 5 200 FIGURE 5. OUTPUT CHARACTERISTICS IDS(ON), DRAIN TO SOURCE CURRENT (A) FIGURE 4. FORWARD BIAS SAFE OPERATING AREA 15 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VGS = 10V VGS = 6.0V 50 2.4 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX ID = 10A, VGS = 10V 1.8 1.2 0.6 0 -60 -40 -20 0 20 40 60 80 100 120 140 160 TJ, JUNCTION TEMPERATURE (oC) FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE IRF740 Typical Performance Curves Unless Otherwise Specified (Continued) 2500 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS ≈ CDS + CGD ID = 250µA 1.15 2000 C, CAPACITANCE (pF) NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 1.25 1.05 0.95 1500 1000 COSS 0.85 0.75 -60 CISS CRSS 500 -40 -20 0 20 40 60 80 0 100 120 140 160 1 2 TJ, JUNCTION TEMPERATURE (oC) FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE 100 ISD, SOURCE TO DRAIN CURRENT (A) 12 TJ = 25oC 9 TJ = 150oC 6 3 4 8 12 16 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX TJ = 150oC TJ = 25oC 1.0 20 0 0.3 0.6 0.9 1.2 VSD, SOURCE TO DRAIN VOLTAGE (V) ID, DRAIN CURRENT (A) FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT 20 FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE ID = 10A 16 VDS = 80V 12 VDS = 200V VDS = 320V 8 4 0 0 12 24 36 48 60 Qg, GATE CHARGE (nC) FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE 4-243 103 10 0.1 0 0 5 FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VDS ≥ 50V VGS, GATE TO SOURCE VOLTAGE (V) gfs, TRANSCONDUCTANCE (S) 15 10 2 5 2 5 102 VDS , DRAIN TO SOURCE VOLTAGE (V) 1.5 IRF740 Test Circuits and Waveforms VDS BVDSS L tP VARY tP TO OBTAIN + RG REQUIRED PEAK IAS - VGS VDS IAS VDD VDD DUT tP 0V IAS 0 0.01Ω tAV FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS tON tOFF td(ON) td(OFF) tf tr VDS RL 90% 90% + RG - VDD 10% 10% 0 90% DUT VGS VGS 0 10% VDS (ISOLATED SUPPLY) CURRENT REGULATOR 0.2µF 50% PULSE WIDTH FIGURE 18. RESISTIVE SWITCHING WAVEFORMS FIGURE 17. SWITCHING TIME TEST CIRCUIT 12V BATTERY 50% VDD Qg(TOT) SAME TYPE AS DUT 50kΩ Qgd 0.3µF VGS Qgs D VDS DUT G 0 IG(REF) S 0 IG CURRENT SAMPLING RESISTOR VDS ID CURRENT SAMPLING RESISTOR FIGURE 19. GATE CHARGE TEST CIRCUIT 4-244 IG(REF) 0 FIGURE 20. GATE CHARGE WAVEFORMS IRF740 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 4-245 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029