IRF630, RF1S630SM Data Sheet 9A, 200V, 0.400 Ohm, N-Channel Power MOSFETs These are N-Channel enhancement mode silicon gate power field effect transistors. They are advanced power MOSFETs designed, tested, and guaranteed to withstand a specified level of energy in the breakdown avalanche mode of operation. All of these power MOSFETs are designed for applications such as switching regulators, switching convertors, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. These types can be operated directly from integrated circuits. Formerly developmental type TA17412. Ordering Information PART NUMBER PACKAGE June 1999 File Number 1578.2 Features • 9A, 200V • rDS(ON) = 0.400Ω • Single Pulse Avalanche Energy Rated • SOA is Power Dissipation Limited • Nanosecond Switching Speeds • Linear Transfer Characteristics • High Input Impedance • Related Literature - TB334 “Guidelines for Soldering Surface Mount Components to PC Boards” Symbol BRAND IRF630 TO-220AB IRF630 RF1S630SM TO-263AB RF1S630 D G NOTE: When ordering, use the entire part number. Add the suffix 9A to obtain the TO-263AB variant in the tape and reel, i.e., RF1S630SM9A. S Packaging JEDEC TO-220AB JEDEC TO-263AB SOURCE DRAIN GATE GATE SOURCE DRAIN (FLANGE) 4-202 DRAIN (FLANGE) CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 IRF630, RF1S630SM TC = 25oC, Unless Otherwise Specified Absolute Maximum Ratings Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulse Avalanche Energy Rating (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tpkg IRF630, RF1S630SM 200 200 9 6 36 ±20 75 0.6 150 -55 to 150 UNITS V V A A A V W W/oC mJ oC 300 260 oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC. Electrical Specifications TC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS Drain to Source Breakdown Voltage BVDSS ID = 250µA, VGS = 0V (Figure 10) Gate Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA Zero Gate Voltage Drain Current IDSS On-State Drain Current (Note 2) ID(ON) Gate to Source Leakage Current IGSS Drain to Source On Resistance (Note 2) Forward Transconductance (Note 2) Turn-On Delay Time rDS(ON) gfs td(ON) Rise Time tr Turn-Off Delay Time td(OFF) Fall Time MIN Qg(TOT) Gate to Source Charge Qgs Gate to Drain “Miller” Charge Qgd Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS Internal Drain Inductance LD LS UNITS 200 - - V 2 - 4 V - - 25 µA VDS = 0.8 x Rated BVDSS, VGS = 0V, TJ = 125oC - - 250 µA VDS > ID(ON) x rDS(ON)MAX, VGS = 10V 9 - - A VGS = ±20V - - ±100 nA ID = 5A, VGS = 10V (Figure 8, 9) - 0.25 0.4 Ω VDS > ID(ON) x rDS(ON)MAX, ID = 5A (Figure 12) 3 4.8 - S VDD = 90V, ID ≈ 9A, RGS = 9.1Ω, VGS = 10V RL = 9.6Ω MOSFET Switching Times are Essentially Independent of Operating Temperature - - 30 ns - - 50 ns - - 50 ns - - 40 ns - 19 30 nC - 10 - nC - 9 - nC VGS = 10V, ID = 9A, VDS = 0.8 x Rated BVDSS Ig(REF) = 1.5mA (Figure 14) Gate Charge is Essentially Independent of Operating Temperature VDS = 25V, VGS = 0V, f = 1MHz (Figure 11) Measured From the Contact Screw on Tab to Center of Die Measured From the Drain Lead, 6mm (0.25in) From Package to Center of Die Internal Source Inductance MAX VDS = Rated BVDSS, VGS = 0V tf Total Gate Charge (Gate to Source + Gate to Drain) TYP Measured From the Source Lead, 6mm (0.25in) From Header to Source Bonding Pad Modified MOSFET Symbol Showing the Internal Devices Inductances D - 600 - pF - 250 - pF - 80 - pF - 3.5 - nH - 4.5 - nH - 7.5 - nH - - 1.67 oC/W - - 80 oC/W LD G LS S Thermal Resistance Junction to Case RθJC Thermal Resistance Junction to Ambient RθJA 4-203 Free Air Operation IRF630, RF1S630SM Source to Drain Diode Specifications PARAMETER SYMBOL Continuous Source to Drain Current TEST CONDITIONS ISD Pulse Source to Drain Current (Note 3) Modified MOSFET Symbol Showing the Integral Reverse P-N Junction Diode ISDM D MIN TYP MAX UNITS - - 9 A - - 36 A G S Source to Drain Diode Voltage (Note 2) TJ = 25oC, ISD = 9A, VGS = 0V (Figure 13) - - 2 V trr TJ = 150oC, ISD = 9A, dISD/dt = 100A/µs - 450 - ns QRR TJ = 150oC, ISD = 9A, dISD/dt = 100A/µs - 3 - µC VSD Reverse Recovery Time Reverse Recovery Charge NOTES: 2. Pulse Test: Pulse width ≤ 300µs, Duty Cycle ≤ 2%. 3. Repetitive rating: Pulse width limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3). 4. VDD = 20V, starting TJ = 25oC, L = 3.37mH, RG = 50Ω, peak IAS = 9A. Typical Performance Curves Unless Otherwise Specified 10 ID, DRAIN CURRENT (A) 1.0 0.8 0.6 0.4 0.2 0 0 50 100 8 6 4 2 0 25 150 50 TC, CASE TEMPERATURE (oC) 75 100 150 125 TC, CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE ZθJC, NORMALIZED TRANSIENT THERMAL IMPEDANCE POWER DISSIPATION MULTIPLIER 1.2 FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 1.0 0.5 0.2 0.1 0.1 0.05 0.02 0.01 PDM t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJC RθJC + TC SINGLE PULSE 0.01 10-5 10-4 10-3 10-2 10-1 t1, RECTANGULAR PULSE DURATION (s) FIGURE 3. NORMALIZED TRANSIENT THERMAL IMPEDANCE 4-204 1 10 IRF630, RF1S630SM Typical Performance Curves Unless Otherwise Specified (Continued) 100 20 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VGS = 10V ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) VGS = 8V 10µs 100µs 10 1ms OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 1 10ms 100ms DC 16 12 VGS = 5V 4 VGS = 4V 100 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 1 VGS = 6V 8 TJ = MAX RATED TC = 25oC 0.1 VGS = 7V 0 1000 0 VGS = 8V VGS = 7V VGS = 6V VGS = 5V 4 2 8 ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) VGS = 9V 6 125oC 2 4 3 25oC 4 -55oC 2 0 1 0 5 0 1 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 6. SATURATION CHARACTERISTICS 3 4 2 5 VGS, GATE TO SOURCE VOLTAGE (V) 6 7 FIGURE 7. TRANSFER CHARACTERISTICS 2.2 NORMALIZED DRAIN TO SOURCE ON RESISTANCE 2µs PULSE TEST VGS = 10V 0.6 ON RESISTANCE rDS(ON), DRAIN TO SOURCE 0.8 100 6 VGS = 4V 0 80 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VDS > ID(ON) x rDS(ON)MAX VGS = 10V 8 60 FIGURE 5. OUTPUT CHARACTERISTICS 10 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 40 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 4. FORWARD BIAS SAFE OPERATING AREA 10 20 0.4 VGS = 20V 0.2 0 1.8 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VGS = 10V, ID = 5A 1.4 1 0.6 0.2 0 10 20 30 ID, DRAIN CURRENT (A) FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT 4-205 40 -40 0 40 80 120 TJ , JUNCTION TEMPERATURE (oC) FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE IRF630, RF1S630SM Typical Performance Curves Unless Otherwise Specified (Continued) 2000 VGS = 0V, f = 1MHz CISS = CGS + CGD, CDS CRSS = CGD COSS = CDS + CGD ID = 250µA 1.15 1600 C, CAPACITANCE (pF) NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE 1.25 1.05 0.95 0.85 1200 800 CISS 400 COSS CRSS 0.75 -40 0 40 80 120 0 160 1 10 TJ , JUNCTION TEMPERATURE (oC) FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE ISD, SOURCE TO DRAIN CURRENT (A) gfs, TRANSCONDUCTANCE (S) PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 8 55oC 25oC 4 125oC 2 2 4 6 8 150oC 10 25oC 1 10 1 0 ID , DRAIN CURRENT (A) VGS, GATE TO SOURCE VOLTAGE (V) 2 FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE ID = 9A VDS = 40V 15 V20 DS = 100V 10 VDS = 160V IRF630, IRF632 5 0 0 8 16 24 32 40 Qg, GATE CHARGE (nC) FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE 4-206 3 VSD, SOURCE TO DRAIN VOLTAGE (V) FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT 20 50 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 100 0 0 40 FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE 10 6 30 20 VDS, DRAIN TO SOURCE VOLTAGE (V) 4 IRF630, RF1S630SM Test Circuits and Waveforms VDS BVDSS L tP VARY tP TO OBTAIN + RG REQUIRED PEAK IAS - VGS VDS IAS VDD VDD DUT tP 0V IAS 0 0.01Ω tAV FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS tON tOFF td(ON) td(OFF) tf tr RL VDS 90% 90% + RG - VDD 10% 10% 0 DUT 90% VGS VGS 0 FIGURE 17. SWITCHING TIME TEST CIRCUIT 0.2µF 50% PULSE WIDTH 10% FIGURE 18. RESISTIVE SWITCHING WAVEFORMS VDS (ISOLATED SUPPLY) CURRENT REGULATOR 12V BATTERY 50% VDD Qg(TOT) SAME TYPE AS DUT 50kΩ Qgd 0.3µF VGS Qgs D VDS DUT G 0 Ig(REF) S 0 IG CURRENT SAMPLING RESISTOR VDS ID CURRENT SAMPLING RESISTOR FIGURE 19. GATE CHARGE TEST CIRCUIT 4-207 IG(REF) 0 FIGURE 20. GATE CHARGE WAVEFORMS IRF630, RF1S630SM All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 4-208 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029