IRFP9140 Data Sheet July 1999 19A, 100V, 0.200 Ohm, P-Channel Power MOSFET This is an advanced power MOSFET designed, tested, and guaranteed to withstand a specified level of energy in the breakdown avalanche mode of operation. It is a P-Channel enhancement mode silicon gate power field effect transistor designed for applications such as switching regulators, switching convertors, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. These types can be operated directly from integrated circuits. 2292.4 Features • 19A, 100V • rDS(ON) = 0.200Ω • Single Pulse Avalanche Energy Rated • SOA is Power Dissipation Limited • Nanosecond Switching Speeds • Linear Transfer Characteristics • High Input Impedance Symbol Formerly developmental type TA17521. D Ordering Information PART NUMBER File Number PACKAGE BRAND G IRFP9140 TO-247 IRFP9140 NOTE: When ordering, use the entire part number. S Packaging JEDEC STYLE T0-247 SOURCE DRAIN GATE DRAIN (FLANGE) 4-57 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 IRFP9140 Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID TC =100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Pulsed Drain (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulse Avalanche Energy Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Eas Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ , TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg IRFP9140 -100 -100 -19 -12 -76 ±20 150 1.2 960 -55 to 150 UNITS V V A A A V W W/oC mJ oC 300 260 oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC. Electrical Specifications TC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Drain to Source Breakdown Voltage BVDSS VGS = 0V, ID = -250µA, (Figure 10) -100 - - V Gate Threshold Voltage VGS(TH) VDS = VGS, ID = -250µA -2.0 - -4.0 V Zero Gate Voltage Drain Current IDSS On-State Drain Current (Note 2) ID(ON) Gate to Source Leakage Current IGSS Drain to Source On Resistance (Note 2) Forward Transconductance (Note 2) Turn-On Delay Time rDS(ON) gfs td(ON) Rise Time tr Turn-Off Delay Time td(OFF) Fall Time VDS = Rated BVDSS, VGS = 0V - - 25 µA VDS = 0.8 x Rated BVDSS, VGS = 0V, TJ = 125oC - - 250 µA VDS > ID(ON) x rDS(ON) MAX, VGS = -10V VGS = ±20V VGS = -10V, I D = -10A, (Figures 8, 9) VDS ≤ -50V, ID = -10A, (Figure 12) VDD = -50V, ID ≈ -19A, RG = 9.1Ω, RL = 2.5Ω, VGS = -10V, (Figures 17, 18) MOSFET Switching Times Are Essentially Independent of Operating Temperature tf Total Gate Charge (Gate to Source + Gate to Drain) Qg(TOT) Gate to Source Charge Qgs Gate to Drain “Miller” Charge Qgd Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS VGS = -10V, ID = -19A, VDS = 0.8 x Rated BVDSS, IG(REF) = -1.5mA (Figures 14, 19, 20) Gate Charge is Essentially Independent of Operating Temperature VGS = 0V, VDS = -25V, f = 1.0MHz, (Figure 11) Internal Drain Inductance LD Measured Between Contact Screw on Header That Is Closer to Source and Gate Pins and Center of Die Internal Source Inductance LS Measured From the Source Pin, 6mm (0.25in) From Header and Source Bonding Pad Modified MOSFET Symbol Showing the Internal Device Inductances D -19 - - A - - ±100 nA - 0.14 0.20 Ω 5.3 7.9 - S - 16 20 ns - 65 100 ns - 47 70 ns - 28 70 ns - 37 55 nC - 8.7 - nC - 22 - nC - 1200 - pF - 570 - pF - 160 - pF - 5.0 - nH - 13 - nH - - 0.83 oC/W - - 30 0C/W LD G LS S Junction to Case RθJC Junction to Ambient RθJA 4-58 Free Air Operation IRFP9140 Source to Drain Diode Specifications PARAMETER SYMBOL Continuous Source to Drain Current MIN TYP MAX UNITS - - -19 A - - -76 A TJ = 25oC, ISD = -19A, VGS = 0V, (Figure 13) - - -1.5 V trr TJ = 25oC, ISD = -18A, dISD/dt = 100A/µs - 210 - ns QRR TJ = 25oC, ISD = -18A, dISD/dt = 100A/µs - 2.0 - µC ISD Pulse Source to Drain Current (Note 3) TEST CONDITIONS Modified MOSFET Symbol Showing the Integral Reverse P-N Junction Diode ISDM D G S Source to Drain Diode Voltage (Note 2) Reverse Recovery Time Reverse Recovery Charge VSD NOTES: 2. Pulse test: pulse width ≤ 80µs, duty cycle ≤ 2%. 3. Repetitive rating: pulse width limited by Maximum junction temperature. See Transient Thermal Impedance curve (Figure 3). 4. VDD = 50V, start TJ = 25oC, L = 4.2mH, RG = 25Ω, peak IAS = 19A. See Figures 15, 16. Typical Performance Curves Unless Otherwise Specified 20 ID, DRAIN CURRENT (A) 1.0 0.8 0.6 0.4 0.2 0 0 25 50 75 100 TC , CASE TEMPERATURE (oC) 125 FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE 150 16 12 8 4 0 25 50 75 100 125 TC, CASE TEMPERATURE (oC) 150 FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 1 ZθJC, NORMALIZED 0.05 THERMAL IMPEDANCE POWER DISSIPATION MULTIPLIER 1.2 0.2 0.1 0.1 0.05 0.02 0.01 10-2 10-3 10-5 PDM SINGLE PULSE t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ= PDM x ZθJC x RθJC + TC 10-4 10-3 10-2 0.1 t1, RECTANGULAR PULSE DURATION (s) FIGURE 3. NORMALIZED TRANSIENT THERMAL IMPEDANCE 4-59 1 10 IRFP9140 Typical Performance Curves Unless Otherwise Specified (Continued) 30 10µs 100µs 1ms 10 OPERATION IN THIS AREA IS LIMITED BY rDS(ON) 10ms 100ms DC 1 TC = 25oC TJ = MAX RATED SINGLE PULSE 0.1 1 10 VDS, DRAIN VOLTAGE (V) IDS, DRAIN TO SOURCE CURRENT (A) IDS, DRAIN TO SOURCE CURRENT (A) 100 VGS = -10V VGS = -8V VGS = -7V 24 VGS = -6V 18 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 12 VGS = -5V 6 VGS = -4V 0 100 0 -10 -20 -30 -40 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. OUTPUT CHARACTERISTICS 102 VGS = -10V IDS, DRAIN TO SOURCE CURRENT (A) IDS, DRAIN TO SOURCE CURRENT (A) 30 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 24 VGS = -8V VGS = -7V 18 VGS = -6V 12 VGS = -5V 6 VGS = -4V 0 VDS ≤ -50V PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 10 1 TJ = 150o TJ = 25o 0.1 0 1 2 3 4 VDS, DRAIN TO SOURCE VOLTAGE (V) 5 0 2 4 6 8 VGS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 6. SATURATION CHARACTERISTICS 1.2 3.0 VGS = -10V 0.9 0.6 0.3 0 VGS = -20V 0 16 32 48 ID, DRAIN CURRENT (A) 64 FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT 4-60 80 2.4 RESISTANCE PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX 10 FIGURE 7. TRANSFER CHARACTERISTICS NORMALIZED DRAIN TO SOURCE ON 1.5 rDS(ON), DRAIN TO SOURCE ON RESISTANCE (Ω) -50 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VGS = -10V 1.8 1.2 0.6 0 -60 -40 -20 0 20 40 60 80 100 120 140 160 TJ, JUNCTION TEMPERATURE (oC) FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE IRFP9140 Typical Performance Curves Unless Otherwise Specified (Continued) 1.25 2500 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS ≈ CDS + CGD NORMALIZED DRAIN TO SOURCE BREAKDOWN ID = 250µA 1.15 C, CAPACITANCE (pF) 2000 1.05 0.95 0.85 1500 CISS 1000 COSS 500 CRSS 0.75 -60 -40 -20 0 20 40 60 80 0 100 120 140 160 1 TJ, JUNCTION TEMPERATURE (oC) FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE TJ = 25oC 9 TJ = 150oC 6 3 0 0 8 FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE ISD, SOURCE TO DRAIN CURRENT (A) 12 24 32 16 NEGATIVE ID, DRAIN CURRENT (A) 40 FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT 20 ID = -19A 16 TJ = 150oC -10 TJ = 25oC -1.0 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX -0.1 -0.4 -0.6 -0.8 -1.0 -1.2 -1.4 -1.6 NEGATIVE VSD, SOURCE TO DRAIN VOLTAGE (V) FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE VDS = -80V VDS = -50V VDS = -20V 12 8 4 0 0 12 24 36 48 Qg(TOT), TOTAL GATE CHARGE (nC) 60 FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE 4-61 102 -100 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX VDS ≤ -50V VGS, GATE TO SOURCE VOLTAGE (V) gfs, TRANSCONDUCTANCE (S) 15 10 NEGATIVE VDS, DRAIN TO SOURCE VOLTAGE (V) -1.8 IRFP9140 Test Circuits and Waveforms VDS tAV L 0 VARY tP TO OBTAIN - RG REQUIRED PEAK IAS + VDD DUT 0V VDD tP VGS IAS IAS VDS tP 0.01Ω BVDSS FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS tON tOFF td(OFF) td(ON) tr 0 RL - DUT VGS + 10% 10% VDS VDD RG tf VGS 0 90% 90% 10% 50% 50% PULSE WIDTH 90% FIGURE 17. SWITCHING TIME TEST CIRCUIT -VDS (ISOLATED SUPPLY) CURRENT REGULATOR FIGURE 18. RESISTIVE SWITCHING WAVEFORMS 0 VDS DUT 12V BATTERY 0.2µF 50kΩ 0.3µF Qgs VGS Qgd D Qg(TOT) DUT G 0 0 S IG(REF) IG CURRENT SAMPLING RESISTOR +VDS ID CURRENT SAMPLING RESISTOR FIGURE 19. GATE CHARGE TEST CIRCUIT 4-62 VDD IG(REF) FIGURE 20. GATE CHARGE WAVEFORMS IRFP9140 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. 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