RFD15P06, RFD15P06SM, RFP15P06
Data Sheet
July 1999
15A, 60V, 0.150 Ohm, P-Channel Power
MOSFETs
• 15A, 60V
Formerly developmental type TA09833.
• rDS(ON) = 0.150Ω
• Temperature Compensating PSPICE® Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
Ordering Information
PACKAGE
3988.3
Features
These P-Channel power MOSFETs are manufactured using
the MegaFET process. This process which uses feature
sizes approaching those of LSI integrated circuits, gives
optimum utilization of silicon, resulting in outstanding
performance. They were designed for use in applications
such as switching regulators, switching converters, motor
drivers, and relay drivers. These transistors can be operated
directly from integrated circuits.
PART NUMBER
File Number
D
BRAND
RFD15P06
TO-251AA
F15P06
RFD15P06SM
TO-252AA
F15P06
RFP15P06
TO-220AB
RFP15P06
G
NOTE: When ordering, use the entire part number. Add the suffix 9A to
obtain the TO-252AA variant in the tape and reel, i.e., RFD15P06SM9A.
S
Packaging
JEDEC TO-220AB
JEDEC TO-251AA
SOURCE
DRAIN
GATE
DRAIN (FLANGE)
SOURCE
DRAIN
GATE
DRAIN (FLANGE)
JEDEC TO-252AA
DRAIN (FLANGE)
GATE
SOURCE
4-103
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
PSPICE® is a registered trademark of MicroSim Corporation.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
RFD15P06, RFD15P06SM, RFP15P06
Absolute Maximum Ratings
TC = 25oC Unless Otherwise Specified
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDSS
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . VDGR
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Pulsed Drain Current (Figure 5) (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . IDM
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS
Pulsed Avalanche Rating (Figure 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PD
Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . TL
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . Tpkg
RFD15P06, RFD15P06SM, RFP15P06
-60
-60
15
Refer to Peak Current Curve
±20
Refer to UIS Curve
80
0.533
-55 to 175
UNITS
V
V
A
300
260
oC
oC
V
W
W/oC
oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ = 25oC to 150oC.
Electrical Specifications
TC = 25oC, Unless Otherwise Specified
MIN
TYP
MAX
UNITS
Drain to Source Breakdown Voltage
PARAMETER
SYMBOL
BVDSS
ID = 250µA, VGS = 0V
-60
-
-
V
Gate to Source Threshold Voltage
VGS(TH)
VGS = VDS, ID = 250µA
Zero Gate Voltage Drain Current
IDSS
Gate to Source Leakage Current
Drain to Source On Resistance (Note 2)
IGSS
-2.0
-
-4.0
V
VDS = Rated BVDSS, VGS = 0V
-
-
-1
µA
VDS = 0.8 x Rated BVDSS, TC = 150oC
-
-
-25
µA
VGS = ±20V
-
-
±100
nA
ID ≈ 15A, VGS = -10V, (Figure 9)
-
-
0.150
W
VDD = -30V, ID = 7.5A
RL = 4.0Ω, VGS = -10V
RG = 12.5Ω
(Figure 13)
-
-
60
ns
-
16
-
ns
-
30
-
ns
td(OFF)
-
50
-
ns
tf
-
20
-
ns
-
-
100
ns
-
-
150
nC
-
-
75
nC
-
-
3.5
nC
-
1150
-
pF
-
300
-
pF
rDS(ON)
Turn-On Time
tON
Turn-On Delay Time
td(ON)
Rise Time
tr
Turn-Off Delay Time
TEST CONDITIONS
Fall Time
Turn-Off Time
tOFF
Total Gate Charge
Qg(TOT)
VGS = 0V to -20V
Gate Charge at -10V
Qg(-10)
VGS = 0V to -10V
Threshold Gate Charge
Qg(TH)
VGS = 0V to -2V
VDD = -48V, ID = 15A,
RL = 3.20Ω
IG(REF) = 0.65mA
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
-
56
-
pF
Thermal Resistance Junction to Case
RθJC
TO-220AB, TO-251AA, TO-252AA
-
-
1.875
oC/W
Thermal Resistance Junction to Ambient
RθJA
TO-251AA, TO-252AA
-
-
100
oC/W
TO-220AB
-
-
62
oC/W
VDS = -25V, VGS = 0V
f = 1MHz
(Figure 12)
Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage (Notte 2)
Reverse Recovery Time
SYMBOL
VSD
trr
TEST CONDITIONS
MIN
TYP
MAX
UNITS
ISD = -15A
-
-
-1.5
V
ISD = -15A, dISD/dt = 100A/µs
-
-
125
ns
NOTES:
2. Pulsed: pulse duration ≤ 300ms Max, duty cycle ≤ 2%.
3. Repetitive rating: pulse width limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3).
4-104
RFD15P06, RFD15P06SM, RFP15P06
Typical Performance Curves
Unless Otherwise Specified
POWER DISSIPATION MULTIPLIER
1.2
-16
ID , DRAIN CURRENT (A)
1.0
0.8
0.6
0.4
-12
-8
-4
0.2
0
0
0
25
50
75
100
125
25
175
150
50
75
100
125
150
175
TC , CASE TEMPERATURE (oC)
TC , CASE TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
2
ZθJC, NORMALIZED
THERMAL IMPEDANCE
1
0.5
0.2
0.1
0.1
PDM
0.05
t1
0.02
0.01
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x Zθ JC x Rθ JC + TC
SINGLE PULSE
0.01
10-5
10-4
10-3
10-2
10-1
t, RECTANGULAR PULSE DURATION (s)
100
101
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
-200
TJ = MAX RATED
TC = 25oC
100µs
-10
1ms
10ms
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
100ms
DC
-1
-1
-10
VDS , DRAIN TO SOURCE VOLTAGE (V)
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
4-105
-100
VGS = -20V
IDM , PEAK CURRENT (A)
ID, DRAIN CURRENT (A)
-100
FOR TEMPERATURES ABOVE 25oC
DERATE PEAK CURRENT
CAPABILITY AS FOLLOWS:
-100
175 – T C
I = I 25 ------------------------
150
TC = 25oC
VGS = -10V
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
-10
10-5
10-4
10-3
10-2
10-1
100
t, PULSE WIDTH (s)
FIGURE 5. PEAK CURRENT CAPABILITY
101
RFD15P06, RFD15P06SM, RFP15P06
Typical Performance Curves
Unless Otherwise Specified (Continued)
-50
STARTING TJ = 25oC
ID , DRAIN CURRENT (A)
IAS , AVALANCHE CURRENT (A)
-40
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TC = 25oC
STARTING TJ = 150oC
-10
If R = 0
tAV = (L) (IAS) / (1.3RATED BVDSS - VDD)
If R ≠ 0
tAV = (L/R) ln [(IAS*R) / (1.3 RATED BVDSS - VDD) + 1]
-1
0.1
1
10
tAV, TIME IN AVALANCHE (ms)
-30
VGS = -7V
-20
VGS = -6V
-10
100
VGS = -4.5V
VGS = -5V
0
0
-1.5
-3.0
-4.5
-6.0
-7.5
VDS , DRAIN TO SOURCE VOLTAGE (V)
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
FIGURE 7. SATURATION CHARACTERISTICS
2.5
-40
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = -15V
-32
25oC
-55oC
-24
175oC
-16
-8
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
IDS(ON) , DRAIN TO SOURCE CURRENT (A)
VGS = -8V
VGS = -20V
NOTE: Refer to Intersil Application Notes AN9321 and AN9322.
0
0
-2
-4
-6
-8
VGS , GATE TO SOURCE VOLTAGE (V)
2.0
1.5
1.0
0.5
-40
0
40
80
120
160
200
TJ , JUNCTION TEMPERATURE (oC)
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
2.0
2.0
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
VGS = VDS, ID = 250µA
1.5
1.0
0.5
0
-80
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VGS = -10V, ID = 15A
0
-80
-10
FIGURE 8. TRANSFER CHARACTERISTICS
NORMALIZED GATE
THRESHOLD VOLTAGE
VGS = -10V
-40
0
40
80
120
160
200
TJ , JUNCTION TEMPERATURE (oC)
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
4-106
ID = 250µA
1.5
1.0
0.5
0
-80
-40
0
40
80
120
160
200
TJ , JUNCTION TEMPERATURE (oC)
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
RFD15P06, RFD15P06SM, RFP15P06
Typical Performance Curves
Unless Otherwise Specified (Continued)
-60
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS ≈ CDS + CGS
1000
800
600
COSS
400
200
CRSS
-10
VDD = BVDSS
VDD = BVDSS
-45
-7.5
RL = 3.33Ω
IG(REF) = 0.65mA
VGS = -10V
-30
-15
0
-5
0.75 BVDSS 0.75 BVDSS
0.50 BVDSS 0.50 BVDSS
0.25 BVDSS 0.25 BVDSS
-2.5
0
0
-5
-10
-15
-20
VGS , GATE TO SOURCE VOLTAGE (V)
CISS
1200
C, CAPACITANCE (pF)
VDS , DRAIN TO SOURCE VOLTAGE (V)
1400
0
-25
20
VDS , DRAIN TO SOURCE VOLTAGE (V)
IG(REF)
t, TIME (µs)
IG(ACT)
80
IG(REF)
IG(ACT)
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
FIGURE 13. NORMALIZED SWITCHING WAVEFORMS FOR
CONSTANT GATE CURRENT
Test Circuits and Waveforms
VDS
tAV
0
L
VARY tP TO OBTAIN
REQUIRED PEAK IAS
-
RG
+
0V
VGS
VDD
VDD
DUT
tP
IAS
IAS
VDS
tP
0.01Ω
BVDSS
FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT
tON
tOFF
td(OFF)
td(ON)
tr
VDS
0
RL
tf
10%
10%
VGS
VDS
VDD
+
VGS
DUT
RGS
VGS
0
90%
90%
10%
50%
50%
PULSE WIDTH
90%
FIGURE 16. SWITCHING TIME TEST CIRCUIT
4-107
FIGURE 17. RESISTIVE SWITCHING WAVEFORMS
RFD15P06, RFD15P06SM, RFP15P06
Test Circuits and Waveforms
(Continued)
VDS
RL
VDS
Qg(TH)
0
VGS = -2V
VGS
-
VGS = -10V
-VGS
VDD
Qg(-10)
+
DUT
VGS = -20V
VDD
Ig(REF)
Qg(TOT)
0
Ig(REF)
FIGURE 18. GATE CHARGE TEST CIRCUIT
4-108
FIGURE 19. GATE CHARGE WAVEFORMS
RFD15P06, RFD15P06SM, RFP15P06
PSPICE Electrical Model
.SUBCKT RFP15P06 2 1 3
REV 9/06/94
CA 12 8 1.6e-9
CB 15 14 1.47e-9
CIN 6 8 1.09e-9
LDRAIN
5
10
DBODY 5 7 DBDMOD
DBREAK 7 11 DBKMOD
DPLCAP 10 6 DPLCAPMOD
5
51
ESG
+
1
9
RDRAIN
6
8
18
8
17
18
+
DBODY
MOS2
21
-
+
20
EBREAK
16
VTO
-
EVTO
GATE LGATE RGATE
ESCL
+
-
LDRAIN 2 5 1e-9
LGATE 1 9 6.73e-9
LSOURCE 3 7 6.69e-9
RSCL1
RSCL2
EBREAK 5 11 17 18 -73.0
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 5 10 8 6 1
EVTO 20 6 8 18 1
IT 8 17 1
2
DRAIN
DPLCAP
RIN
11
MOS1
6
DBREAK
CIN
8
RSOURCE
LSOURCE
3
SOURCE
MOS1 16 6 8 8 MOSMOD M = 0.99
MOS2 16 21 8 8 MOSMOD M = 0.01
RBREAK 17 18 RBKMOD 1
RDRAIN 50 16 RDSMOD 63.6e-3
RGATE 9 20 7.37
RIN 6 8 1e9
RSCL1 5 51 RSCLMOD 1e-6
RSCL2 5 50 1e3
RSOURCE 8 7 RDSMOD 46.5e-3
RVTO 18 19 RVTOMOD 1
S1A
12
13
8
S1B
7
S2A
14
13
13
15
17
RBREAK
S2B
RVTO
CB
CA
IT
+
6
EGS
8
-
+
EDS
-
14
5
8
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 8 19 DC 1
VTO 21 6 -0.65
ESCL 51 50 VALUE = {(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)*1e6/35,4))}
.MODEL DBDMOD D (IS = 1.27e-13 RS = 1.62e-2 TRS1 = 1.35e-3 TRS2 = -4.33e-6 CJO = 1.25e-9 TT = 7.97e-8)
.MODEL DBKMOD D (RS = 2.54e-1 TRS1 = 4.54e-3 TRS2 = -1.12e-5)
.MODEL DPLCAPMOD D (CJO = 285e-12 IS = 1e-30 N = 10)
.MODEL MOSMOD PMOS (VTO = -3.78 KP = 6.97 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL RBKMOD RES (TC1 = 9.15e-4 TC2 = -4.0e-7)
.MODEL RDSMOD RES (TC1 = 5.47e-3 TC2 = 1.37e-5)
.MODEL RSCLMOD RES (TC1 = 1.9e-3 TC2 = -7.5e-6)
.MODEL RVTOMOD RES (TC1 = -3.71e-3 TC2 = -2.41e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 3.65 VOFF = 1.65)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 1.65 VOFF = 3.65)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.60 VOFF = -4.40)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4.40 VOFF = 0.60)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; written by William J. Hepp and C. Frank Wheatley.
4-109
18
19
-
VBAT
+
RFD15P06, RFD15P06SM, RFP15P06
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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4-110
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