V13N3 - SEPTEMBER

LINEAR TECHNOLOGY
SEPTEMBER 2003
IN THIS ISSUE…
COVER ARTICLE
Multiphase Power Conversion
for Portable and Point-of-Load
Boost Applications..........................1
David Salerno
Issue Highlights .............................2
LTC® in the News ............................2
DESIGN FEATURES
CompactPCI® Hot Swap™
Controller with I2C™ Interface,
Bus Precharge and On-Chip
LOCAL_PCI_RESET# Logic...............6
Victor Fleury
Low Noise, Micropower
Precision Op Amp Swings
Outputs from Rail to Rail .............10
Kris Lokere and Glen Brisebois
Addressable Bus Buffer Provides
Capacitance Buffering, Live
Insertion and Nested Addressing
in 2-Wire Bus Systems ..................13
John Ziegler
Versatile Hot Swap Controller
with Open Circuit Detect, Foldback
Current Limiting and Much More ..17
Mark Belch
Micropower SOT-23 Boost with
Integrated Schottky Diode
Provides Output Disconnect
and Short Circuit Protection ........20
Leonard Shtargot
Ampliier with Integrated Filter
Offers the Best High Speed,
Low Noise Interface for
Differential DACs and ADCs..........22
Michael Kultgen
VOLUME XIII NUMBER 3
Multiphase Power
Conversion for Portable
and Point-of-Load
Boost Applications
Introduction
Multiphase power converters offer
the advantages of higher eficiency,
smaller size and lower capacitor ripple currents over their single phase
counterparts. The higher effective
switching frequency and phased ripple
currents signiicantly reduce the size
and cost of the ilter capacitors and
lower output ripple, while allowing
the use of several small inductors.
This has made them popular in
many high current buck (step-down)
applications, especially where space
is a concern. With the LTC3425, the
industry’s irst multiphase monolithic
boost converter, you can achieve the
same performance and size beneits
in boost (step-up) applications.
This 4-phase synchronous boost
converter can deliver over 12W of
by David Salerno
power in a smaller size, with higher
eficiency and lower output ripple than
is achievable with a comparable singlephase boost converter. The LTC3425
can startup with as little as 1V, and
operate with inputs up to 4.5V, making
it suitable for a variety of input voltage
applications. The output voltage range
is 2.4V to 5.25V, and peak current
capability is over 5A.
Multiphase Converters:
They’re Not Just for Buck
Applications Anymore
The high frequency (up to 8MHz)
4-phase architecture allows the use
of small, low cost inductors rather
than a single large, bulky inductor,
and requires much less output ilter capacitance than the equivalent
continued on page 3
Low Voltage Ampliiers Give
Choice of Accuracy or Speed.........25
Frank Johnston, Glen Brisebois
and Danh Tran
Feature-Rich Battery Charger that
Manages Both Battery Charging
and Bus Voltage Regulation..........28
John Shannon
DESIGN IDEAS
............................................... 30–38
(complete list on page 30)
New Device Cameos.......................38
Design Tools .................................39
Sales Ofices.................................40
Figure 1. How does a multiphase boost converter improve on its single phase counterpart? First
of all, a multiphase topology saves space and simpliies layout by removing bulky, hard-to-place
components and replacing them with easier-to-it, low proile components. Inductor and output
capacitor size comparison of single-phase and 4-phase circuits.
, LTC, LT, Burst Mode, OPTI-LOOP, Over-The-Top and PolyPhase are registered trademarks of Linear Technology Corporation. Adaptive Power, C-Load, DirectSense, FilterCAD, Hot Swap, LinearView, Micropower SwitcherCAD, Multimode
Dimming, No Latency ΔΣ, No Latency Delta-Sigma, No RSENSE, Operational Filter, PowerPath, PowerSOT, SoftSpan, Stage
Shedding, SwitcherCAD, ThinSOT, UltraFast and VLDO are trademarks of Linear Technology Corporation. Other product
names may be trademarks of the companies that manufacture the products.
EDITOR’S PAGE
Issue Highlights
Our cover article introduces the
LTC3425, the industry’s irst multi–
phase monolithic boost converter,
offering the advantages of small size
and low output ripple currents.
This 4-phase synchronous boost
converter can deliver over 12W of
power in a smaller size, with higher
eficiency and lower output ripple
than is achievable with a comparable
single-phase boost converter.
Featured Devices
This issue features a variety of exciting new devices which simplify
application designs and improve their
performance.
Hot Swap, Hot Plug
The LTC4240 provides a controlled
on-off switch for four hot swappable
board power supply voltages, allowing the board to be safely inserted
or removed from a live CompactPCI
(CPCI) slot without disturbing the
system power supplies. The LTC4240
includes an I2C-compatible interface
that allows software control and monitoring of device function and power
supply status.
The new LTC4302 addressable 2wire bus buffer addresses problems
associated with live insertion of I/O
cards in data processing and communications systems. The LTC4302
provides a bridge between any two
physically separate 2-wire buses.
Masters on the buses can command
the LTC4302 to connect and disconnect the backplane and card buses
through software. By using multiple
LTC4302s in a system and connecting
and disconnecting them appropriately,
users can assign the same address to
multiple devices in the system.
The LT4254 is designed to turn on a
board’s supply voltage in a controlled
manner, allowing the board to be safely
inserted or removed from a live backplane having a supply voltage from
10.8 to 36 volts. The device features
programmable inrush current control,
current foldback, programmable 1%
2
tolerance on the undervoltage and
overvoltage thresholds, overcurrent
protection, and a power good output
signal that indicates when the output
supply voltage is ready.
Power
The LTC1980 is a single-device that
manages both battery charging and
generation of the regulated system
bus voltage.
The LT3464 is the only micropower
boost converter in the industry to combine a 36V NPN power switch, power
Schottky diode, and output disconnect into an 8-lead ThinSOT™. This
unprecedented level of integration
saves several external components
while offering true output disconnect, making it possible to generate
outputs of up to 34V with a zero current
shutdown while using a mere 40mm2
of board area.
Ampliiers and Filters
The LT6011 dual precision op amp its
into a 3 × 3mm2 DFN package, which
is so small it doesn’t even have leads.
The LT6011 also offers low voltage,
micro-power operation. A quad version, the LT6012, is also available in
the SO-14 and GN16 packages.
The LT6600 is a family of fully differential ampliiers with an integrated
4th order lowpass ilter. Each device in
the family features a ixed cutoff frequency (2.5MHz, 10MHz and 20MHz)
and operates with power supplies
ranging from 3V to 10V. The LT6600s
have a proprietary architecture that
minimizes noise and distortion while
maximizing speed.
Two new families of single, dual, and
quad ampliiers, the 1mA LT6220/1/
2 and the 3mA LT1803/4/5, provide
high speed ampliication on supplies as
low as 2.5V. The 85MHz LT1803 series
is optimized for large signals, with a
100V/µs slew rate, while the 60MHz
LT6220 series focuses on excellent
DC performance at low current, with
a maximum input offset speciication
of only 350µV.
LTC in the News…
On July 22, Linear Technology
Corporation announced its inancial results for its iscal year
ending June 29, 2003. According
to Robert H. Swanson, Chairman
of the Board and CEO, “Fiscal 2003 was a successful, but
challenging year for Linear, as
we reported solid growth in a
modestly improving economic
environment. We beneited from
the demand for our high-performance analog solutions in
many new diverse applications
in wireless, high-end consumer,
automotive, security, computer,
military, industrial/medical and
networking. Our sales increased
18%, and operating income improved 31%. We had an increase
in net income of 20%, which was
impacted by a decrease in interest income due to the dramatic
decrease in interest rates.
Although the overall demand
for our products is improving, our
customers continue to be cautious
in their ordering patterns. While
accurately forecasting short-term
results remains a challenge, we
expect low single digit growth in
sales and proits in the September quarter, which is in line with
our normal summer quarter patterns.”
The Company reported net sales
for the year of $606,573,000 and
net income of $236,591,000.
Diluted earnings were $0.74 per
share. A cash dividend of $.06
per share was paid on August 20,
2003 to stockholders of record on
August 1, 2003.
Design Ideas and Cameos
Starting on page 30 are ive new Design
Ideas, and at the back are three New
Device Cameos. See www.linear.com
for complete device speciications and
applications information.
CompactPCI is a trademark of PCI Industrial Computer
Manufacturers Group. I2C is a trademark of Philips
Electronics N.V.
Linear Technology Magazine • September 2003
DESIGN FEATURES
LTC3425, continued from page 1
Table 1. Comparison of typical inductors used for 1-phase and 4-phase designs
1-Phase
4-Phase
Inductor
Coilcraft
DO3316
TDK
RLF5018T
Inductance
(µH)
Required
Qty
Total Area
(mm2)
Height
(mm)
Max Total DC Resistance
(Ω)
Total Peak Current
Rating (A)
2.2
1
122
5.21
0.012
7.0
2.7
4
29.12 × 4 = 116.5
2.05
0.033/4 = 0.0083
1.8 × 4 = 7.2
single-phase circuit. This is ideal for
space-constrained boards, Point-ofLoad regulators, and portable devices
that demand the use of low-proile
components. For example, in a 2-cell
NiCd or NiMH to 3.3V/2A boost application, the peak inductor current
required for a single-phase design is
nearly 5A.
Figure 1 shows the size difference
between a typical single inductor that
would be required to handle this current, and the inductors that could be
used in a 4-phase design. Figure 1
also compares the output capacitors
required to achieve the same output
ripple voltage in single-phase and
4-phase applications. Table 1 shows
speciications for the inductors pictured in Figure 1—not only are the
four small inductors much thinner, but
they also have a lower combined DC
resistance for improved eficiency.
discontinuous mode operation. In discontinuous mode, an internal resistor
is placed across the inductor when the
synchronous rectiier turns off, damping any high frequency ringing.
A single error ampliier is used
for all four phases, and controls the
peak current required to maintain
regulation. Referring to Figure 2, the
loop compensation components are
connected between COMP and GND.
Soft-start time is set by the CSS capacitor, which ramps the current limit up
to its inal value during startup
Each VOUT pin should have its own
ceramic ilter capacitor located as close
as possible to the VOUT and GND pins
in that phase. These are typically 0805
size parts. The pinout of the LTC3425
lends itself to a tight symmetrical layout of the power components. With
the 4-phase architecture, low output
voltage ripple is achieved using only
the four small ceramic capacitors,
Easy to Use
even at load currents of 2A or more.
Designing a converter using the An optional bulk capacitor on VOUT
LTC3425 is no different than design- can be added to improve transient
ing a traditional single phase boost response with dynamic loads. This
converter. All the power switches are can be a ceramic, tantalum, or an
internal, so the 4-phase operation is OSCON-style capacitor.
transparent. Current limit and switchThe output disconnect feature efing frequency for all four phases are fectively eliminates the PMOS body
each programmed by a single resistor, diode between the switch node and
as in single phase designs. Setting the VOUT during shutdown, allowing VOUT
output voltage and compensating the to discharge to zero volts, all while
loop are also no different than in other achieving less than 1µA shutdown
familiar designs.
current. The disconnect feature also
blocks unwanted current low between
Circuit Description: Four
VIN and VOUT, eliminating the large inIndependent Power Stages
rush currents during startup that are
Each of the four phases has an NMOS inherent to most boost converters.
and a PMOS power switch, and conThe internal oscillator, programmed
trols its own inductor current using by a resistor from R T to GND, genera peak current mode control loop, ates four internal clock pulses, each
consisting of a current comparator phase shifted by 90o. The switching
with adaptive slope compensation frequency can be set from 100kHz to as
and a reverse current comparator for high as 2MHz per phase, for an effecLinear Technology Magazine • September 2003
tive frequency of 8MHz as seen at the
output ilter cap. Maximum duty cycle
for each phase is set to 90%. A sync
input and oscillator output are provided for synchronizing the converter
to a system clock, or synchronizing
two converters together. Note that the
sync input and clock output are at
four times the switching frequency of
each phase.
In Burst Mode® operation, only
phase A is active, reducing switching
and quiescent losses for maximum
eficiency. In this mode, phase A
operates with a ixed peak inductor
current of 0.6A typical. Drawing just
12µA of quiescent current in Burst
Mode operation allows the LTC3425
to operate with high eficiency during
very light load conditions.
2-Cell to 3.3V/2.2A Boost
Application, with Automatic
Burst Mode Operation
Figure 2 shows a typical application
circuit using the LTC3425 to boost
from two NiCd or NiMH cells to 3.3V.
This design can supply over 2A of load
current with eficiencies up to 94%
while switching at 1MHz per phase
(4MHz output ripple frequency).
Maximum component height is a slim
2.05mm. High eficiency is maintained
over a very wide load range, as shown
in Figure 3.
A key feature of the LTC3425 is the
programmable automatic Burst Mode
operation, which allows the user to set
the load current where the converter
enters Burst Mode operation, extending the eficiency at light load. This is
ideal for systems where the mode cannot be controlled manually by the host.
Since the Burst Mode circuit monitors
average output current (rather than
peak inductor current), the mode
threshold is not affected by input
3
DESIGN FEATURES
100
90
CIN
2.2µF
L1
2.7µH
VIN
SWA
L1
2.7µH
L1
2.7µH
SWB
SWC
SHDN
REFOUT
CCM
REFEN
BURST
R4
17.4k
RT
RT
15k
RLIM
75k
80
SWD
VOUTS
VOUTA
VOUTB
VOUTC
VOUTD
COUT
4.7µF
×4
LTC3425
SYNCIN
C3
0.1µF
L1
2.7µH
ILIM
GNDA
SGND
GNDB
CIN: TAIYO YUDEN JMK107BJ225MA
COUT: TAIYO YUDEN JMK212BJ475MG (×4)
FB
COMP
SS
SYNCOUT
PGOOD
GNDC GNDD
RFF
10k
CFF
22pF
R2
1M
C2
47pF
R1
590k
+
EFFICIENCY (%)
VIN
2V TO 3V
VOUT
3.3V
2.2A
CIN
2.2µF
CBULK
220µF
4V
40
30
10000
Figure 3. Eficiency vs load of 3.3V boost,
using automatic Burst Mode operation
CSS
0.047µF
pin, allowing the use of large value
feedback resistors for maximum light
load eficiency.
3.3V/Li-Ion to 5V/2.4A
Boost Application
with Active Clamp
Because of the bulk capacitor on
VOUT in this example, only a single
compensation capacitor is required.
The feed-forward network, consisting of RFF and CFF, reduces output
ripple in Burst Mode operation and
further improves transient response
during load steps. It also lowers the
high frequency impedance at the FB
L1
2.7µH
50
VIN = 2.4V
VOUT = 3.3V
10 f = 1MHz/PHASE
L = 2.7µH
0
1
10
100
1000
0.1
LOAD CURRENT (mA)
Figure 2. 2-cell to 3.3V boost application
VIN
3.3V
60
FIXED
FREQUENCY
MODE
20
L1-L4: TDK RLF5018T-2R7M1R8
CBULK: SANYO 4TPC220M
voltage variation. In this example,
the Burst Mode threshold is set by
R4 to 100mA. When the average load
current drops below 100mA, the part
enters Burst Mode operation, when the
load current increases again, it leaves
Burst Mode operation and returns to
ixed frequency operation. Capacitor
C3 ilters the switching ripple at the
Burst pin.
Burst Mode
OPERATION
70
L2
2.7µH
L3
2.7µH
L4
2.7µH
Figure 4 shows the LTC3425 in a 5V
boost application. This circuit can deliver 5V at 2.4A from a single Li-Ion
cell, or from a 3.3V supply. That’s 12W
of output power in a 475mm2 (0.74in2)
footprint with a component height of
only 2.5mm. As Figure 5 shows, the
eficiency peaks at 95%. Output ripple
D1
CS
0.47µF
×2
D2
D3
D4
VIN
VOUT OFF ON
REFOUT
SWA
SWB
SHDN
REFOUT
C1
0.1µF
CCM OFF ON
REFOUT OFF ON
CCM
REFEN
SYNC
SYNCIN
BURST ON OFF
BURST
ILIM
RLIM
75k
SGND
SWD
VOUTS
VOUTA
VOUTB
VOUTC
VOUTD
Q1
COUT
4.7µF
×4
LTC3425
RT
RT
15k
SWC
GNDA
GNDB
CIN: TAIYO YUDEN JMK107BJ225MA
CS: TAIYO YUDEN LMK107BJ474KA
COUT: TAIYO YUDEN JMK212BJ475MG (×4)
CBULK: SANYO 6TPC150M
FB
COMP
SS
SYNCOUT
PGOOD
GNDC GNDD
C2
68pF
CSS
0.047µF
R3
330k
R2
1M
R1
324k
RFF
10k
CFF
15pF
R4
100k
+
CBULK
150µF
6.3V
VOUT
5V
2.5A
PGOOD
D1 TO D4: MOTOROLA MBR0520L
L1 TO L4: TDK RLF5018T-2R7M1R8
Q1: ZETEX ZXM61P02F
Figure 4. Li-Ion/3.3V to 5V boost application with active clamp
4
Linear Technology Magazine • September 2003
DESIGN FEATURES
100
90
VIN = 3.6V BURST MODE
EFFICIENCY (%)
80
VOUT
50mV/DIV
VIN = 3.3V
BURST MODE
70
60
VIN = 3.6V
50 1MHZ/PHASE
40
VOUT
20mV/DIV
VIN = 3.3V
1MHZ/PHASE
30
2.2A
IOUT
1A/DIV
20
200mA
10
0
0.1
1
VIN = 3.6V
500ns/DIV
VOUT = 5V
CO = 4 • 47µF + 150µF POSCAP
10k
10
100
1k
LOAD CURRENT (mA)
Figure 6. Li-Ion to 5V output voltage ripple at
2.5A load
Figure 5. Eficiency vs load of 5V boost
100µs/DIV
VIN = 3.6V
VOUT = 5V
CO = 4 • 47µF + 150µF POSCAP
COMP = 330k +68pF
FF = 10k + 15pF
TDK INDUCTORS
Figure 7. Step response for a 2A load step
at full load, shown in Figure 6, is less
than 20mVP–P.
In this application, Schottky diodes
are used as part of an active clamp
to limit the peak voltage seen at the
switch nodes during the anti-crossconduction time between the turn-on
and turn-off of the internal NMOS and
PMOS switches. The use of the external SOT-23 P-channel MOSFET (Q1)
and 0.47µF capacitors (CS) preserves
the output disconnect feature of the
LTC3425, allowing VOUT to go to 0V
in shutdown and limits the inrush
current. If output disconnect is not
required, Q1 and CS can be eliminated,
and the Schottky diodes can be tied
directly from SW to VOUT.
This circuit also illustrates the features and lexibility of the LTC3425.
There is a 1.22V, short circuit pro-
+
VIN = 2V TO 3V
CIN
2.2µF
L1
2.2µH
VIN
SWA
L2
2.2µH
SWB
SHDN
REFOUT
CCM
REFEN
BURST
C3
0.022µF
RT
RT
15k
RLIM
100k
ILIM
SGND
CBULK: AVX TPSD157M004R0050
CIN: TAIYO YUDEN JMK107BJ225MA
L3
2.2µH
SWC
L4
2.2µH
SWD
VOUTS
VOUTA
VOUTB
VOUTC
VOUTD
GNDA
GNDB
FB
COMP
SS
SYNCOUT
PGOOD
GNDC GNDD
COUT
4.7µF
×4
Low Cost, Very Low Proile
5W Boost Application Using
All Ceramic Caps
Many portable applications have strict
limitations on component height. This
can be a challenge for a power converter, since the inductor and ilter
capacitors are usually among the
tallest components. The LTC3425’s
4-phase architecture is ideal for these
applications. An example of a two cell
to 3.3V/1.6A boost converter with a
component height of only 1.55mm is
shown in Figure 8.
In this design, the only output ilter
capacitors needed are the four 0805
CSS
0.047µF
Figure 8. Low cost, 1.55mm proile 3.3V boost example
R2
499k
VOUT
3.3V
1.6A
R1
294k
C1
220pF
COUT: TAIYO YUDEN JMK212BJ475MG (×4)
L1 TO L4: MURATA LQH32CN2R2M51
Linear Technology Magazine • September 2003
tion. This can improve the transient
response by bringing the converter
out of Burst Mode operation prior to
a large load step. A scope photo of the
output step response, while operating
in ixed frequency mode, is shown in
Figure 7.
continued on page 9
LTC3425
SYNCIN
R4
20k
tected reference output that can be
turned on or off (for higher eficiency
at very light loads), a sync input for
synchronizing the internal oscillator to
an external clock, and an open-drain
Power Good output that monitors the
output voltage.
The CCM input allows the user to
force continuous conduction mode,
which eliminates pulse skipping at
light loads for noise sensitive applications. When CCM is pulled high, the
synchronous rectiier stays on until
a reverse inductor current of about
0.6A is sensed. Note that this lowers
the eficiency at light load, and should
only be used during ixed frequency
mode operation.
In this example, the BURST pin is
used to manually command either
ixed frequency or Burst Mode opera-
R3
100k
Figure 9. 3.3V boost demo (circuit shown in
Figure 8)
5
DESIGN FEATURES
CompactPCI Hot Swap Controller with
I2C Interface, Bus Precharge and OnChip LOCAL_PCI_RESET# Logic
by Victor Fleury
Introduction
When a board is plugged into the
live backplane of a host system (hot
swapped), the bulk bypass capacitors
of the board can draw large inrush
currents as they charge. These transient currents can damage connectors
or create glitches on the backplane,
potentially causing other boards in
the system to inadvertently reset. To
prevent such large inrush currents, the
bulk bypass capacitors on the plug-in
board must be isolated during the Hot
Swap sequence.
The LTC4240 provides a controlled
on-off switch for four hot swappable
board power supply voltages, allowing the board to be safely inserted
or removed from a live CompactPCI
(CPCI) slot without disturbing the
system power supplies. The LTC4240
includes an I2C-compatible interface
that allows software control and moniCompactPCI
BACKPLANE
CONNECTOR
(MALE)
MEDIUM 5V
LONG 5V
MEDIUM 3.3V
LONG 3.3V
CompactPCI
BACKPLANE
CONNECTOR
(FEMALE)
Z4
R1
0.005Ω
C7
0.01µF
PER
PIN
R19
2.55k
1%
10k
R25, 1.2k
R28, 200Ω
+
3VOUT
3.3V AT 7.6A
CLOAD (3VOUT)
+
R3
10Ω
3VIN
ADDRIN
SCL
SDA
PRSNT2#
PRSNT1#
3VSENSE GATE
R4
10Ω
3VOUT
5VIN
R5
1k
5VSENSE
–12V
5VIN
BD_SEL#
Z1
HEALTHY#
PCI_RST#
R13
10Ω
C4
0.01µF
EARLY
V(I/O)
R17, 1.2k
R29 R15
2k
10Ω
R14
10Ω
C5
0.01µF
R30
Z2 1k
R18
1k
R16
10k
C6
0.01µF
C1
0.047µF
5VIN
5VOUT
R10
100Ω
DGND
LED
12VOUT
VEEIN
LTC4240
+
VEEOUT
–12V AT 100mA
TIMER
FAULT
Z1, Z2: SMAJ12CA
Z3, Z4: IPMT5.0AT3
12VOUT
12V AT 500mA
CLOAD (12VOUT)
VEEOUT
OFF/ON
PWRGD
RESETIN
GND
5VOUT
5V AT 5A
CLOAD (5VOUT)
12VIN
12V
GROUND
Q2
Si7880DP
Q1
Si7880DP
C8
0.01µF
PER
PIN
R20
1.91k
R12 1%
SCL
SDA
R2
0.007Ω
Z3
3VIN
C9
10nF
Typical Hot Swap Application
Figure 1 shows a CPCI Hot Swap
application. Transistors Q1 and Q2
isolate 3.3V and 5V backplane power
supplies from the plug-in board’s bulk
capacitance. The currents through Q1
and Q2 are sensed by R1 and R2. Resistors R3 and R4 prevent high frequency
oscillations in Q1 and Q2. R5 and C1
I2C read and write functions in- stabilize the 3.3V and 5V current limit
clude:
loop. During a fault condition, R5 also
 Under a fault condition, deterserves to isolate C1 from the fast inmine which supply created the
ternal pull down resistor. Capacitors
fault
C7 and C8 are 0.01µF, per the CPCI
R22, 2.7Ω
R21, 1.8Ω
 Read the maximum allowed board
power consumption: PRSNT1#,
PRSNT2#
 Cycle board power, reset the
board after a fault condition
 Ignore faults on the +12V and
–12V supplies
Hot Swap features include:
 PRECHARGE output for biasing
I/O connector pins during board
insertion and extraction
 Circuit breakers on all four supplies with 35µs overcurrent glitch
ilters
 Foldback current limit to reduce
power dissipation while charging
large capacitive loads and during
short circuit conditions
 Supports backplanes with and
without bypass capacitors
C11
10nF
5VIN
C10
10nF
LONG V(I/O)
toring of device function and power
supply status.
C2
0.1µF
+
CLOAD (VEEOUT)
TO
QUICKSWITCH®
ENABLE
BE
RESETOUT
PRECHARGE
R11
18Ω
R6
10k
DRIVE
C3, 4.7nF
R9
24Ω
Q3
MMBT2222A
LOCAL_PCI_RST#
TO PCI BRIDGE
DEVICE OR
EQUIVALENT
R8, 1k
R7, 12Ω
3VOUT
3VIN
Figure 1. Typical CompactPCI application
6
Linear Technology Magazine • September 2003
DESIGN FEATURES
TIMER
10V/DIV
TIMER
10V/DIV
GATE
10V/DIV
GATE
10V/DIV
12VOUT
10V/DIV
5VOUT
10V/DIV
3VOUT
10V/DIV
VEEOUT
10V/DIV
12VOUT
10V/DIV
5VOUT
10V/DIV
3VOUT
10V/DIV
VEEOUT
10V/DIV
BD_SEL#
5V/DIV
BD_SEL#
5V/DIV
LCL_PCI_RST#
5V/DIV
LCL_PCI_RST#
5V/DIV
HEALTHY#
5V/DIV
HEALTHY#
5V/DIV
10ms/DIV
10ms/DIV
Figure 2. Typical power-up sequence
Figure 3. Power-down sequence
Hot Swap speciication. On-chip power
transistors isolate the –12V and +12V
supplies. Transistor Q3 and its associated components form the pre-charge
circuit.
3.3V, V(I/O) and GND, mate irst. The
short pins, which includes BD_SEL#
(OFF/ON), mate last. The 3.3V and
5V long pins must be connected to
the LTC4240 in order for the 1V
PRECHARGE voltage to be available
during early power. The following is a
typical hot-plug sequence:
 ESD clips make contact.
 Long power and ground pins
make contact and the 1V PRECHARGE becomes valid. Power
is applied to the pull-up resistors
connected to FAULT, PWRGD,
CompactPCI
Connection Pin Sequence
The staggered lengths of the CPCI
male connector pins ensure that all
power supplies are physically connected before back-end power is
allowed to ramp (BD_SEL# asserted
low). The long pins, which include 5V,
CompactPCI
BACKPLANE
CONNECTOR
(MALE)
MEDIUM 5V
LONG 5V
CompactPCI
BACKPLANE
CONNECTOR
(FEMALE)
5VIN
R22
2.7Ω
21 5V
IN
R17
1.2k
BD_SEL#
R18
1k
LTC4240*
28 OFF/ON
GND
PRECHARGE
R26
51k, 5%
LONG
5V
100Ω
Q4
MMBT3906 0.1µF
I/O PIN 1
IN
VDD
BUS SWITCH
OE
OUT
OUT
RI01
10Ω
RPRE1
10k
RI0128
10Ω
PRECHARGE OUT
1V ±10%
IOUT = ±55mA
RPRE128
10k
UP TO 128 I/O LINES
R7
12Ω
3VIN
I/O
• • •
• • •
DATA BUS
C3, 4.7nF
Q3
MMBT2222A
• • •
R27
75k
R8
1k
17
R9
24Ω
R11
18Ω
GROUND
DRIVE
18
10
Z4
I/O PIN 128
and OFF/ON pins. The status
LED is lit, indicating that the
plug-in board is in the process
of being connected (LOCAL_
PCI_RST# is asserted). All power
switches are off.
 Medium length pins make contact. There are six 5V and eight
3.3V medium length pins, bringing the 5V total to eight pins and
the 3.3V total to ten pins. The
CPCI speciication limits the DC
current to 1A/pin. The I2C latch
is initialized to allow seamless
I/O
PCI
BRIDGE
CHIP
Z4: 1PMT5.0AT3
*ADDITIONAL DETAILS OMITTED FOR CLARITY
Figure 4. PRECHARGE bus switch application circuit for 3.3V and universal Hot Swap boards
Linear Technology Magazine • September 2003
7
DESIGN FEATURES
ADDRESS BYTE
SCL
1
2
3
4
LATCH
COMMAND BYTE
COMMAND BYTE
5
6
7
8
9
1
2
3
4
5
6
7
8
9
STOP
START
0
SDA
1
ADDR 4
ADDR 3
ADDR 2
ADDR 1
ADDR 0 R/WR=0
ACK
XX
XX
C5
C4
C3
C2
C1
XX
ACK
Figure 5. Send byte timing diagram
LED
C3
C2
C1
RESETOUT
GATE
RESETIN
OFF/ON
RESETOUT
PWRGD
C1 TURNS ON THE EXTERNAL STATUS
LED INDEPENDENT OF RESETOUT.
C2 PULLS DOWN THE GATE OF THE
EXTERNAL N-CHANNEL SWITCHES. IT
ALSO TURNS OFF THE 12VIN AND VEEIN
INTERNAL POWER SWITCHES.
C3 IS USED TO SET
LOCAL_PCI_RST# (RESETOUT).
Figure 6. Send byte command byte logic.
CPCI Hot Swap operation.
The +12V and –12V supply
pins make contact at this stage.
Zener clamps Z1 and Z2 plus
shunt RC snubbers R13-C4 and
R14-C5 help protect the +12V
and –12V supply inputs, respectively, from large transient
voltages during hot insertion
and short circuit conditions.
The signal pins also connect
at this point. This includes the
HEALTHY# signal connecting to
the PWRGD pin, and the PCI_
RST# signal connecting to the
RESETIN pin.
 Short pins make contact last.
BD_SEL# signal connects to the
OFF/ON pin, thus starting the
electrical connection process. If
the BD_SEL# signal is grounded
on the backplane, the electrical
connection process begins immediately. The electrical connection
process can be interrupted at any
time via the I2C serial interface.
Power-Up Sequence
Figure 2 shows a typical power-up
timing sequence. The connection sequence is triggered by a high to low
transition on the BD_SEL# signal or
by a power cycling executed by the
I2C interface. A 65µA current source
charges the gate nodes of the external
power transistors. The power-up voltage rate of the 3VOUT and 5VOUT is
approximately given by: dV/dt = 65µA/
C1 or as determined by the current
limit and the load capacitances.
Concurrently, an 11.5µA current
source charges up the TIMER pin
capacitance. Current limit faults are
ignored until the voltage at the TIMER
pin reaches 5.5V. Once all output supply voltages have crossed their power
good thresholds, the HEALTHY# signal is pulled low (green LED turns on)
Table 1. Send byte deinition
Bit
HIGH
LOW
C5
Ignore VEEOUT Faults
Does not Ignore VEEOUT Faults
C4
Ignore 12VOUT Faults
Does not Ignore 12VOUT Faults
C3
Sets RESETOUT Low
Does not Set RESETOUT Low
Turns off all switches
Does not turn off all switches
Overrides OFF/ON Pin
Does not override OFF/ON pin
Turns on LED
Does not turn on LED
C2
C1
8
and LOCAL_PCI_RST# is free to follow
PCI_RST# and bit C3 of the I2C command latch.
Controlled Turn-Off
Allows Safe Extraction
Figure 3 shows a typical powerdown timing sequence. When either
BD_SEL# or bit C2 of the I2C command latch is set high, a 200µA current
source discharges the capacitance on
the gates of the external FETs. The internal +12V and –12V power switches
also turn off. The four power switches
are turned off slowly to avoid glitching
the power supplies. Internal resistors
discharge the output load capacitors.
Once the power-down sequence is
complete, the status LED lights up
and the CPCI card can then be safely
removed from the slot.
Disconnecting
PRECHARGE Resistors
Universal Hot Swap and 3.3V signaling
boards use a 50k, or larger, resistor to
precharge the I/O lines. Since leakage
currents at the I/O lines can be as
high as 10µA, a 10k biasing resistor
is allowed, but must be disconnected
during normal operation. Figure 4
shows an application circuit that
connects the PRECHARGE voltage
to the I/O lines during insertion, but
disconnects the resistors once the
BD_SEL# pin makes contact.
Linear Technology Magazine • September 2003
DESIGN FEATURES
ADDRESS BYTE
SCL
DATA BYTE
1
2
3
4
5
6
7
0
1
ADDR 4
ADDR 3
ADDR 2
ADDR 1
8
9
1
2
3
4
5
6
7
8
9
ACK
S7
S6
S5
S4
S3
S2
S1
S0
ACK
STOP
START
SDA
ADDR 0 R/WR=1
Figure 7. Receive byte timing
Table 2. Receive byte deinition
Table 3. Supply causing fault
S7
Logic State of the PRSNT2# Pin
FAULTCODE0
FAULTCODE1
FAULT
Supply Causing Fault
S6
Logic State of the PRSNT1# Pin
LOW
LOW
LOW
3VIN
S5
Logic State of the PWRGD Pin
LOW
HIGH
LOW
5VIN
S4
Logic State of the RESETOUT Pin
HIGH
LOW
LOW
12VIN
S3
Logic State of the RESETIN Pin
HIGH
HIGH
LOW
VEEIN
S2
FAULTCODE1 (See Table 3)
X
X
HIGH
None
S1
FAULTCODE0 (See Table 3)
S0
Logic State of the FAULT pin
The LTC4240 incorporates an I2C
compatible 2-wire (SCL, SDA) interface that allows the user to easily
query and control the status of the
LTC4240. A single analog pin selects 1
of 32 allowed addresses. The LTC4240
supports send byte and receive byte
LTC3425, continued from page 5
size, 4.7µF ceramics, with a height
of 1.35mm. Output voltage ripple is
under 50mVP–P at full load. The four
low-cost inductors are only 1.55mm
high, with a 3.2mm by 2.5mm footprint. The entire 5W power converter
can it into a 20mm by 16mm space,
as seen in Figure 9.
2- or 3-Phase Operation
For cost-sensitive applications or for
reduced board area with lower maximum current capability, the LTC3425
can be used as a 2- or 3-phase converter by simply de-populating one or
two of the inductors. Figure 10 illustrates the typical eficiency difference
between 2-, 3- and 4-phase operation.
In Burst Mode, there is no eficiency
penalty, since only phase A is used.
Linear Technology Magazine • September 2003
Conclusion
The LTC4240 provides a comprehensive solution to CompactPCI Hot
Swap applications. An integrated
I2C-compatible interface allows software control and monitoring of device
function and power supply status. The
LTC4240 control functions allow the
plug-in board to be safely inserted or
removed from a live CompactPCI slot
without disturbing the system power
supplies or I/O lines.
Conclusion: Good Things Do
Come in Small Packages
The examples here illustrate the
performance, lexibility, small size
and ease-of-use of the LTC3425. The
synchronous 4-phase architecture
achieves high eficiency over a wide
range of loads while enabling the use
of low-proile components. The four-toone reduction in output ripple current
makes it possible to achieve very low
output voltage ripple using small, lower cost ceramic capacitors. Users can
choose between automatic or manual
Burst Mode operation, pulse skipping
mode or forced continuous conduction
mode for noise sensitive applications.
All these features, along with output
disconnect, soft-start, 1µA shutdown
current, anti-ringing control, thermal
98
TJ = 25°C
96 VIN = 2.4V
VOUT = 3.3V
94 1MHz/PHASE
EFFICIENCY (%)
Control and Monitor Card
Power with I2C Interface
commands. Figure 5 and Table 1 depict
the timing and bit deinition of the send
byte command. Figure 6 schematically
outlines some of the command bit
functions. Figure 7 shows the timing
of the receive byte command. Tables
2 and 3 deine the data byte. If a fault
occurs, the FAULTCODE bits can be
used to determine which supply generated the fault.
92
90
4 PHASE
88
86
84
2 PHASE
3 PHASE
82
80
100
1000
LOAD (mA)
10000
Figure 10. Typical eficiency with 2, 3 and 4
phases (ixed frequency mode)
shutdown, a buffered reference output
and a Power Good output are packed
in a small 5mm by 5mm, thermally
enhanced QFN package.
9
DESIGN FEATURES
Low Noise, Micropower Precision Op
Amp Swings Outputs from Rail to Rail
by Kris Lokere and Glen Brisebois
Introduction
for the LT6011), the requirement to
stay 1V away from either rail leaves
less than 1V for the sensor signal, severely reducing the dynamic range. The
LT6011 allows the outputs to swing
to 40mV from either supply rail, making it practical in low supply voltage
applications.
In portable instrumentation, medical applications, or in sophisticated
systems that measure hundreds or
even thousands of variables simultaneously, the power consumption
of the precision op amp is important.
This is especially so because designers
usually want to burn as much of the
available power in the sensor itself,
since this tends to reduce noise. The
LT6011 suits all these applications
because the supply current is less
than 150µA per ampliier—instead
of the milliamps of other precision
ampliiers. In addition, micropower
operation has the obvious beneits
of increasing battery run time and
reducing system heat dissipation,
thus simplifying system design and
improving the system reliability.
250
200
INPUT OFFSET VOLTAGE (µV)
Applications that measure temperature, location or light using
thermocouples, hall-effect sensors,
or precision photodiodes can beneit
from an op amp with offset voltage of
less than 100µV, an input bias current
in the picoamps, and thermal drift of
less than 1µV/°C. Op amps that meet
these stringent requirements are available, and have been for some time, but
they tend to come in relatively large
packages, do not work with low supply voltages, and sometimes consume
milliamps of supply current.
The LT6011 dual precision op
amp its into a 3 × 3mm2 DFN package, which is so small it doesn’t even
have leads. The LT6011 also offers low
voltage, micro-power operation. A quad
version, the LT6012, is also available
in the SO-14 and GN16 packages.
Low voltage operation is useless if
the outputs of the op amp can’t swing
nearly from rail to rail. Many older op
amps clip if the output is driven closer
than 1V from either VCC or ground. This
is not a problem in systems with split
±15V supplies, but in a system with
a single 2.7V supply (the minimum
150
100
50
0
–50
–100
–150
–200
–250
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
Figure 1. The LT6011 typical input offset
drift of 0.2µV/°C is close to VOS/298K, the
theoretical minimum for a bipolar differential
pair with resistive load. Performance of a
representative sample of ampliiers shown.
Performance
Table 1 shows the precision speciications for the LT6011. While input
offset voltage is an obvious measure of
an ampliier’s precision, other speciications can affect the overall precision
of the application, and thus, should
be considered when choosing a precision op amp. The LT6011 is carefully
designed so that its low input offset
voltage is not corrupted by noise, offset
Table 1: LT6011 speciications that impact precision operation
Parameter
LT6011/LT6012
Available Packages
S8/S14
DFN/GN16
S8/S14
DFN/GN16
Input Offset Voltage (max)
60µV
85µV
75µV
125µV
Input Offset Drift (max)
0.8µV/°C
1.3µV/°C
0.8µV/°C
1.3µV/°C
Input Bias Current (max)
10
LT6011A/LT6012A
300pA
900pA
Input Noise Voltage, 0.1Hz to 10Hz
0.4µVP–P
Input Noise Voltage Density (1kHz)
14nV/√Hz
Common-Mode Rejection Ratio (min)
VCM = 1V to 3.8V , VS = 5V
107dB
Power Supply Rejection Ratio (min)
VS = ±1.35V to ±18V
112dB
Open-Loop Voltage Gain (min)
VOUT = ±13.5V, VS = ±15V, 10k load
1000V/mV
Linear Technology Magazine • September 2003
DESIGN FEATURES
NOISE VOLTAGE (0.2µV/DIV)
VS = ±15V
TA = 25°C
0
1
2
3
4 5 6
TIME (SEC)
7
8
9
10
Figure 2. As a result of low 1/f noise, the total
LT6011 input noise is only 0.4µVP-P in the
0.1Hz to 10Hz frequency band.
current, temperature drift or commonmode voltage.
The LT6011 typical input offset
drift of 0.2µV/°C is close to VOS/
298°K, the theoretical minimum for
a bipolar differential pair with ideal
resistive loads. In order to achieve this
low drift, all internal base currents
must be balanced. In addition, the
LT6011 superbeta input devices are
particularly insensitive to packaging
stresses. Figure 1 shows VOS drift for
a representative sample of LT6011
ampliiers.
Whenever microvolt levels of DC
input precision are required, low frequency noise can corrupt the readings.
At low frequencies, total noise is often
dominated by process-dependent 1/f
noise, which is inadequately captured
by looking at the higher frequency
noise density spec. In the 0.1Hz to
10Hz frequency band, total LT6011
input noise is only 0.4µVP-P (Figure 2).
Higher frequency noise, to the extent
that the application does not ilter it
out, can be calculated from the 14nV/
√Hz white-noise density.
Input bias current can easily be as
important to precision as offset voltage,
especially when using higher impedance sensors, or when large feedback
resistors are needed to maintain low
power. For a 10k total source impedance, the 300pA maximum input bias
current of the LT6011 causes only
3µV of error. The LT6011 features
internal base current cancellation,
which makes the positive and negative input bias current uncorrelated.
It is therefore not necessary to try to
balance the input impedances.
To get a better appreciation of how
low a 300pA current is, consider that
sloppy board design can easily generate leakage current much larger than
that. For example, if an input trace
at 0V (on a PCB) would run next to a
supply trace of 15V, then even 10GΩ
of parasitic resistance would cause an
extra 1500pA of input current.
Finally, in order to maintain input
accuracy over operating conditions,
you must consider the effects of
common-mode voltage, power supply voltage, and output swing. Divide
any changes in the supply voltage by
the PSRR to see how much the input
offset changes. Similarly, divide the
changes in the input common-mode
voltage by the CMRR. At a 5V supply,
the 107dB CMRR spec translates a
2.8V ΔVCM to 12.5µV of offset change
(worst case over temperature). When
VS
HALL ELEMENT
ASAHI-KASEI
HW-108A (RANK D)
www.asahi-kasei.co.jp
VS
4
LT1790-1.25
1, 2
6
7.87k
1%
100k
1%
VS = 3V TO 18V
IS ≈ 600µA
VOUT ≈ 40mV/mT
1
10k
OFFSET
VS
ADJUST
+
2
2
+
8
1/2 LT6011
1
–
49.9k
400Ω
×4
3
1k
49.9k
4
LT1782
–
3
6
26.7k
1%
5
–
1/2 LT6011
+
7
4
Figure 3. Amplifying the Hall Sensor voltage with a low-power precision ampliier allows you
to burn less power in the sensor—reducing total current consumption by a factor of 4, while
achieving 10 times the sensitivity.
Linear Technology Magazine • September 2003
the output of the op amp swings, the
gain-induced input error is calculated
from the open-loop gain spec. For the
LT6011, this translates to 12µV worstcase over temperature (3V swing at 5V
supply with 2k load).
Applications
Hall Sensor Ampliier
The circuit of Figure 3 shows the
LT6011 applied as a low power Hall
sensor ampliier. The magnetic sensitivity of a Hall sensor is proportional
to the DC bias voltage applied to it.
With a 1V bias voltage, the sensitivity of this Hall sensor is speciied as
4mV/mT of magnetic ield. At that level
of DC bias, however, the 400Ω bridge
consumes 2.5mA. Reducing the bias
voltage would reduce the power consumption, but it would also reduce the
sensitivity. This is where the beauty
of precision micropower ampliication
becomes especially apparent. First,
though, lets look at the operation of
the circuit.
The LT1790-1.25 micropower
reference provides a stable reference
voltage. Resistive ladder 7.87k:100k
attenuates this to about 90mV across
the 7.87k, and the LT1782 acts as a
buffer. When this 90mV is applied as
bias across the Hall bridge, the current
is only 230µA. This is less than 1/10
of the original value. (Just imagine if
all your batteries could last 10 times
longer than they do.)
But, as mentioned earlier, the sensitivity is now likewise reduced by the
same factor, down to 0.4mV/mT. The
way back to high output voltage is to
take gain with a precision micropower
ampliier. The LT6011 is conigured as
a differential gain block in a gain of 100.
Such high gains, and even higher, are
permissible and advantageous using
an LT6011 because of its exceptional
precision and low input drift. The output sensitivity of the circuit is raised
to a whopping 40mV/mT, with a
total supply current budget of about
600µA. (Here in Milpitas, California,
the Earth’s 50µT ield is about 60
degrees from horizontal, and causes
a 2mV output shift in the circuit.)
11
DESIGN FEATURES
VS+
CS/LD
5V/DIV
0V
LT1236-5
5
6
+
B
1/2 LT6011
–
9
0.1µF
14
13
12
11
10
VOUT
5V/DIV
0V
SUPPLY CURRENT ≅ 1.6mA TO 4mA
DEPENDING ON CODE
C2
270pF
2
1
16 15
R1
RCOM
R2 REF ROFS RFB
3
4
C1
270pF
R2
R1
5V
7
100µs/DIV
Figure 5. The output of the circuit in Figure 4
settles in less than 250µs.
VS+
VCC
5
2
–
IOUT2 6
3
+
IOUT1
16-BIT DAC
CLR
CS/LD
SCK
AGND
SDI
GND
LTC1592
SDO
8
A
1/2 LT6011
7
1
VOUT
4
VS–
8
6011 TA01
Figure 4. Functioning as reference inverter and I-to-V converter for this DAC, the LT6011
maintains 16-bit precision without adding much to the total supply current.
DAC I-to-V Converter
Figure 4 shows the LT6011 applied as
both a reference ampliier and I-to-V
converter with the LTC1592 16-bit
DAC. Whereas faster ampliiers such
as the LT1881 and LT1469 are also
suitable for use with this DAC, the
LT6011 is desirable when power
consumption is more important than
speed. The total supply current of this
application varies from 1.6mA to 4mA,
depending on code, and is almost entirely dominated by the DAC resistors
and the reference.
The DAC itself is powered only
from a single 5V supply. Op amp B of
the LT6011 inverts the 5V reference
using the DAC’s internal precision
resistors R1 and R2, thus providing
the DAC with a negative reference allowing bipolar output polarities. Op
amp A provides the I-to-V conversion
and buffers the inal output voltage.
The precision required of the I-to-V
converter function is critical because
the DAC output resistor network is
obviously very code dependent, so the
noise gain that the op amp sees is also
code dependent. An imprecise op amp
in this function would have its input
errors ampliied almost chaotically
versus code.
Since the outputs of the LT6011
swing to within 40mV of either supply
rail, the supply voltages to the ampliier
need to be only barely wider than the
desired ±5V DAC outputs.
The large signal time domain
response of the circuit is shown in
Figure 5.
How it Works
The simpliied schematic in Figure 6
shows how the op amp achieves its
precision input performance and railto-rail output capabilities.
The overall architecture features
three gain stages, providing very
high open loop voltage gain of 1MV/V.
continued on page 19
V+
R3
R6
R5
R4
Q7
Q18
Q6
Q8
Q4
Q3
–IN
D1
Q12
Q1
Q2
D5
Q14
Q17
C
B
A
D2
OUT
D4
C3
Q20
Q11
Q15
V–
D3
Q22
Q16
R1
500Ω
R2
500Ω
Q13
C2
Q21
B
A
+IN
RC1
Q5
Q19
C1
Q9
Q10
6011 SS
Figure 6. This simpliied schematic shows how the LT6011 achieves its precision input performance and rail-to-rail output capabilities.
12
Linear Technology Magazine • September 2003
DESIGN FEATURES
Addressable Bus Buffer Provides
Capacitance Buffering, Live
Insertion and Nested Addressing
by John Ziegler
in 2-WireBus Systems
Introduction
The reliability of data processing,
data storage and communications
systems depends in part on how
well the system is monitored. To this
end, input/output (I/O) cards contain circuitry to monitor parameters
such as temperature, fan speed and
system voltages. These circuits often
communicate through 2-wire serial
buses, such as SMBus or I2C.
Several practical problems can
occur in these systems, especially
as they become large. First, data
bus rise time speciications become
dificult to meet, as the SDA (serial
data) and SCL (serial clock) capacitances of each I/O card add directly
to those of the backplane, while the
pull-up impedance remains constant.
Second, cycling power whenever a new
I/O card is installed is not an option in
many uninterruptible systems. Third,
a device’s address is often dictated by
the function that it performs. If an
existing system already contains a
temperature sensor, for example,
then inserting a new I/O card with a
temperature sensor into the system
could result in multiple devices having
the same address. Finally, the likelihood of a device becoming confused
and holding the bus lines low increases
as the number of devices on the bus
increases.
The new LTC4302 addressable 2wire bus buffer addresses all of these
problems. The LTC4302 provides a
bridge between any two physically
separate 2-wire buses. SDAIN and
SCLIN connect to one 2-wire bus, e.g., a
backplane; and SDAOUT and SCLOUT
connect to a second 2-wire bus, e.g.
an I/O card. Masters on the buses
can command the LTC4302 to connect and disconnect the backplane and
Linear Technology Magazine • September 2003
card buses through software. By using
multiple LTC4302s in a system and
connecting and disconnecting them
appropriately, users can assign the
same address to multiple devices in the
system. If a large bus becomes stuck
low, the CONN pin of the LTC4302 can
be used to isolate portions of the bus,
helping the master locate the source
of the problem quickly.
When it connects the backplane
and card buses, the LTC4302 provides bidirectional buffering, keeping
the backplane and card capacitances
isolated from each other. Therefore, users can design several LTC4302s into a
large system to break its large capacitance into several smaller pieces, while
still passing the SDA and SCL signal
to all devices at the same time. Finally,
because the LTC4302’s SDA and SCL
pins default to a high impedance state
even when no VCC voltage is applied,
an LTC4302 can be inserted onto a live
2-wire bus without corrupting it. Two
general purpose input-outputs (GPIOs)
are available on the LTC4302-1. The
LTC4302-2 replaces one GPIO with a
second supply voltage VCC2, providing
level shifting between systems with different supply voltages.
Circuit Operation
Startup
A block diagram for the LTC4302-1 is
shown in Figure 1. During power-up,
the LTC4302 starts in an undervoltage
lockout (UVLO) state, ignoring any activity on the SDA and SCL pins until
the VCC voltage rises above 2.5V (typical). This ensures that the LTC4302
does not try to function until it has
suficient bias voltage. During this
time, the 1V pre-charge circuitry is
active and forces 1V through 100kΩ
nominal resistors to the SDA and SCL
pins. The 1V pre-charge minimizes the
disturbance caused by the LTC4302’s
SDA and SCL pins in hot-swapping
applications. When the LTC4302 is
being inserted into a live backplane,
the backplane SDA and SCL bus
voltages may be anywhere from 0V
to the bus pull-up supply voltage.
Pre-charging the SDA and SCL pins
to 1V minimizes the worst-case backplane-to-pin voltage differential at the
moment of connection, thus minimizing the amount of disturbance on the
backplane.
Once the LTC4302 comes out of
undervoltage lockout, the pre-charge
circuitry is shut off, and the 2-Wire
Digital Interface circuitry (shown in
Figure 1) is activated. The master on
SDAIN and SCLIN can then address
the LTC4302 and utilize its various
features, which include the Backplane-to-Card Connection circuitry
(also referred to below as “Connection
Circuitry”), Rise Time Accelerators,
and GPIO circuits. These features
default to a high-impedance state:
the Connection Circuitry and Rise
Time Accelerators are inactive, and
the GPIOs are in open-drain output
mode with their pull-down devices
turned off. The LTC4302 is in the
default state whenever it is in UVLO
or when the CONN voltage is low.
Connection Circuitry
When the connection circuitry is activated, the functionality of the SDAIN
and SDAOUT pins is identical. A low
forced on either pin at any time results
in both pins being low. SDAIN and
SDAOUT enter a logic high state only
when all devices on both SDAIN and
SDAOUT turn their pull-downs off. The
same is true for SCLIN and SCLOUT.
13
DESIGN FEATURES
This important feature ensures that
clock stretching, clock arbitration
and the acknowledge protocol always
work, regardless of how the devices
in the system are connected to the
LTC4302.
Another key feature of the connection circuitry is that, while it joins the
two buses together, it still maintains
electrical isolation between them,
thus providing capacitance buffering for both sides. This means that
devices on the backplane must drive
only the backplane capacitance plus
the low capacitance of the LTC4302
(around 10pF). The LTC4302 drives the
capacitance of the rest of the I/O card.
Likewise, devices on the card must only
drive the capacitance of the card plus
the low capacitance of the LTC4302.
The LTC4302 drives the capacitance
on the backplane. The LTC4302 is
capable of driving capacitive loads
ranging from 0pF to 1000pF on all of
its data and clock pins.
Rise Time Accelerators
Masters on the bus may activate rise
time accelerators on the backplane
side (SDAIN and SCLIN), the card
side (SDAOUT and SCLOUT), neither
or both. When activated, the accelerators switch in 2mA of pull-up current
at VCC = 2.7V and 9mA at VCC = 5.5V
during bus rising edges to quickly slew
the SDA and SCL lines once their DC
voltages exceed 0.6V and the initial
rise rate on the pin exceeds 0.8V/µs.
Figure 2 shows the rise time reduc-
LTC4302-1
2mA
INACC
1
2mA
SLEW RATE
DETECTOR
SLEW RATE
DETECTOR
SDAIN
OUTACC
SDAOUT
BACKPLANE-TO-CARD
CONNECTION
10
UVLO
100k
100k
1V
PRECHARGE
100k
100k
2mA
INACC
2
SDAIN
SDAOUT
SCLIN
SCLOUT
2mA
SLEW RATE
DETECTOR
SLEW RATE
DETECTOR
SCLIN
OUTACC
SCLOUT
BACKPLANE-TO-CARD
CONNECTION
9
+
0.55VCC
0.45VCC
–
SDAIN
+
100ns GLITCH
FILTER
CONNECT
VCC
100ns GLITCH
FILTER
–
OUT CFG2
2pF
VCC
RLIM
50k
N1
4
8
VCC
+
2.5V
2.35V
3
–
1µs
FILTER
GPIO2
DIR2
DATA2
5-BIT
A/D
ADDRESS
DECODER
ADDRESS
CONN
2-WIRE
DIGITAL
INTERFACE
7
VCC
ADDRESS
FIXED BITS
“11”
UVLO
OUT CFG1
DIR1
DATA1
INACC
OUTACC
GPIO1
GND
6
5
4302 BD1
Figure 1. Addressable 2-wire bus buffer block diagram
14
Linear Technology Magazine • September 2003
DESIGN FEATURES
OUTPUT
SIDE
50pF
INPUT
SIDE
150pF
200ns/DIV
Figure 2. Rise time accelerators reduce rise
time for CBUS = 50pF, CBUS = 150pF.
tion achieved for VCC = 3.3V and bus
equivalent capacitances of 50pF and
150pF.
General Purpose
Input/Outputs (GPIOs)
The LTC4302 -1 provides two GPIOs
that can be conigured as input, opendrain outputs, or push-pull outputs.
In push-pull mode, at VCC = 2.7V, the
typical pull-up impedance is 670Ω
and the typical pull-down impedance
is 35Ω, making the GPIO pull-downs
capable of driving LEDs. In open-drain
output mode, the logic high is provided
by connecting a pull-up resistor from
the GPIO pin to an external supply
voltage. This supply voltage can range
from 2.2V to 5.5V, independent of the
VCC voltage. The LTC4302-2 replaces
one GPIO with a second supply voltage pin VCC2 and therefore provides a
single GPIO.
BACKPLANE
CONNECTOR
BACKPLANE
VCC
5V
The application shown in Figure 3
highlights the live insertion and removal, and the capacitance buffering
features of the LTC4302. Assuming
that a staggered connector is available,
make ground and VCC the longest pins
to guarantee that SDAIN and SCLIN
receive the 1V pre-charge voltage before they connect. Make SDAIN and
SCLIN medium length pins to ensure
that they are irmly connected while
CONN is low. Make CONN the shortest
pin and connect a weak resistor from
CONN to ground on the I/O card. This
ensures that the LTC4302 remains in a
high impedance state while SDAIN and
SCLIN are making connection during
live insertion. During live removal, having CONN disconnect irst ensures that
the LTC4302 enters a high impedance
state in a controlled manner before
SDAIN and SCLIN disconnect.
Note that if the I/O card were
plugged directly into the backplane,
the card capacitance would add directly to the backplane capacitance,
making rise and fall time requirements
dificult to meet. Inserting a LTC4302
on the edge of the card, however,
isolates the card capacitance from
the backplane. The LTC4302 drives
the capacitance of everything on the
card, and the backplane must drive
only the capacitance of the LTC4302,
which is less than 10pF. As more I/O
cards are added and the system grows,
placing a LTC4302 on the edge of each
CONN Reset Pin
Grounding the CONN pin resets the
LTC4302 to its high-impedance default
state: the output side is disconnected
from the input side, the rise time accelerators on both sides are disabled,
and the GPIOs are set in open-drain
output mode with the NMOS opendrain pulldown turned off. Grounding
the CONN pin also disables the 2-Wire
Digital Interface circuitry, preventing
masters on the bus from communicating with the LTC4302. When the
CONN voltage is brought back high,
the LTC4302 remains in its default
state.
When an SDA or SCL line is stuck
low, masters can use the CONN pins
of the LTC4302s in the system to ind
the source of the problem. A master
drives one CONN pin low at a time
while monitoring the stuck bus. When
the line returns high, the master then
knows that the stuck device is on the
other side of the last LTC4302 whose
CONN pin was driven low.
PCB EDGE
BACKPLANE
CONNECTOR
I/O PERIPHERAL CARD
+
R1
10k
Live Insertion and Removal,
and Capacitance Buffering
Application
Single ADDRESS Pin
Provides 32 Addresses
The LTC4302 saves valuable board
space by providing 32 unique addresses from a single ADDRESS pin.
A resistive divider between VCC and
ground sets an analog voltage on the
ADDRESS pin. An internal A/D converter translates the ADDRESS voltage
into a 5-bit digital word, which sets
the ive LSBs of the address. The two
MSBs are hard-wired to “11.”
R3
137Ω
R2
10k
SDA
SCL
CONN
R5
200k
R4
8660Ω
C1
0.01µF
VCC
LTC4302-1
SDAIN SDAOUT
SCLIN
SCLOUT
CONN
ADDRESS GPIO2
GPIO1
GND
X1
R6
10k
R7
10k
R8
1k
R9
1k
CARD SDA
CARD SCL
LED
LED
Figure 3. LTC4302-1 in a live insertion and capacitance buffering application
Linear Technology Magazine • September 2003
15
DESIGN FEATURES
BACKPLANE
VCC
5V
I/O PERIPHERAL CARD 1
R1
10k
C1
0.01µF
R3
8660Ω
R2
10k
R6
10k
R5
10k
VCC
LTC4302-1
SDAIN SDAOUT
SCLIN
SCLOUT
CONN
ADDRESS GPIO2
GPIO1
GND
X1
SDA
SCL
R4
137Ω
CARD SDA
CARD SCL
SENSOR
ADDRESS = 1111111
ADDRESS = 1100000
I/O PERIPHERAL CARD 2
C2
0.01µF
R7
2800Ω
R9
10k
R10
10k
VCC
LTC4302-1
SDAIN SDAOUT
SCLOUT
SCLIN
CONN
ADDRESS GPIO2
GND
GPIO1
X2
R8
137Ω
CARD SDA
CARD SCL
SENSOR
ADDRESS = 1111111
ADDRESS = 1100001
Figure 4. LTC4302-1 in a nested addressing application
card breaks what would be one large,
unmanageable bus into several manageable segments, while still allowing
all segments to be active at the same
time. Moreover, the LTC4302’s rise
time accelerators provide strong pullup currents during bus rising edges,
so that even heavily loaded bus lines
meet system rise time requirements
with ease.
Address Expansion with
Nested Addressing
Figure 4 illustrates how the LTC4302
can be used to expand the number of
devices in a system by using nested
addressing. Note that each I/O card
contains a sensor device having address 1111111. If the two cards were
plugged directly into the backplane,
the two sensors would require two
different addresses. However, each
LTC4302 isolates the devices on its
card from the rest of the system until
it is commanded to connect. If masters use the LTC4302s to connect only
16
one I/O card at a time, then each I/O
card can have a device with address
1111111 and no problems occur.
5.5V to 3V Level Translator
and Power Supply
Redundancy (LTC4302-2)
Systems requiring different supply
voltages for the backplane side and
the card side can use the LTC43022 as shown in Figure 5. The pull-up
resistors on the card side connect
from SDAOUT and SCLOUT to VCC2,
and those on the backplane side conVCC
5V
R3
10k
R4
10k
R1
8660Ω
SDA
SCL
R2
137Ω
R5
10k
nect from SDAIN and SCLIN to VCC.
The LTC4302-2 functions for voltages
ranging from 2.7V to 5.5V on both VCC
and VCC2. There is no constraint on the
voltage magnitudes of VCC and VCC2
with respect to each other.
This application also provides power
supply redundancy. If either the VCC
or VCC2 supply voltage falls below its
UVLO threshold, the LTC4302-2 disconnects the backplane from the card,
so that the side that is still powered
can continue to function.
continued on page 35
C2
0.01µF
R6
10k
VCC
VCC2
LTC4302-2
SDAIN SDAOUT
SCLIN
SCLOUT
CONN
ADDRESS
GND
GPIO1
R7
10k
R8
1k
CARD VCC 3.3V
C1
0.01µF
CARD SDA
CARD SCL
LED
4203 F14
Figure 5. 5V to 3.3V level translator application
Linear Technology Magazine • September 2003
DESIGN FEATURES
Versatile Hot Swap Controller with
Open Circuit Detect, Foldback
Current Limiting and Much More
by Mark Belch
Introduction
When a circuit board is inserted into
a live backplane, the input capacitors
on the board can draw high inrush
currents from the backplane power
bus as they charge. The inrush current
can permanently damage the connector pins and board components as well
as glitch the system supply, causing
other boards in the system to reset.
The new LT4254 provides a compact
and robust solution to eliminate these
hot plugging issues.
The LT4254 is designed to turn
on a board’s supply voltage in a controlled manner, allowing the board to
be safely inserted or removed from a
live backplane having a supply voltage
from 10.8V to 36V. The device features
programmable inrush current control,
current foldback, programmable 1%
tolerance on the undervoltage and
overvoltage thresholds, overcurrent
protection, and a power good output
signal that indicates when the output
supply voltage is ready.
Power-Up Sequence
Figure 1 shows a typical LT4254
application. An external N-channel MOSFET pass transistor (Q1) is
placed in the power path to control
the turn-on/turn-off characteristics of
the supply voltage. Capacitor C1 controls the GATE slew rate, R7 provides
PWRGD
20V/DIV
CONTACT BOUNCE
VCC
20V/DIV
VOUT
20V/DIV
GATE
20V/DIV
2.5ms/DIV
Figure 2. Startup waveforms
Linear Technology Magazine • September 2003
VIN
24V
R5
0.025Ω
(SHORT PIN)
16
R1
324k
C3
0.1µF
R2
40.2k
R3
40.2k
VCC
1
D1
CMPZ5241B
11V
15
SENSE
GATE
UV
13
LT4254
2
4
10
GND
Q1
IRF530
C2
33nF
OV
OPEN
TIMER
FB
RETRY
PWRGD
GND
8
10
R6
10Ω
CL
VOUT
24V
1.5A
R8
140k
R4
27k
R7
100Ω
C1
10nF
R9
40.2k
7
5
PWRGD
UV = 20V
OV = 40V
PWRGD = 18V
Figure 1. 24V, 1.5A application
compensation for the current control
loop and R6 prevents high frequency
oscillations in Q1.
When the power pins irst make
contact, transistor Q1 is held off. The
VIN and GND connector pins should
be longer than the pin that goes to
R1 so they connect irst and keep the
LT4254 off until the board is completely seated in its connector. When the
voltage on the VCC pin is between the
externally programmed undervoltage
and overvoltage thresholds, transistor Q1 is turned on (Figure 2). The
voltage at the GATE pin rises with a
slope equal to 35µA/C1 and the supply inrush current is IINRUSH = CL •
35µA/C1, where C1 is the total load
capacitance, provided the part is not
in current limit. When the FB pin voltage goes above 4.45V, the PWRGD pin
goes high.
power dissipation in the pass transistor and to reduce voltage spikes on
the input supply during short-circuit
conditions at the output, the current
folds back as a function of the output
voltage, which is sensed internally on
the FB pin. When the voltage at the FB
pin is 0V, if the part goes into current
limit, the current limit circuitry drives
the GATE pin to force a constant 12mV
drop across the sense resistor.
Under high current (but not shortcircuit) conditions, as the FB voltage
increases linearly from 0V to 2V, the
voltage across the sense resistor increases linearly from 12mV to 50mV
(see Figure 3). With FB above 2V, a
VCC – VSENSE
50mV
Short-Circuit Protection
The LT4254 features a programmable
foldback current limit with an electronic circuit breaker that protects
against short circuits or excessive load
currents. The current limit is set by
placing a sense resistor (R5) between
VCC and SENSE. To limit excessive
12mV
0V
2V
FB
Figure 3. Current limit sense voltage vs FB pin
voltage
17
DESIGN FEATURES
IOUT
500mA/
DIV
IOUT
500mA/
DIV
VOUT
20V/DIV
TIMER
5V/DIV
TIMER
5V/DIV
VOUT
20V/DIV
GATE
1V/DIV
GATE
20V/DIV
2.5ms/DIV
2.5ms/DIV
Figure 4. Retry waveforms
Figure 5. Latch off waveforms
constant 50mV is maintained across
the sense resistor.
During startup, a large output
capacitance can cause the LT4254
to go into current limit. The current
limit level when VOUT is low is only one
quarter of the current limit level under
normal operation, and it is time limited, so careful attention is needed to
insure proper start up. The maximum
time the LT4254 is allowed to stay in
current limit is deined by the TIMER
pin capacitor.
The current limit threshold (during
normal operation) is ILIMIT = 50mV/R5,
where R5 is the sense resistor. For a
0.025Ω sense resistor, the current limit
is set at 2A and folds back to 480mA
when the output is shorted to ground.
For a 24V application, MOSFET dissipation under short circuit conditions
is reduced from 48W to 11.5W.
The LT4254 also features a variable overcurrent response time. The
time required for the part to regulate
the GATE pin voltage is a function of
the voltage across the sense resistor,
R5. This helps to eliminate sensitivity to current spikes and transients
that might otherwise unnecessarily
trigger a current limit response and
increase MOSFET dissipation.
mum current limit time is chosen, the
capacitor value is:
Current Limit TIMER
The TIMER pin provides a method for
programming the maximum time the
part is allowed to operate in current
limit. When the current limit circuitry
is not active, the TIMER pin is pulled
to GND by a 3µA current source. When
the current limit circuitry becomes active, a 120µA pull-up current source
is connected to the TIMER pin and
the voltage rises with a slope equal to
117µA/CTIMER. Once the desired maxi18
C(nF) = 25 • t(ms)
If the TIMER pin reaches 4.65V
(typ), the internal fault latch is set
causing the GATE to be pulled low
and the TIMER pin to be discharged
to GND by the 3µA current source.
The LT4254 does not turn on again
until the voltage at the TIMER pin falls
below 0.65V (typ).
Undervoltage and
Overvoltage Detection
The LT4254 uses the UV (undervoltage)
and OV (overvoltage) pins to monitor
VCC and allow the user the greatest
lexibility for setting the operational
thresholds. Figure 1 also shows the UV
and OV level programming via a 3-resistor divider (R1, R2, and R3). The UV
and OV pins are internally connected
to an analog window comparator.
If the UV pin goes below 3.6V or
the OV pin rises above 4V, the GATE
pin will be immediately pulled low
until the UV/OV pin voltages return
to the normal operating voltage window (4V and 3.65V on UV and OV,
respectively).
Automatic Restart and
Latch Off Operation
The RETRY pin can be conigured
either to latch off the LT4254 or
force it into a hiccup mode after an
overcurrent fault condition.
If the RETRY pin is loating, when
the voltage at the TIMER pin ramps
back down to 0.65V (typ), the LT4254
turns Q1 on again. If the short-circuit
condition at the output still exists, the
cycle will repeat itself indeinitely. The
duty cycle under short-circuit condi-
tions is 3%, which limits the power
dissipated by Q1, preventing overheating (see Figure 4).
If the RETRY pin is grounded, the
LT4254 latches off after a current fault
(see Figure 5). After the part latches
off, it can be commanded to start back
up by cycling the UV pin to ground
and then back high. This command
can only be accepted after the TIMER
pin discharges below the 0.65V typ
threshold (to prevent overheating
transistor Q1).
Power Good Detection
The LT4254 includes a comparator
for monitoring the output voltage.
The output voltage is sensed through
the FB pin via an external resistor
string. If the FB pin goes above 4.45V,
the comparator’s output releases the
PWRGD pin so it can be externally
pulled up. The comparator’s output
(PWRGD pin) is an open collector
capable of operating from a pull-up
voltage as high as 36V, independent
of VCC.
Open MOSFET Detection
The LT4254 can be used to detect the
presence of an open MOSFET through
the OPEN and PWRGD pins. When
the voltage across the sense resistor
is less than 3.5mV, the open collector
pull-down device is shut off allowing
the OPEN pin to be externally pulled
high.
An open MOSFET condition is
inferred when the OPEN pin is high
and the PWRGD pin is low (after the
part has completed its start-up cycle).
This condition can be falsely signaled
during start-up if the load is not activated until after PWRGD goes high; or
if the inrush current during start-up is
too small, OPEN will not go low until
the load is enabled (by the PWRGD
signal) as shown in Figure 6. During
this time, the OPEN pin is high and the
PWRGD pin is low falsely signaling an
open MOSFET condition (unless this
start-up period is ignored). To avoid
this false indication, the OPEN and
PWRGD pins should not be polled for
a period of time, TSTARTUP, given by:
TSTARTUP = (3 • VCC • C1)/35µA
Linear Technology Magazine • September 2003
DESIGN FEATURES
GATE Pin
VOUT
20V/DIV
VOUT
20V/DIV
GATE
20V/DIV
GATE
20V/DIV
OPEN
5V/DIV
OPEN
5V/DIV
PWRGD
20V/DIV
PWRGD
20V/DIV
2.5ms/DIV
2.5ms/DIV
Figure 6. Normal MOSFET start-up waveforms
Figure 7. Open MOSFET start-up waveforms.
For example, in Figure 6, TSTARTUP
is equal to 3 times the typical start-up
time, which is 25.5ms (3 × 8.5ms).
This can be accomplished either by
using a microcontroller and not polling
the logic signals during TSTARTUP or by
placing an RC ilter on the OPEN pin.
Once the OPEN voltage exceeds the
monitoring logic threshold (signaling
an undercurrent condition lasting
longer than the start-up period), and
PWRGD is low (signaling that the
output is not high after the start-up
period has inished), an open MOSFET
condition is indicated.
Figure 7 shows the typical waveforms for an actual open MOSFET
condition. Since the MOSFET is open,
VOUT and PWRGD never go high. OPEN
goes high as soon as the part is powered up while GATE is clamped to the
external Zener voltage above VOUT.
Another condition that can cause
a false open MOSFET indication is if
the LT4254 goes into current limit
during start-up. This causes TSTARTUP
to be longer than anticipated. Also,
if the LT4254 stays in current limit
long enough for the TIMER pin to
fully charge up to its threshold, the
LT4254 will either latch off (RETRY =
0) or go into the current limit hiccup
mode (RETRY = loating). In either
case, an open MOSFET condition will
be falsely signaled. If the LT4254 does
go into current limit during start-up,
C1 can be increased (to reduce inrush
current).
LT6011, continued from page 12
Differential pair Q1 and Q2, together
with load resistors R3 and R4, form
a irst gain stage. The PNPs Q5 and
Q6, and current mirror Q9 and Q10
form the second gain stage. The output
stage is designed to be able to both
source and sink much larger currents than the stage biasing current.
The current-sinking device NPN Q20
is driven directly by Q12, while the
current-sourcing PNP Q19 is driven
through level-shifting bias network
Q13 and Q14.
The level-shifter works as follows:
The ixed current lowing into diodes
D3–D5 establishes a bias voltage at
the base of Q13. As the base of Q14
is driven lower, the VBE of both Q13
and Q14 increases. This increases
their current, which lows through
Linear Technology Magazine • September 2003
Q18/R6 and is mirrored as sourcing
current in Q19. Since only collectors
are connected to the output, a mere
40mV VCE saturation voltage limits the
output swing to either supply rail.
Input devices Q1 and Q2 are superbeta transistors. Their lightly doped
base region results in a current gain
of more than 1000. In addition, the
already low base current is internally
compensated by a base current-cancellation circuit. Current mirror Q21
biases Q11 with the exact same current
as the input devices. Q17 measures
the base current of Q11 and feeds this
same current back into the bases of
Q1 and Q2. The resulting input bias
current is limited only by mismatch
and is typically just 20pA.
The GATE pin is clamped to a maximum of 12V above the VCC voltage.
This clamp is designed to withstand
the internal charge pump current. An
external Zener diode must be used if
the possibility exists for an instantaneous low resistance short from VOUT
to GND. When the input supply voltage
is between 12V and 15V, the minimum
gate drive voltage is 4.5V, and a logic
level MOSFET must be used. When
the input supply voltage is higher
than 20V, the gate drive voltage is at
least 10V, and a standard threshold
MOSFET is recommended.
Conclusion
The LT4254’s comprehensive set of
advanced protection and monitoring
features make it applicable in a wide
variety of Hot Swap solutions. It can
be programmed to control the output
voltage slew rate and inrush current.
It has programmable undervoltage and
overvoltage protection, and monitors
the output voltage via the PWRGD
pin. The part also indicates if an open
MOSFET condition exists. The LT4254
provides a simple and lexible Hot Swap
solution with the addition only a few
external components.
The input offset voltage of the ampliier is a result of mismatch in Q1/Q2
as well as R3/R4. These internal load
resistors are trimmed at the factory to
cancel out the total offset voltage to
less than 60µV (A-grade). A high degree
of balance is maintained through the
second stage, which virtually eliminates second-order temperature drift
contributions.
Conclusion
Rail-to-rail output swing to supplies
as low as 2.7V, power consumption as
low as 400µW, and availability in tiny
packages make the LT6011 op amp the
ideal precision op amp for low voltage,
low power, or space constrained applications.
19
DESIGN FEATURES
Micropower SOT-23 Boost
with Integrated Schottky Diode
Provides Output Disconnect and
by Leonard Shtargot
Short Circuit Protection
Introduction
The LT3464 is the only micropower
boost converter in the industry to
combine a 36V NPN power switch,
power Schottky diode, and output
disconnect into an 8-lead ThinSOT.
This unprecedented level of integration saves several external components
while offering true output disconnect,
making it possible to generate outputs
of up to 34V with a zero current shutdown while using a mere 40mm2 of
board area (refer to Fig. 1).
In addition to component savings, the LT3464 offers a low typical
switch current limit of 115mA and fast
switching, a combination that allows
the use of a tiny chip inductor and tiny
ceramic capacitors. The LT3464 also
features Burst Mode control (see Figure 2), which results in highly eficient
operation over a wide range of load
currents and a low quiescent current
of only 25µA typical. The CTRL pin of
the LT3464 acts much like a dial on a
lab power supply—it allows the output
voltage to be varied, which is useful
in applications for purposes such as
LCD contrast adjustment.
L1
10µH
VIN
2.3V
TO
10V
7
6
VIN
SW
OUT
1
C1
1µF
CTRL
LT3464 CAP
8
SHDN
FB
R2
4.53M
R1
301k
Figure 1. The integrated Schottky diode and output disconnect transistor result in a tiny solution
occupying as little as 40mm2.
The LT3464’s small size and high eficiency make it an especially attractive
power solution for portable electronics
requiring long battery life and compact
circuitry. See Figure 3 for a simpliied
block diagram of the LT3464.
Output Disconnect
In a simple boost circuit (Figure 4)
there exists a DC path from the input
CTRL
1
supply (VIN) through the inductor and
diode to the load (VOUT), effectively leaving the load connected to VIN during
shutdown. The resulting current drain
during shutdown is unacceptable in
many applications, requiring the addition of several external components
to isolate the load from VIN. To save
space and complexity, the LT3464 is
equipped with a PNP that completely
VIN
SW
CAP
OUT
7
6
5
3
2
VOUT
50mV/DIV
+
–
–
DELAY
S
Q
R
Q
OUT
ANTI
SAT
+
1.25V
OUT
12mV
–
20
C2
0.1µF
VOUT
20V
C1: TAIYO YUDEN LMK107 BJ105MA-T
C2: TAIYO YUDEN TMK107 BJ104MA-T
C3: TAIYO YUDEN TMK107 BJ104MA-T
L1: TAIYO YUDEN LB 2012T100MR
IL
0.1A/DIV
Figure 2. Burst Mode waveforms showing low
output ripple. The LT3464 consumes only
25µA typical when not switching.
2
4
FB
5µs/DIV
5
C3
0.1µF
GND
CPL
VIN = 5V
VOUT = 20V
ILOAD = 1mA
L = 22µH
3
SHDN 8
0.1Ω
VREF
4
GND
Figure 3. LT3464 block diagram showing integrated NPN switch, Schottky diode and output
disconnect PNP.
Linear Technology Magazine • September 2003
DESIGN FEATURES
LT3464
SIMPLE BOOST
VOUT
VIN
DISCONNECT
PNP
…
SHDN
VOUT
DRV
SW
5V/DIV
VIN = 5V
CAP PIN VOLTAGE
GND
VOUT
…
Figure 4. A simple boost circuit with LT3464’s output disconnect allows the complete solution to
draw less than 0.5µA during shutdown. The output disconnect is designed with a 25mA current
limit to protect the circuit during short circuit conditions.
disconnects the load from the Schottky
diode during shutdown (see Figures 4
and 5). During normal operation, the
control circuitry turns on the PNP and
keeps it just out of saturation, resulting in low VCE(SAT) and low quiescent
current. In addition, the disconnect
circuit has a built in current limit
25
VIN = 4V
OUTPUT VOLTAGE (V)
20
15
10
5
0
0
0.25
0.5 0.75
1
1.25 1.5
CONTROL PIN VOLTAGE (V)
1.75
Figure 6: Using the CTRL Pin as an auxiliary
reference input to control the output voltage
of 25mA to protect the chip during
a short-circuit at the output. This
feature allows the LT3464 to tolerate
an indeinite short, but care must be
taken to avoid exceeding the maximum
junction temperature.
Using the CTRL Pin
The LT3464 features an auxiliary reference input that provides an easy way
to vary the output voltage for purposes
such as LCD contrast adjustment or
display dimming. When the CTRL pin
held at or above 1.25V, the LT3464
uses the internal 1.25V reference, but
when a voltage lower than 1.25V is
applied to the CTRL pin, that voltage
becomes the new reference. Figure 6
shows the output voltage versus the
CTRL pin voltage for a 20V output
circuit. Note that the LT3464 will not
regulate the output to a voltage lower
than the input.
VIN = 5V
VOUT = 20V
ILOAD = 1mA
L = 22µH
1ms/DIV
Figure 5: The output disconnect isolates the
output load from the input supply during
shutdown. CAP Pin voltage is the output of the
Schottky in Figure 4.
LT3464 ±20V
Dual Output Converter
Figure 7 shows a single-inductor dualoutput converter for applications that
require both a positive and negative
voltage. The positive output is generated by a simple boost set up, whereas
the negative output is generated using
an inverting charge pump. Although
well regulated, the negative output will
have a slight offset from the positive
output because the external diodes
have a different on voltage when
compared to the integrated Schottky
diode.
1-Cell Li-Ion to 16V
Boost Converter
Figures 8 and 9 show that the LT3464
performs well in applications that need
a high output voltage at a relatively
continued on page 24
L1
47µH
VIN
2.3V TO 10V
C5
D1
0.33µF
VIN
SW
OUT
1
CTRL
LT3464 CAP
8
L1
22µH
VIN
2.3V TO 10V
6
7
C1
1µF
D2
–VOUT
–20V
C4
0.33µF
SHDN
FB
3
5
2
C3
0.22µF
C2
0.33µF
GND
4
C1: TAIYO YUDEN LMK107 BJ105MA-T
C2, C4, C5: TAIYO YUDEN GMK212 BJ334MG-T
C3: TAIYO YUDEN UMK212 BJ224MG-T
L1: MURATA LQH32CN470K
D1, D2: CENTRAL CMDSH-3
Figure 7. ±20V Dual output converter
Linear Technology Magazine • September 2003
VOUT
20V
R2
4.53M
R1
301k
7
6
VIN
SW
OUT
C1
1µF
1
CTRL
LT3464 CAP
8
SHDN
FB
3
5
2
C3
0.22µF
C2
0.33µF
GND
VOUT
16V
3.48M
294k
4
C1: TAIYO YUDEN LMK107 BJ105MA-T
C2: TAIYO YUDEN GMK212 BJ334MG-T
C3: TAIYO YUDEN EMK107 BJ224MA-T
L1: MURATA LQH32CN220K
Figure 8. Li-Ion to 16V boost converter
21
DESIGN FEATURES
Ampliier with Integrated Filter Offers
the Best High Speed, Low Noise
Interface for Differential
by Michael Kultgen
DACs and ADCs
Introduction
Differential signal paths are becoming a popular way to improve system
performance. A differential signal has
twice the amplitude for a given supply
level. Interference from other components, digital clocks for example,
become common mode signals and
are rejected by the ampliiers in the
differential signal chain. Hence, with a
differential signal path, dynamic range
can be maintained while the supply
voltage is reduced.
Differential output op amps are
one means of providing gain, buffering, and iltering in these signal
paths, but often at the price of added
complexity and board real estate. A
circuit using a differential output
op amp typically requires twice the
number of resistors and capacitors
as the corresponding single-ended
circuit. Therefore, there is a need for
a compact, high performance means
to process differential signals. The
solution is the new LT6600.
The LT6600 is a family of fully differential ampliiers with an integrated 4th
order lowpass ilter. Each device in the
family features a ixed cutoff frequency
(2.5MHz, 10MHz and 20MHz) and op10
–10
60
50
–30
40
–50
GROUP DELAY
30
20
–60
10
–70
0
–80
100k
1M
10M
FREQUENCY (Hz)
VMID
7
V+
V–
OUT –
6
5
RF
PROPRIETARY
LOWPASS
FILTER STAGE
11k
V–
+
OP AMP
+ –
–
VOCM
–
VOCM
+
– +
RF
1
VIN–
IN –
RIN
PASSBAND GAIN =
2
3
4
VOCM
V+
OUT +
RF
RIN
WHERE RF =
{
402Ω FOT THE LT6600-10 AND LT6600-20
1580Ω FOR THE LT6600-2.5
Figure 1. LT6600 block diagram
erates with power supplies ranging
from 3V to 10V. The LT6600 is packaged in an SO-8, and is pin-for-pin
compatible with other commercially
available high-speed differential op
amps (Figure 1). Like their industry
counterparts, the LT6600 ampliiers
can accept single-ended or differential
input signals, translate common mode
voltages, and have a common mode
input range that extends to ground.
But, unlike these other ampliiers,
the LT6600s have a proprietary architecture that minimizes noise and
distortion while maximizing speed.
Furthermore, the custom lowpass ilter
200Ω
402Ω
43pF
402Ω
VI
287Ω
82pF
402Ω
287Ω
10pF
200Ω
+
OP AMP #1
–
162Ω
82pF
200Ω
162Ω
402Ω
+
OP AMP #2
VO
–
43pF
+
VI
LT6600
402Ω
VO
–
10pF
402Ω
200Ω
100M
Figure 2. The frequency response of the
LT6600-10
22
IN +
11k
70
MAGNITUDE
–20
–40
RIN
8
80
GROUP DELAY (ns)
MAGNITUDE (dB)
0
VIN+
THE COMPETITION
THE BETTER WAY
Figure 3. The LT6600 vs the competition
Linear Technology Magazine • September 2003
DESIGN FEATURES
5V
12pF
SINGLE ENDED
ANALOG INPUT
0.1µF
24.9Ω
1:1
24.9Ω
100Ω
100Ω
12pF
24.9Ω
24.9Ω
V+
+
AIN
–
12pF
LTC174x DOUT
V–
VCM
12pF
Figure 4. Using a transformer to drive a differential ADC
5V
SINGLE ENDED INPUT
REFERENCED TO VCM
+
U1
5V
–
12pF
24.9Ω
24.9Ω
12pF
24.9Ω
100Ω
+
V+
+
AIN
24.9Ω
–
12pF
LTC174x DOUT
V–
VCM
U2
–
4.7µF
499Ω
499Ω
A Great Solution for
Differential ADC and
DAC Interfaces
Figure 5. Using single-ended op amps to drive a differential ADC
DC GAIN =
A
RIN
WHERE A =
{
402Ω FOT THE LT6600-10 AND LT6600-20
1580Ω FOR THE LT6600-2.5
LT6600
RIN
0
800mVP-P
SINGLE ENDED INPUT
REFERENCED TO GND
1
7
0.01µF
t
VIN
RIN
2
8
–
VMID
VOCM
+
5V
5V
3
12pF
+
–
49.9Ω
4
49.9Ω
5
12pF
6
V+
+
12pF
AIN
–
LTC174x DOUT
V–
VCM
1µF
V
VCM
0
VOUT+
VOUT–
3.2VP-P
DIFFERENTIAL SIGNAL
TO THE ADC
t
Figure 6. Using the LT6600 to drive a differential ADC
response provides 30dB attenuation
at 3 times the cutoff frequency with
low delay distortion (Figure 2).
discrete active-RC design would
require 18 precision resistors and
capacitors, as well as a second operational ampliier package (Figure 3).
Quiet, Compact and
The irst available devices in the family
Easy to Use
are the LT6600-2.5, the LT6600-10,
The LT6600s are also the most and the LT6600-20, with ixed ilter
compact anti-alias/smoothing ilter bandwidths of 2.5MHz, 10MHz, and
solutions available. These integrated 20MHz respectively.
ilter-ampliiers need only two external
The LT6600-2.5 offers true 14-bit
resistors to set the gain. The precision performance with noise and distortion
response is completely determined by components below –86dB for 1MHz
the monolithic ilter. By contrast, a 1VRMS inputs. The LT6600-10 has a
Linear Technology Magazine • September 2003
total noise of 56µVRMS in a 10MHz
bandwidth with harmonics below
–74dB for 5MHz 2VP–P signals. With
the gain set to +12dB, the LT660020 has 42µVRMS total input referred
noise in a 20MHz bandwidth and
shares many features of the -2.5 and
-10. Each member of the family has a
lowpass response with less than 0.5dB
of passband ripple. These combinations of low noise, low distortion and
controlled frequency response are
practically impossible to duplicate
with discrete designs.
The LT6600s are speciied and
tested for both single 3V supply
operation and ±5V supply operation.
This lexibility, combined with the low
external parts count and the wide input common mode range, makes the
LT6600 extremely easy to use.
Differential output ampliiers have
gained popularity in systems that
have differential input ADC converters. Often the signal to be processed
by the converter is single-ended, low
amplitude, and from a large source
impedance. For the converter to realize its full range and accuracy, it must
be presented with a larger differential
signal and a common mode level near
mid supply. There are two common
solutions to this problem. Figure 4
shows a transformer coupling circuit
and Figure 5 shows an operational
ampliier circuit. The circuit shown
in Figure 5 is preferable when size
and DC response are important, when
gain is needed, or when buffering is
required. The circuit of Figure 4 is useful for wide bandwidth applications.
Figure 6 shows how simple the differential converter interface is with the
LT6600. This circuit retains all of the
beneits of Figure 5’s circuit (gain, DC
response, and single-ended to differential conversion) with the added feature
of selective anti-alias iltering. Furthermore, the single-ended analog input
can have a common mode level that
differs from the ADC converter (unlike
the circuit of Figure 5). The LT6600
automatically translates the common
23
DESIGN FEATURES
VLT6600 OUT = IDAC •
1+
A
R2 R2
+
R1 R3
WHERE A =
R3
432Ω
+
“I”
DIGITAL
INPUT
–
7
2
8
R2 402Ω
R3
432Ω
3.3V
3.3V
R3
432Ω
R2
402Ω
R1
66.5
–5V
R2 402Ω
R3
432Ω
3.3V
+
4
VCC
LT6600-10
LT5503
3.3V
BI
–5
+
390Ω
8.2pF
2.7nH
0°
90°
MODIN
3.3V
0.1µF
7
0.1µF
3
–
6
1
R1
66.5Ω
LTC1666/7
DIN (Q CHANNEL DAC) IOUT
10mA FS
–
1
0.1µF
+
“Q”
DIGITAL
INPUT
R2
402Ω
R1
66.5
–5V
5V
3.3V
0.1µF
R1
66.5Ω
LTC1666/7
DIN (I CHANNEL DAC) IOUT
10mA FS
402Ω FOT THE LT6600-10 AND LT6600-20
1580Ω FOR THE LT6600-2.5
3.3V
3.3V
5V
{
2
8
MOI
1.2pF
3.3V
+
4
LT6600-10
–5
+
8.2pF
VGA
1.2pF
3
–
18nH
2.7nH
BQ
GND
DMODE
MixEN
ModEN
GC1
GC2
6
Figure 7. Using the LT6600 as a transimpedance ampliier and smoothing ilter in a base station application.
mode level when it converts the singleended input to differential. In Figure
6, the input signal is referenced to
ground and the signal presented to
the ADC is referenced to VCM.
To illustrate the excellent dynamic
range of the LT6600, consider Figure 6
with a 1MHz input signal of 800mVPP
ampliied by an LT6600-2.5. With RIN
= 402Ω, the ampliier provides 12dB
of voltage gain. The signal presented
to the ADC converter is 3.2VP–P. The
distortion components will be at least
82dB below the fundamental, and the
signal-to-noise ratio will be 81dB in a
5MHz bandwidth.
The differential output DAC is another application where the LT6600
excels. Figure 7 shows the LT6600
acting as a transimpedance ampliier
and a 4th order smoothing ilter, in
LT3464, continued from page 21
90
80
VIN = 8.4V
EFFICIENCY (%)
VIN = 4.2V
70
low delay distortion in the passband
(Figure 2), making for an outstanding
DAC smoothing solution.
low current. As shown in Figure 9,
high eficiency is maintained with low
output currents.
For further information on any
of the devices mentioned in this
issue of Linear Technology, use
the reader service card or call the
LTC literature service number:
Conclusion
60
50
40
30
0.01
a base station application. The input
common mode range of the LT6600
accommodates the compliance range
of the DAC. The output common mode
voltage of the LT6600 is set to optimize
the performance of the LT5503 direct
I/Q modulator. The resistors between
the DAC and the LT6600 allow the user
to adjust the transimpedance gain. The
LT6600 and LT5503 are operating on
a 3.3V power supply.
To illustrate the optimized iltering
of the LT6600, consider the case where
the DAC in Figure 7 has a sample rate
of 50Msps and the baseband signal
information extends to 10MHz. By using an LT6600-10, the attenuation of
the images near 40MHz would be more
than 50dB (ilter response plus sin(x)/x
attenuation). The excellent rejection
in the stopband is combined with
0.1
1
10
LOAD CURRENT (mA)
100
The LT3464 in the ThinSOT package
produces an ultra compact boost
solution featuring high eficiency,
low quiescent current, true output
disconnect, and low external parts
count.
Conclusion
The LT6600 differential ilter-ampliiers are the most compact ADC
anti-aliasing and DAC smoothing
solutions available in the 2.5MHz
to 20MHz range. The combination of
low noise, low distortion, and precision
response are impossible to replicate
with discrete designs. The LT6600 is
pin compatible with standard differential output op amps and performs
all of the same functions. The LT6600
improves the design of any system
requiring differential signal buffering
and iltering.
1-800-4-LINEAR
Ask for the pertinent data sheets
and Application Notes.
Figure 9. Eficiency for the circuit in Figure 7
24
Linear Technology Magazine • September 2003
DESIGN FEATURES
Low Voltage Ampliiers Give
Choice of Accuracy or Speed
by Frank Johnston, Glen Brisebois and Danh Tran
Table 1 summarizes the performance
of the devices. Note that input offset
voltage and input bias current are
speciied and guaranteed with the
common mode voltage near each rail.
Histograms of input offset voltage are
shown in Figures 3 and 4. The large
signal transient response is shown in
Figures 5 and 6. The response is clean
with no aberrations.
rent of the PNP input pair. When Q1
and Q2 are active, the current in
Q16 matches the current in Q1 and
Q2, thus the base current of Q16 is
nominally equal to the base current
of Q1/Q2. The base current of Q16
is mirrored by devices Q17, Q18 and
Q19 to each input. The cancellation
is effective for common mode voltage
5
600
VS = 5V, 0V
4
INPUT BIAS CURRENT (nA)
3
2
1
0
–1
–2
–3
0
1
2
3
4
COMMON MODE VOLTAGE (V)
5
Figure 1. LT1803 IB vs common mode voltage
35
30
200
0
–200
–400
–600
–4
–5
VS = 5V, 0V
400
–800
35
VS = 5V, 0V
VCM = 0V
30
25
20
15
10
5
0
–1250
0
1
2
3
4
COMMON MODE VOLTAGE (V)
5
Figure 2. LT6220 IB vs common mode voltage
PERCENT OF UNITS (%)
Performance
a folded cascode coniguration formed
by Q8, Q9, Q11 and Q12, which provides most of the voltage gain. A pair
of complementary common emitter
devices, Q14 and Q15, creates an
output stage which can swing from
rail to rail.
In the input stage, devices Q18
and Q19 act to cancel the bias cur-
INPUT BIAS CURRENT (µA)
Two new families of single, dual and
quad ampliiers, the 1mA LT6220/1/
2 and the 3mA LT1803/4/5, provide
high speed ampliication on supplies as
low as 2.5V. The 85MHz LT1803 series
is optimized for large signals, with a
100V/µs slew rate, while the 60MHz
LT6220 series focuses on excellent
DC performance at low current, with
a maximum input offset speciication
of only 350µV. Both series have railto-rail output stages that can swing to
within 20mV of the rails, and rail-torail inputs that can be used anywhere
within the supplies. The supply range
is 2.5 to 12V. DC accuracy is insured
by trimming of the input offset voltage
and cancellation of input bias current.
Figures 1 and 2 show the results of a
proprietary bias current cancellation
circuit.
The devices are available in small
packages; singles in the SOT-23, and
duals in the DFN as well as the larger
SO packages.
PERCENT OF UNITS (%)
Introduction
VS = 5V, 0V
VCM = 0V
25
20
15
10
5
750
–250 0 250
–750
INPUT OFFSET VOLTAGE (µV)
1250
Figure 3. LT1803 offset voltage distribution
0
–250
150
–50 0 50
–150
INPUT OFFSET VOLTAGE (µV)
250
Figure 4. LT6220 offset voltage distribution
Circuit Description
Figure 7 shows a simpliied schematic
of the ampliiers. The circuit is composed of three distinct stages: an input
stage, an intermediate stage, and an
output stage. The input stage consists
of two differential ampliiers, a PNP
stage (Q1 and Q2) and an NPN stage
(Q3 and Q4), that are active over different portions of the input common
mode range. The intermediate stage is
Linear Technology Magazine • September 2003
1V/DIV
1V/DIV
100ns/DIV
Figure 5. LT1803 slew rate
100ns/DIV
Figure 6. LT6220 slew rate
25
DESIGN FEATURES
Table 1. Speciications of LT1803 and LT6220 at 25°C, VS = 5V, 0V
Parameter
Conditions
LT1803
LT6220
Units
–3dB Bandwidth
AV = 1
60
55
MHz
85
60
MHz
100
20
V/µs
3.0
1.0
mA (Max)
2.5 to 12
2.5 to 12
V
2
0.35
VCM = V–,SOT-23
5
0.85
VCM = V–+1V
750
150
VCM = V+
5500
600
66
85
dB (Min)
Gain-Bandwidth Product
Slew Rate
RL = 1k
Supply Current
Operating Supply Range
VCM =
Input Offset Voltage
Input Bias Current
V–,
SO-8
CMRR
mV (Max)
nA (Max)
PSRR
VS = 2.5V to 10V, VCM = 0V
68
86
dB (Min)
Input Voltage Noise
f = 10kHz
21
10
nV/√Hz
Harmonic Distortion
VS = 5V, AV = 1, RL = 1k, VO = 2VP–P,
fC = 500kHz (LT6220)
fC = 1MHz (LT1803)
–75
–75
dBc
AVOL
VS = 5V, VO = 0.5V to 4.5V, RL = 1k
20
30
V/mV (Min)
IL = 0mA
60
40
IL = 15mA (LT1803)
IL = 20mA (LT6220)
300
650
IL = 0mA
60
40
IL = 15mA (LT1803)
IL = 20mA (LT6220)
600
900
Output Voltage Swing LOW
Output Voltage Swing HIGH
mV (Max)
V+
V+
+
V–
ESDD1
I2
R5
R4
R3
+
D1
ESDD2
Q12
Q11
I1
Q13
+IN
D6
D5
D8
D2
Q5
CC
Q4 Q3
ESDD4
D3
Q18
OUT
V–
V+
D4
BUFFER
AND
OUTPUT BIAS
Q10
Q9
Q16
Q17
I3
Q1 Q2
ESDD3
V–
+
VBIAS
D7
–IN
Q15
C2
Q8
C1
Q19
Q7
Q14
Q6
R1
R2
V–
Figure 7. Simpliied schematic
26
Linear Technology Magazine • September 2003
DESIGN FEATURES
R2
10k
R1
1k
VIN
VIN
50mV/DIV
GND
–
A
1/2 LT1804
VOUT
+
VS+
C1
0.1µF
R6
1M
B
1/2 LT1804
50µs/DIV
Figure 9. Inverting DC restore oscillograph
+
D1
1N4148
R3
1k
–
R5
2k
D2
1N4148
VOUT
500mV/DIV
GND
R4
100k
VS = ±5V
18045 TA01
VS–
Figure 8. Inverting DC restore
greater than the saturation voltage of
Q18 and Q19, about V– + 0.2V, up to
the voltage that the PNP devices switch
off, about V+ – 1.3V.
Inverting Ampliier
with DC Restore
The circuit of Figure 8 shows half of the
LT1804 used as a gain of –10 ampliier,
and the other half as a DC restore.
This type of circuit is often associated with photomultiplier tubes and
photodiodes (see Figure 10), which are
inherently unipolar but can be subject
to annoying DC components caused
by ampliier offsets, dark current, and
the presence of residual light. The
oscillograph in Figure 9 shows how effectively the circuit rejects the varying
DC level which the incoming negative
going pulses are riding on (top trace).
The pulses are inverted and restored to
a 0V ground reference (bottom trace)1.
Note that this is not the same as AC
coupling, which would simply center
the average output waveform around
ground. The DC restore function has
three operating regions: output high
or “ignore,” output low or “restore,”
and output zero or “lock.”
When the output is high, op amp
B’s output falls low turning D1 on and
D2 off. This leaves the pull down R6
in place, so the voltage on C1 falls
slowly. Therefore the positive output
voltage also starts to fall back towards
ground via op amp A. The long time
constant of R6 • C1 is what makes
this the “ignore” function. Of course,
it does not fully ignore positive outputs, as that would make the circuit
useless. The point is, though, that a
positive signal indicates the presence
of signal, so the restore circuit does
little to zero the output.
When the output is low, however,
we have a situation where we have
negative light. Since that situation is
unlikely to exist outside of academic
circles, we can assume that we have
zero light, or at least are at the light
signal loor, and would like to set that
as the DC reference level. To that end,
op amp B’s output goes high turning
D1 off and D2 on. This now leaves
R5 to pull up on C1 about 500 times
harder than R6 had pulled down.
Again, through op amp A, this positive
going voltage causes the output to rise
quickly. When the output reaches 0V,
op amp B detects this and pulls down
on D1, stopping the restore function
and entering “lock” mode.
In lock mode, light is presumably
absent, and the output is held close
to 0V. D1 and D2 are both on, and
although they are running different
currents, the resultant mismatch voltage is relatively small output referred
because of the high gain around op
amp B. Should a negative going “light
present” pulse occur at VIN, the circuit
goes again into ignore mode.
Photodiode Ampliier
The circuit in Figure 10 is a stepped
gain transimpedance photodiode ampliier. At low signal levels, the circuit
has a high 100kΩ transimpedance
gain, but at high signal levels the
circuit automatically and smoothly
changes to a low 3.1kΩ gain. The
beneit of a stepped gain approach
is that it maximizes dynamic range,
continued on page 29
VS+
R2
3.24k
3
VS+
R1
100k
IPD
PHOTODIODE
~4pF
INFINEON SFH213
C1
1pF
VS+
–
LT6220
+
R4
10k
PHILIPS
BCV62
C2
30pF
4
Q1
PHOTO
CURRENT
100µA/DIV
Q2
2
VS
1
–
R3
33k
LT1634-1.25
VOUT
0.5V/DIV
GND
VOUT
VS = ±1.5V TO ±5V
VS–
Figure 10. Photodiode ampliier
Linear Technology Magazine • September 2003
5µs/DIV
Figure 11. Stepped gain photodiode ampliier
oscillograph
27
DESIGN FEATURES
Feature-Rich Battery Charger that
Manages Both Battery Charging and
by John Shannon
Bus Voltage Regulation
Introduction
Until now power management in
portable devices has required a mix
of major components to fulill the basic functions of battery charging and
generation of system supply voltages.
A typical solution requires at least two
major devices (and associated external components): one charger IC for
charging the battery and another IC
to supply a regulated system bus voltage from a constantly changing battery
voltage. The LTC1980 is a single-device
solution that manages both battery
charging and generation of the regulated system bus voltage.
way through the converter, a fact that
is exploited to charge or discharge the
battery, depending on the power needs
of the system.
The battery charger portion of the
LTC1980 is a full-featured, constant
current, constant voltage, Li-Ion
charger with timer termination. The
LTC1980 can be set up for either 1- or
2-cell, and 4.1V or 4.2V chemistries.
This switch mode charger maintains
high eficiency over a wide range of
input voltages. The lyback topology
allows any input voltage to generate
any output voltage, unlike buck or
boost topology chargers that require
the input voltage to be always higher
or always lower than the battery voltage.
Powerful Features
The LTC1980, in simple terms, controls the power low between the AC
adapter, a battery and the system bus.
The basic LTC1980 circuit is a synchronous lyback converter. In such
a coniguration, power can low either
+
4.1V
Li-Ion
BATTERY
C1
68µF
VBAT
+
BH511-1014
D1*
1N5819
3.3V
+
5.1Ω
•
1nF
If the AC adapter is present and has
suficient voltage then the LTC1980
VREG
•
5.1Ω
Charging (AC Power Present)
enters charge mode. In charge mode
power lows from the adapter to both
the system bus and the battery. The
charger uses a constant current, constant voltage algorithm that is suitable
for Li-Ion cells. Deeply discharged
batteries are trickle charged with a
low current until the battery voltage
exceeds the trickle charge threshold,
at which point full current charging
commences. The switch mode operation of the charger typically keeps
eficiency above 80%, which results
in less heat generation compared to
a linear charger. Adapter power also
lows directly to the system bus via a
linear regulator. The eficiency of the
linear converter is simply the ratio of
the system bus voltage to the adapter
voltage, so losses are minimized if the
adapter voltage is close to the desired
system bus voltage.
C4
68µF
OPTIONAL PASS
TRANSISTOR
FOR LDO FDC636P
VLDO 3.1V
1nF
1/2 FDC6401N
1/2 FDC6401N
C6
470µF
R5
154k
50mΩ
RSENSE
14
BGTDR
18
VBAT
23
OVP
3
REGFB
22
CAOUT
PROG
R9
10k
1
R10
110k
R11
1M
12
20
PGND
21
GND ISENSE
11
7
6
5
2
VC
C11
1nF
TIMER
4
C7
0.27µF
24
C8
0.1µF
WA
15
REG
16
MODE
9
BATT1
10
BATT2
SS
17
R6
100k
8
RGTDR VREG LDODRV LDOFB
LTC1980
PROGT
DCOUT
VBIAS1
C9
1µF
200pF
R8
169k
WALL
ADAPTER
ACIN
SYSTEM LOAD
DC/DC
CONVERTERS
VOUT
R15
300k
R7
100k
VBIAS2
13
C10
0.33µF
19
R12
100k
R14
100k
*OPTIONAL DIODE FOR
SHORTED WALL ADAPTER
TERMINAL PROTECTION.
C12
82pF
R13
806k
Figure 1. Typical application for single Li-Ion cell
28
Linear Technology Magazine • September 2003
DESIGN FEATURES
Discharging (Battery Mode)
When the adapter input falls, so that
the system bus voltage requirements
can no longer be met, the LTC1980
switches to the regulator mode. In this
mode the LTC1980 no longer functions
as a battery charger. It instead acts
as a battery discharger. Power lows
“backwards” from the battery to the
linear regulator. The output voltage
of the lyback, which is input to the
linear regulator, should be as low as
possible in order to maximize eficiency
and battery run time. The eficiency
of the battery to system bus voltage
conversion can be as high as 88%.
The Linear Regulator
A low dropout regulator, using an
external P-FET as the pass element,
regulates the system bus voltage. The
linear regulator takes its power from
the output of the AC adapter. Dissipation in the linear regulator is lowest
when the AC adapter voltage is near the
system bus voltage. When the system
is in battery discharging mode, the
voltage input to the linear regulator is
the output of the synchronous lyback
converter. This voltage should be set
to be only a percent or two above the
required output voltage (allowing for
LT1803 and LT6220, continued from page 27
which is very useful on limited supplies. Put another way, in order to get
100kΩ sensitivity and still handle a
1mA signal level without resorting to
gain reduction, the circuit would need
a 100V negative voltage supply.
The operation of the circuit is quite
simple. At low photodiode currents
(below 10µA) the output and inverting input of the op amp are no more
than 1V below ground. The LT1634
in parallel with R3 and Q2 keep a
constant current though Q2 of about
20µA. R4 maintains quiescent current through the LT1634 and pulls
Q2’s emitter above ground, so Q1 is
reverse biased and no current lows
through R2. So for small signals, the
only feedback path is R1 (and C1) and
the circuit is a simple transimpedance
ampliier with 100kΩ gain.
As the signal level increases though,
the output of the op amp goes more
Linear Technology Magazine • September 2003
VADAPTER
2V/DIV
IBAT
500mA/DIV
VADAPTER
2V/DIV
BATTERY CHARGING
BATTERY CHARGING
BATTERY
DISCHARGING
0V
0V
BATTERY
DISCHARGING
IBAT
500mA/DIV
200µs/DIV
200µs/DIV
Figure 2. Adapter voltage and battery current
(adapter removal)
Figure 3. Adapter voltage and battery current
(adapter insertion)
IR drops in the pass element). This
prevents saturating the gate drive
to the pass element and will aid in
transient recovery.
Figure 1 shows a typical application circuit for charging a single 4.1V
Li-Ion cell. The adapter voltage can
vary from 4V to 9V, demonstrating one
key advantage of the lyback topology.
Figures 2 and 3 show battery current
and adapter voltage during the transition from battery charging (adapter
present) to regulator mode (battery
discharging). The load on the linear
regulator is 200mA, supported either
by the battery or the adapter. When
the adapter is present the battery is
charged at about 650mA. Once the
wall adapter is removed the battery
is discharged as power lows back
through the synchronous lyback
converter to support the 200mA load
on the linear regulator.
negative. At 12.5µA of photodiode current, the 100kΩ gain dictates that the
LT6220 output is about 1.25V below
ground. At that point, however, the
emitter of Q2 is at ground, and the
base of Q1 is one Vbe below ground.
Thus, Q1 turns on and photodiode
current starts to low through R2. The
transimpedance gain is therefore now
reduced to R1||R2, or about 3.1kΩ.
The circuit response is shown in Figure
11. Note the smooth transition between
the two operating gains, as well as the
linearity of both regions.
reduced supply current, lower input
offset voltage, lower input bias current, and higher DC gain than other
devices with comparable bandwidth,
which is critical in circuits having high
input impedance, such as active ilters, or in circuits having precision
requirements, such as current sensing
ampliiers. The LT1803 and LT6220
series are offered in a variety of small
packages including a 3mm × 3mm
dual ine pitch leadless package with
the standard dual op amp pinout and
also in the SOT-23 package for a single
ampliier. The combination of speed,
DC accuracy and low power makes the
LT1803 series and the LT6220 series
a preferred choice for battery powered,
low voltage signal conditioning.
Conclusion
The LT1803 series and LT6220 series
deliver exceptional performance, and
the rail-to-rail inputs and outputs of
these devices maximize signal dynamic range while simplifying design
for single supply systems. The LT1803
series and the LT6220 series feature
Conclusion
The LTC1980 manages both battery
charging and system voltage regulation, which is typically the work of
two separate devices and their corresponding external circuitry. This
feature combined with the fact that the
design of the LTC1980 also allows for
battery voltages either above or below
the adapter voltage, greatly simpliies
the task of integrating a battery and
adapter into a portable device.
Notes
1 A DC bias on op amp B’s + input could set the
output restore to some other reference voltage.
29
DESIGN IDEAS
Synchronous, Phase Modulated, Full
Bridge Converter Targets Isolated High
by Kurk Mathews
Power Applications
Introduction
In networking and telecom equipment,
power supplies provide isolated low
voltage outputs from the 48V input
supply rail, with the added requirements of high eficiency (to reduce
heat dissipation) and low component
height. These requirements become
even more dificult to meet with increased power levels, because of the
corresponding component power dissipation and increased transformer
size. Simple power supply topologies
give way to more complex single and
two-stage approaches that focus on
transformer and semiconductor utilization.
One such approach, the phase
modulated full bridge converter, is a
popular choice for high power supplies. Unfortunately, until now, there
has not been a controller that offers
both the lexibility in timing control
and features (such as synchronous
rectiier outputs) to manage a variety
of high power applications. The new
LTC3722-1 current-mode controller
DESIGN IDEAS
Synchronous, Phase Modulated, Full
Bridge Converter Targets Isolated
High Power Applications ..............30
Kurk Mathews
Monolithic Buck-Boost Converter
Provides 1A at 3.3V without
Schottky Diodes ...........................32
Mark Jordan
Inductorless, Eficient Step-Down
DC/DC Converter Provides
Dual Low Noise Outputs
in Space-Constrained Designs.......33
Bill Walter
Using Current Sensing Resistors
with Hot Swap Controllers and
Current Mode Voltage Regulators..34
Eric Trelewicz
Complete USB Solution Provides
PowerPath Control and Input
Current Limiting while Charging
a Li-Ion Battery ............................36
Trevor Barcelo
30
Figure 1. LTC3722-1 36–72V input to 12V/35A isolated power supply
is designed speciically with these
issues in mind, providing a full-featured controller for high power, phase
modulated, full bridge converters.
12V Isolated Converter
Figures 1 and 2 show a 36V–72V
input to isolated 12V at 35A supply
using the LTC3722EGN-1 (24-lead
SSOP) and LTC4440 high side drivers. The low proile design features
surface mount power MOSFETs and
planar transformers (less than 0.4”
high) conigured in a parallel/series
coniguration. With a 48V input, this
circuit has a typical full load (35A)
eficiency of 93%. The PCB board
shown in Figure 1 is 3"× 5", and with
200 linear feet per minute of airlow
provides full load operation from 48V
input to 50°C ambient without the use
of a heat sink. The actual PCB area
can be reduced further (depending
on airlow and ambient temperature)
when used as part of a large system
board.
Even with 12V output, the synchronous rectiiers reduce the power
dissipation in the secondary rectiiers.
The output of 12V is chosen here because it is a good intermediate bus
voltage, but the circuit is easily modi-
ied to meet other input or output
voltages. For example, applications
not requiring the full input voltage
range or tight regulation could further
optimize transformer and semiconductor utilization resulting in increased
eficiency.
Operation
The start-up of the circuit in Figure 2
begins with C14 trickle charging via
R29 and Q41's base-collector junction
until U2’s VIN pin reaches 10.2V (the
internal shunt regulator voltage). Assuming the undervoltage lockout pin
(UVLO) is above a 5V threshold, switching begins. C14 keeps the U2’s VIN
pin above its 6.0V shutdown threshold
until a bias winding on T4 (along with
D12, D14 and L4) takes over. U4 and
U5 provide the level translation for the
two high side switches. U2’s OUTE and
OUTF pins provide synchronous timing signals to the output rectiiers gate
drive transformer T5 and the LTC1693
gate driver. The loop is closed by U3,
the LT1431 programmable reference,
and optocoupler ISO1.
Operation of the phase modulated
full bridge converter is similar to a
conventional full bridge converter in
continued on page 35
Linear Technology Magazine • September 2003
Linear Technology Magazine • September 2003
30.1k
C2
0.82µF
100V
0.1µF
1.5nF
12V
D27
12V
1µF
10
100Ω
11
2
9
5VREF
Q10
Q7
12V
220pF
8
20
C
19
0.02Ω
1.5W
499Ω
D
17
ISNS
4
15
180pF
+
D
8
CS
OUTE
16
24
10k
13
33k
5
6
22
D26
120k
68nF
23
7
Q35
4
3
2.2nF
330pF
750Ω
5VREF
75k
8
•
1
7
6
5
6
•4
•3
D22
8
3
C30
2.2nF
250V
4
ISO1
MOC207
330pF
4.7k
100k
2
330Ω
1
D12
Si7852DP
×2
D14
5
0.33µF
Si7852DP
×2
51Ω
2W
T5
1(1.5mH):0.5:0.5
L4
1mH
Q16
Q9
12V
0.22µF
0.1µF
ISNS
22Ω
C14
68µF
20V
12V
2
CT SPRG RLEB FB GND PGND SS COMP
U2
LTC3722-1
5.1k
1
D24
0.33µF
51Ω
2W
•
11
220pF
100Ω
1/4W
D20
5.1V
6
5
7
GNDF GNDS RMID
+
2.49k
9.53k
0.1µF
D5
D1
–VOUT
+VOUT
Q26
1µF
C13, C36
180µF
16V
×2
C1
0.82µF
100V
13k
1/2W
–VOUT
22nF
10k
D16
4.3V
Q18
+VOUT
Si7852DP
×4
VHIGH
820pF
200V
15Ω
1.5W
+VOUT
4440 TA03
2
4
V+ COMP RTOP
LT1431
8
1
COLL U3 REF
3
2.7k
470Ω
1/4W
7
5
OUT2
OUT1
3 LTC1693-1 6
IN2
VCC2
1
8
IN1
VCC1
2
4
GND2 GND1
–VOUT
Q25
•
L1
0.85µH
VHIGH
Si7852DP
×4
T4
5:5(105µH):1:1 Q17
•7
8
• 10
11
•7
8
• 10
0.047µF
D17
D15
1
6
2•
4
2•
4
T1
5:5(105µH):1:1
D21
Figure 2. LTC3722-1 36–72V input to 12V/35A isolated synchronous full bridge power supply
2
21
L2
150nH
Si7852DP
×2
0.02Ω
1.5W
B
3
12V
VCC
LTC4440EMS8E
6
BOOST
1
Si7852DP
7
U5
IN
C
TG
×2
GND GND TS
OUTA OUTB OUTC OUTD OUTF
A
0.22µF
DPRG NC SYNC
150k
14
UVLO VREF
VIN
B
8
TS
SBUS ADLY PDLY
220pF
4
GND GND
0.47µF
12
18
4.99k
Q41
MMBT3904
20k
D23
VCC
LTC4440EMS8E
6
BOOST
1
7
U4
IN
A
TG
3
C3, C4, C5
0.82µF
100V
×3
12V
VIN
C1-C5: VITRAMON VJ1812Y824KXBAT
C13, C36: SANYO 16SP180M
C14: AVX TPSE686M020R0150
C30: MURATA DE2E3KH222MB3B
D1, D5, D21, D22: MURS120T3
D12, D14, D23, D24: BAS21
D15, D17, D26: BAT54
D16: MMBZ5229B
D20: MMBZ5231B
D27: MMBZ5242B
L1: PA1294.910
L2: PULSE PA0651
L4: COILCRAFT DO1608C-105
L5: SUMIDA CDEP105-1R3MC-50
Q7, Q9, Q25, Q26: ZETEX FMMT619
Q10, Q16-Q18: ZETEX FMMT718
Q35: MMBT3906
T1, T4: PULSE PA0526
T5: PULSE PA0297
R29
20k
1/4W
182k
VIN
+VIN
36V TO
72V
–VIN
L5
1.3µH
+VOUT
–VOUT
12V
35A
+VOUT
+VOUT
DESIGN IDEAS
31
DESIGN IDEAS
Monolithic Buck-Boost
Converter Provides 1A at 3.3V
by Mark Jordan
without Schottky Diodes
Introduction
Inside the LTC3441
The LTC3441 patented control technique provides smooth and continuous
transfer from buck, buck-boost and
boost modes while maintaining a
constant frequency at no load. The
operating frequency is factory set to
1MHz and can be synchronized up to
1.7MHz. For light loads, the part offers
user controlled Burst Mode operation
to maximize battery life, drawing only
25µA of quiescent current. To limit
inrush current at start-up, an external
RC network can be connected to the
SHDN/SS pin to control output voltage rise time.
The LTC3441 is available in a small
3mm by 4mm low thermal resistance
12-lead DFN package.
L1
4.7µH
4
9
2.7V TO 4.2V
1
32
*
CIN
10µF
Li-Ion
7
3
SW2
5
340k
8
VOUT
12
LTC3441
VIN
FB
11
SHDN/SS
VC
2
MODE/SYNC GND
6
PGND
PGND
PVIN
*1 = Burst Mode OPERATION
0 = FIXED FREQUENCY
COUT
22µF
15k
1.5nF
200k
CIN: TAIYO YUDEN JMK212BJ106MG
COUT: TAIYO YUDEN JMK325BJ226MM
L1: TOKO A916CY-4R7M
Figure 1. Li-Ion to 3.3V at 1A boost converter
response. For applications requiring
optimum transient response an additional pole/zero pair to broaden the
loop will achieve the desired results.
Figure 2 shows that the converter can
achieve 95% peak eficiency without
the use of Schottky diodes.
100
90
80
Not Just a Buck-Boost
4
9
10
1M
Li-Ion
0.047µF
C1
10µF
1
*
70
60
VIN = 4.2V
50
VIN = 2.7V
40
VIN = 3.6V
30
10
VOUT = 3.3V
0
0.1
1
7
3
*1 = Burst Mode OPERATION
0 = FIXED FREQUENCY
SW1
10
IOUT (mA)
100
1000
Figure 2. Eficiency curves for the converter
in Figure 1
The Schottky diode limits the voltage
spikes on the SW2 pin.
L1
4.7µH
2.5V TO 4.2V
Burst Mode
OPERATION
20
The LTC3441 can also be conigured as
a boost converter with output disconnect as shown in Figure 3. The 5V at
600mA converter from a Lithium-Ion
battery demonstrates peak eficiencies
of over 94%. Input current at start-up
is also controlled by the LTC3441, reducing the load burden on the battery.
Single Inductor Li-Ion to
3.3V/1A Converter
Figure 1 shows a 3.3W converter
powered from a single Lithium-Ion
battery. The single inductor topology
of the LTC3441, along with all ceramic
capacitors, minimizes critical board
real estate. Dominant pole compensation is shown as a simple means to
compensate the converter’s transient
10
SW1
VOUT
3.3V
1A
EFFICIENCY (%)
The power density and small form factor of lithium-Ion batteries makes them
the power source of choice for many
portable devices. A SEPIC converter
topology is a popular way to provide a
regulated bus voltage that falls within
the 2.7V to 4.2V battery range, but a
SEPIC converter has some laws. It
offers mediocre eficiency and requires
coupled inductors and a high current
lyback capacitor. The LTC3441 1A
buck-boost converter offers a compact
and eficient alternative that requires
only a single inductor and very few
external components.
D1
SW2
VOUT
5V
600mA
5
8
VOUT
12
LTC3441
VIN
FB
11
SHDN/SS
VC
2
MODE/SYNC GND
6
PGND
PGND
R1
619k
PVIN
COUT
22µF
R3 15k
C4 1.5nF
R2
200k
C1: TAIYO YUDEN JMK212BJ106MG
C2: TAIYO YUDEN JMK325BJ226MM
D1: MBRM120LT3
L1: TOKO A916CY-4R7M
Figure 3. Li-Ion to 5V at 600mA boost converter with output disconnect
Linear Technology Magazine • September 2003
DESIGN IDEAS
Inductorless, Eficient Step-Down
DC/DC Converter Provides Dual
Low Noise Outputs in Spaceby Bill Walter
Constrained Designs
Introduction
Increase Battery Run Time
Linear Technology’s new LTC3252
switched capacitor step-down DC/
DC converter squeezes dual adjustable outputs into a space saving 3mm
by 4mm DFN package. Each output is
programmable within a range of 0.9V
to 1.6V, is capable of 250mA of current, and operates from a single 2.7V
to 5.5V supply. To keep the converter
footprint small, the LTC3252 operates
at high frequency, allowing the use of
tiny low cost ceramic capacitors—no
inductors are required.
The LTC3252 also features Burst
Mode® operation, which allows the
LTC3252 to achieve high eficiency
even with lightly loaded outputs. While
in Burst Mode operation the LTC3252
delivers a minimum amount of charge
for a few cycles then goes into a low
current state until the output drops
enough to require another burst of
charge. A current sense circuit is used
to detect when the required output
current of both outputs drops below
about 30mA. When this occurs, the
oscillator shuts down and the part
goes into a low current operating
state. The LTC3252 remains in the
low current operating state until either
output has dropped enough to require
another burst of current. The current
transferred to the output is limited
by internal circuitry, thus providing
a nearly ixed output ripple of about
12mVP–P. The unloaded operating current of the part is just 35µA with one
output enabled and 60µA with both
outputs enabled.
Improve Eficiency
and Save Space
Figure 1. A complete dual output Li-Ion
converter
The 2-to-1 switched capacitor fractional conversion architecture of the
LTC3252 is twice as eficient as a linear
regulator, which translates to battery
run times that are double that of an
LDO. Five tiny ceramic capacitors and
four surface mount resistors are all
that are required for operation.
Magnetic Interference). Regulation is
achieved by sensing the output voltage
and regulating the amount of charge
transferred per cycle. This method of
regulation provides much lower input
and output ripple than that of conventional switched capacitor charge
pumps. The spread spectrum feature
of the LTC3252 randomly modulates
the charge transfer rate between 1.0
MHz and 1.6MHz on a cycle-by-cycle
basis. Modulating the frequency in
this manner virtually eliminates high
frequency harmonic EMI that can be
conducted into other circuits.
Reduce Noise
The LTC3252 employs a unique spread
spectrum architecture that continually switches, which not only provides
a low input and output noise, but also
signiicantly reduces EMI (ElectroOFF ON
OFF ON
1-CELL
Li-ION
OR 3-CELL
NiMH
4.7µF
2
11
3
4
1µF 6
10
1µF 8
7
EN1
OUT1
EN2
FB1
VIN
C1 +
C1 –
5
1
OUT2
C2 –
GND
4.7µF
510k
LTC3252
C2 +
470k
VOUT = 1.5V
IOUT ≤ 250mA
FB2
9
12
261k
VOUT = 1.2V
IOUT ≤ 250mA
4.7µF
510k
Figure 2. Space saving, low noise, inductorless dual output DC-DC converter: Li-Ion to
1.5V/250mA and 1.2V/250mA
Linear Technology Magazine • September 2003
Circuit Protection Features
The LTC3252 has built-in short-circuit current limiting as well as over
temperature protection. During a
short-circuit condition the part automatically limits the output current to
approximately 500mA. The LTC3252
shuts down and stops all charge
transfer when the IC temperature
exceeds approximately 160°C. Under
normal operating conditions, the part
should not go into thermal shutdown
but the function is included to protect
the IC from excessively high ambient
temperatures, or from excessive
power dissipation inside the IC (i.e.,
over-current or short circuit). The
continued on page 37
33
DESIGN IDEAS
Using Current Sensing Resistors with
Hot Swap Controllers and Current
by Eric Trelewicz
Mode Voltage Regulators
Introduction
Current mode switching regulators
and Hot Swap controllers—such as the
LTC1622 regulator and the LTC4210
Hot Swap controller—use a sub-50mV
voltage across a sense resistor in a
high-current (Amps to tens of Amps)
path to control the current. Failure
to properly Kelvin sense the current
across the sense resistor is the most
common cause of circuit malfunction
in current mode power supplies and
Hot Swap circuits.
Problems usually arise when the
layout of the circuit does not take into
account the high currents and small
resistances involved. For instance, a
low value precision sense resistor in the
mΩ range is typically used to measure
current in Hot Swap controllers and
current mode switching regulators. A
typical 0.003Ω, 1W sense resistor in a
2512 surface mount package is only
MULTIPLE VIAS TO
INPUT POWER PLANE
(MINIMIZES INPUT VOLTAGE DROP)
BACKPLANE PCB EDGE
CONNECTOR CONNECTOR
(FEMALE)
(MALE)
RSENSE
0.01Ω
LONG
VIN
5V
Z1
OPTIONAL
CON
RON2
10k
LONG
GND
0.125 inches wide and 0.250 inches
long. Consider the same length copper trace with a typical thickness of
0.0014 inches (1oz copper laminate).
The resistance across a quarter inch
Q1
RC
CC
GND
RG
GATE RESISTOR
CL0SE TO Q1 GATE
Q1 GATE
TO LOAD
CTIMER
CON1
GND
RON1
RON2
GND
CLOAD
ON
MULTIPLE VIAS TO
OUTPUT POWER PLANE
(MINIMIZES OUTPUT VOLTAGE DROP)
Figure 2. Example of proper Kelvin sense connections. The important features shown here are:
short connections to terminals of Kelvin sense resistor, expanded copper to heat sink Q1, and
multiple vias connecting power in and the load to pass FET Q1 for minimal voltage drop.
34
TIMER
RC
100Ω
CC
0.01µF
GND
CTIMER
0.22µF
GND
of copper trace is 0.0009Ω at room
temperature. Adding a quarter inch
of copper to the measurement path
induces a sense measurement error of
0.0009Ω/0.003Ω, or 30%! The circuit
simply wouldn’t work, because it would
prematurely trip the current limit.
Pitfalls Lie in the Layout
POWER IN
Cx
LTC4210
RG
100Ω
Figure 1. This Hot Swap circuit controls current by sensing the voltage across a small value
resistor, RSENSE—a method called Kelvin sensing. The layout of this circuit is important for
accurate current sensing.
COPPER TO
SPREAD HEAT
ON Q1 DRAIN
Z1
ON
SENSE
GATE
VOUT
5V
470µF 4A
CLOAD
Z1: ISMA10A OR SMAJ10A
RSENSE
Rx
RX
10Ω
CX
0.1µF
RON1
20k
SHORT CONNECTION
TO 4-TERMINAL
KELVIN-SENSED RESISTOR
LTC4210
+
VCC
SHORT
Q1
Si4410DY
The printed circuit board layout process is full of pitfalls, especially when
an auto-router is part of the process.
When one terminal of the sense resistor
is the power plane, the sense pin on
the IC and the terminal of the current
sense resistor can end up connected
across a signiicant span of copper,
with uncontrolled current low from
other circuits on the board lowing
between the resistor and IC connections. Excess voltage drop and noise
coupling are a prescription for circuit malfunction. With many designs
outsourced to PCB design houses, the
circuit designer faces a formidable task
of controlling the layout.
What can be done?
Several resistor manufacturers1 now
sell 4-terminal Kelvin current sense
Linear Technology Magazine • September 2003
DESIGN IDEAS
EXCESSIVELY LONG SENSE PATH
CREATES SIGNIFICANT VOLTAGE DROP
THAT CAUSES FAULTY OPERATION
LARGE SENSE LOOP AREA
SUSCEPTIBLE TO EMI
Rx
Cx
GND
RSENSE
GND
Setting the Proper
Constraints in an
Auto-Router
Z1
POOR HEAT
SINKING
POWER IN
Q1
LTC4210
EXCESS VOLTAGE DROP
CAUSES FAULTY OPERATION
RC
CTIMER
that can inductively couple with the
sense loop and also cause malfunction. To minimize inductive coupling,
the Kelvin sense circuit must exhibit
minimal loop area.
RG
Q1 GATE
CC
EXCESS VOLTAGE DROP
CAUSES FAULTY OPERATION
CON
RON1
GND
CLOAD
GND
RON2
ON
Figure 3. Example of layout that can reduce the accuracy of Kelvin sensing. The problems
shown here include: excess length of thin high resistance track in series with sense resistor,
inadequate heat sinking on Q1, and an insuficient number of vias for input power and output
load connections.
resistors. The use of a 4-terminal resistor forces the auto router to make
a correct Kelvin connection to the curLTC3722, continued from page 30
that power is delivered when diagonal switches are on. It differs in that
during the free-wheeling portion of
the switching cycle, either the top or
bottom switches of the bridge remain
on. This provides for recovery of parasitic energy and zero-voltage turn-on
transitions for the primary switches.
The LTC3722-1 can be conigured to
provide adaptive (with programmable
time-out) or ixed delay control for
zero voltage switching operation. In
adaptive DirectSense™ mode, the
rent sense resistor. But this alone is
not enough. High speed switch mode
power supplies have a high dI/dt path
Set the auto-router constraints to
route the Kelvin sense connections
as a differential pair to keep the
connections side by side and close
together. Use maximum length constraints to prevent the connections
from wandering too far from the direct
path. Constrain the connection to the
component layer on a multi-layer PC
board to prevent unwanted vias in this
critical connection path. Although the
proper choice of sense resistor and
layout constraints can mitigate many
of the PCB layout pitfalls, in the end it’s
up to the designer to carefully check
the layout.
Notes
1 Some sources of 4-terminal Kelvin sensed resistors include:
• www.Caddock.com
• www.IMS-Resistors.com
• www.IRCtt.com
• www.Vishay.com
turn-on timing adjusts automatically
by sensing the transition voltages on
the bridge legs, eliminating external
trims. This provides accurate zero voltage transition timing with changes in
input voltage, output load and circuit
parasitics. Fixed (or manual) delay
control is also available, which allows for ixed transition delays or even
custom dynamic timing schemes. The
LTC3722-1 also features adjustable
synchronous rectiier timing.
Conclusion
into live systems and break one large
capacitive bus into several smaller
ones, while still passing the SDA and
SCL signals to every device in the
system. They can also connect and
disconnect different bus segments
at different times, providing nested
addressing capability and easing the
debugging process during stuck low
situations.
The new LTC3722-1 current-mode
controller provides a wealth of features targeted at high power isolated
full bridge applications, including
lexible timing control, synchronous
rectifier outputs, under -voltage
lockout, programmable slope compensation and current mode leading
edge blanking.
LTC4302, continued from page 16
Summary
The LTC4302-1/LTC4302-2 addressable 2-wire bus buffers ease
the practical issues associated with
complex 2-wire bus systems. They
allow I/O cards to be hot-plugged
Linear Technology Magazine • September 2003
35
DESIGN IDEAS
Complete USB Solution Provides
PowerPath Control and Input
Current Limiting while Charging
by Trevor Barcelo
a Li-Ion Battery
Introduction
An increasing number of portable
handheld devices are using the Universal Serial Bus (USB) to exchange
data with a host computer. Now, more
portable device designs are taking
advantage of the power-supply provisions of the USB speciication—hosts
can supply up to 500mA at a nominal
5V—to power the portable device and
charge its batteries. The most effective
use of the USB-limited 500mA requires
a USB-compliant battery charger and
well-designed PowerPath™ controls.
USB Power Speciications
USB power speciications require that
a Li-Ion battery charger is able to operate at input voltages as low as 4.75V
(ignoring resistive drops in the cable
and connectors which further reduce
this value to 4.4V), has a low current
standby mode, and that it limits the
total current drawn from the USB
power port to 500mA.
The LTC4056 provides a unique
feature allowing it to work well with
USB power. The undervoltage charge
current limiting function automatically reduces charge current if the
input supply voltage drops to approxiVBUS
USBINPUT
R1
750Ω
mately 4.575V. This feature prevents
resistive drops from lowering the USB
voltage below approximately 4.575V.
Typically, if a battery charger is connected to a particularly resistive USB
cable, the USB voltage drops below
the charger’s undervoltage lockout
threshold as soon as charge current
is turned on. This causes the charger
to turn off, the USB supply voltage
rebounds, and the cycle repeats. If an
LTC4056 is connected to a particularly resistive USB cable, the charge
current is reduced to ensure that the
input voltage does not drop below
the undervoltage lockout threshold.
In fact, charge current is adjusted to
maintain the USB voltage at or above
the undervoltage charge current limit
voltage of approximately 4.575V.
The TIMER/SHDN pin of the
LTC4056 can be used to reduce its
supply current to about 40µA allowing
it to meet the USB low current standby
mode speciication.
The inal USB requirement is that
the device cannot draw more the
500mA from the USB port. Careful PowerPath design is required to
eficiently meet this requirement.
LTC4056
VCC
TIMER/SHDN ISENSE
BAT
PROG
C1
1µF
C4
1µF
R2
1.87k
R5
0.5Ω
Q1
ZXT1M322
DRIVE
GND
C3
1µF
SYSTEM
VOLTAGE
+
Figure 1. Basic USB charger solution
36
Figure 1 shows a basic USB solution. This solution draws system
power directly from the battery as it
is charging. Since the battery charger
is the only system on the device that
draws current directly from the USB
port, the current limit is set simply
by programming the battery charge
current. For instance, if the battery
charger is programmed to charge at
490mA and the system load is 140mA,
then 350mA is effectively used to
charge the battery.
This design works within the conines
of the USB speciication, but it does
not maximize eficiency. Here’s why.
Consider an application with a buck
switching regulator that needs to provide a 1.8V supply at 300mA. Powering
the buck regulator directly from the
battery (at a nominal voltage of 3.85V)
would require approximately 140mA,
leaving 350mA to charge the battery
(assuming the same 490mA charge
current as above). On the other hand,
powering the buck regulator from the
USB supply (nominally 5V) would require just 110mA leaving 380mA to
charge the battery, 30mA more. This
additional 10% charge current can
reduce the battery charge time by
about 10%.
PowerPath Solution
RED
CHRG
Basic Solution
Li-Ion
Figure 2 shows an application allowing
the peripheral to draw current from
the USB supply when it is present,
and otherwise, draw current from
the battery. The LTC4056 actually
regulates the current output from
the ISENSE pin (rather than the BAT
pin current). This feature allows the
500mA maximum USB power port
consumption to be easily enforced
by tying all system loads to the ISENSE
pin and programming the charger to
Linear Technology Magazine • September 2003
DESIGN IDEAS
USB
+
–
R1
750Ω
RED
LTC4056
CHRG
VCC
M2B
1/2 IRF7329
TIMER/SHDN ISENSE
ON 0FF
M1
2N7002
C1
1µF
BAT
R2
1.87k
Q1
ZXT1M322
DRIVE
PROG
C4
4.7µF
R5
0.5Ω
GND
M2A
1/2 IRF7329
BAT
+
–
C3
1µF
+
C2
0.1µF
Li-Ion
VIN SENSE
LTC4412
GND
GATE
CTL
SYSTEM
VOLTAGE
R3
470k
STAT
Figure 2. Complete USB PowerPath control and battery charger solution
supply just under 500mA (in Figure 2
the charger is programmed for 490mA).
The total impedance between the VCC
pin and ISENSE pin is typically 0.2Ω, so
the maximum drop is just 100mV (at
500mA) allowing the peripheral device
to operate at a voltage signiicantly
higher than a single Li-Ion battery
when the USB supply is present.
It is important to keep in mind that
the LTC4056 can only control charge
current. If the system load is less than
500mA, then the LTC4056 simply reduces the charge current by an amount
equal to the system load current. For
instance, if the system load is 110mA,
then the charge current is reduced
from 490mA to 380mA to keep the total
USB input current at 490mA, thereby
meeting the speciication. The 110mA
system load, however, is now being
provided at approximately 5V rather
than the battery voltage. Assuming a
nominal battery voltage of 3.85V, the
circuit in Figure 2 can provide approximately 23% more power to the system
than the circuit in Figure 1 for a given
battery charge current.
LTC3252, continued from page 33
charge transfer reactivates once the
junction temperature drops back to approximately 150°C. The LTC3252 can
cycle in and out of thermal shutdown,
without latch-up or damage, until the
fault condition is removed.
The EN1 and EN2 pins are used to
individually enable OUT1 and OUT2
respectively. When both EN pins are
low the outputs become high impedance and all control circuitry is
Linear Technology Magazine • September 2003
Of course, if the system load is increased beyond 500mA the LTC4056
will reduce the charge current to zero,
and all of the system load will be provided by the USB input. This scenario
violates the USB power speciication.
In order to avoid this situation, it is
important to ensure that the system
load never exceeds 500mA.
Note that even the CHRG LED is
connected to ISENSE. This is a good
example of a peripheral load current. When the LTC4056 is charging
a battery, the CHRG pin is pulled low
drawing 4mA to 5mA through R1. This
load current reduces the amount of
current delivered to the battery by an
equal amount.
To ensure that the system voltage
is always present (even when USB
power is not), the LTC4412 provides
automatic switchover of the system
load between a battery and the USB
input supply. This feature reduces the
current drain on the battery to just a
few microamps when a USB input is
present. Figure 2 shows a dual FET
solution to minimize voltage drop
between the USB input voltage and
the system voltage (a Schottky diode
can also be used in place of M2B).
The combination of the LTC4412 and
M2A forms an ideal diode from BAT to
SYSTEMVOLTAGE. M2B serves as a
switch that is ON when the ideal diode
is not conducting and OFF otherwise.
Therefore, as long as the USB input is
present and the voltage on the ISENSE
pin is higher than BAT, M2B is ON
and M2A is OFF. As soon as the USB
input supply drops below the battery
voltage, M2A turns on and acts as an
ideal diode.
disabled leaving only a few nanoamps
of supply current. The LTC3252 includes a soft-start feature that limits
the inrush currents required to charge
the output capacitor when an output
is enabled, thereby minimizing input
supply transients caused by the power
on phase of the IC. The soft-start is
implemented whenever an output is
brought out of shutdown.
Conclusion
Conclusion
The USB speciication allows for up
to 500mA of current to be delivered
from the USB port. Portable devices
are increasingly using the USB power
provided by a host computer to power
the device system bus and to charge
batteries. When used in a PowerPath
control coniguration, the LTC4056
makes the most of this 500mA to
eficiently charge the battery, even
while the system draws power from
the USB.
The LTC3252 is well suited for medium
to low power step-down applications
requiring multiple low noise outputs
in a small footprint. It is an especially
good match for single cell Li-Ion and
multi-cell NiMH/NiCd battery powered applications and where EMI is
a concern.
37
NEW DEVICE CAMEOS
New Device Cameos
Data/Clock Hot Swap
Devices Provide Capacitance
Buffering, Level Translation
on 2-Wire Bus Systems
The LTC4300A-1 and LTC4300A-2
enable I/O card insertion into a live
backplane without corruption of the
data and clock lines (SDA and SCL)
for I2C and SMBus systems. The
LTC4300A is typically used at the
edge of a peripheral card, with two of
its pins, SDAOUT and SCLOUT, connected to the data and clock buses on
the card. When the card is plugged into
a live backplane, two other pins, SDAIN
and SCLIN connect to the data and
clock buses on the backplane. Control
circuitry provides a glitch-free connection by preventing the backplane
buses from being connected to the card
buses until data transactions on both
sides are complete.
Once the backplane is connected to
the card, the functionality of the SDAIN
and SDAOUT pins is identical. A low
forced on either pin at any time results
in both pin voltages being low. SDAIN
and SDAOUT enter a logic high state
only when all devices on both SDAIN
and SDAOUT force a high. The same
is true for SCLIN and SCLOUT. This
important feature ensures that clock
stretching, arbitration, synchronization, and data acknowledge always
work, regardless of how devices in the
system are tied to the LTC4300A-1 or
LTC4300A-2.
Another important feature of the
connection circuitry is that, while it
joins the two buses together, it still
maintains electrical isolation between
them, thus providing capacitance buffFor further information on any
of the devices mentioned in this
issue of Linear Technology, use
the reader service card or call the
LTC literature service number:
1-800-4-LINEAR
Ask for the pertinent data sheets
and Application Notes.
38
ering for both sides. This means that
devices on the backplane must drive
only the backplane capacitance plus
the low capacitance of the LTC4300A
(around 10pF). The LTC4300A drives
the capacitance of the rest of the I/O
card. Likewise, devices on the card
must only drive the capacitance of
the card plus the low capacitance of
the LTC4300A. The LTC4300A drives
the capacitance on the backplane. The
LTC4300A is capable of driving capacitive loads ranging from 0pF to 1000pF
on all of its data and clock pins.
Other features of the part include:
rise time accelerator circuitry, which
allows the use of weaker DC pull-up
currents while still meeting rise time
requirements; and pre-charge circuitry, which initializes the data and
clock buses to 1V before card insertion.
The LTC4300A2-1 features a digital
ENABLE input pin, which disconnects
the backplane from the card and forces
the part into a low current mode; and
an open drain READY output pin,
which indicates whether the backplane and card sides are connected
together. The LTC4300A-2 features
independent power supply inputs
for the backplane and card, enabling
level translation between 3.3V and
5V systems. The LTC4300A-1 and
LTC4300A-2 are both available in a
small 8-pin MSOP package.
High Speed, High Voltage,
High Side Gate Driver
The LTC4440 is a high frequency, high
side N-channel MOSFET gate driver
that is designed to operate in applications with input voltages up to 80V. It
is able to withstand, and continues to
function through 100V input supply
transients, making it ideally suited
for use in telecommunications power
supplies.
The LTC4440 receives a ground-referenced, low voltage input logic signal
that is internally level-shifted to drive
an external high-side MOSFET. The
input stage has TTL/CMOS compatible
thresholds with 350mV of hysteresis.
The LTC4440 has propagation delays
from input to output of less than 30ns,
making it ideal for high frequency applications.
Designed to drive standard threshold MOSFETS, the LTC4440 operates
with a bootstrapped supply voltage of
8V to 15V. Its powerful drive capability
reduces switching losses in MOSFETs
with high gate capacitances. Its pullup has a peak output current of 2.4A,
and its pull-down has an output impedance of 1.6Ω. The LTC4440 can
drive a 1000pF load with a 10ns rise
time and 7ns fall time with 12V of
gate drive.
To protect the external MOSFET
from inadequate supply voltages, the
LTC4440 features both high-side and
low-side undervoltage lockout circuits
that disable the external MOSFET
when activated.
This rugged architecture, high
speed, and powerful drive capability
are available in a 6-lead low proile
ThinSOT package or a thermally enhanced 8-lead MSOP package.
Programmable Supply
Current, Rail-to-Rail Output,
Current Feedback Ampliier
The LT6210 is a current feedback ampliier with externally programmable
supply current and bandwidth ranging
from 10MHz at 300µA to 200MHz at
6mA. It features a low distortion railto-rail, C-Load™-stable output stage,
700V/µs slew rate and a minimum
output current drive of 75mA.
The LT6210 operates on supplies
as low as a single 3V and up to either
12V or ±6V. The I SET pin allows for
the optimization of quiescent current
for speciic bandwidth, distortion or
slew rate requirements. Regardless
of supply voltage, the supply current
is programmable from just 300µA to
6mA with an external resistor or current source.
The LT6210 is manufactured on
Linear Technology’s proprietary low
voltage complementary bipolar process and is available in the low proile
(1mm) 6-lead ThinSOT package.
Linear Technology Magazine • September 2003
DESIGN TOOLS
2003 Databooks
Linear Technology is pleased to announce the availability
of seven databooks organized by product family. This set
supersedes all previous Linear databooks. Each databook contains all related product data sheets, selection
guides, QML/space information, package information,
appendices, and a complete reference to all of the other
family databooks.
For more information, or to obtain any of the databooks,
contact your local sales ofice (see the back of this magazine), or visit www.linear.com.
Ampliiers —
• Operational Ampliiers
• Instrumentation Ampliiers
• Application Speciic Ampliiers
References, Filters, Comparators, Special
Functions, RF & Wireless —
• Voltage References
• Monolithic Filters
• Comparators
• Special Functions
• RF & Wireless
Monolithic Switching Regulators —
• Micropower Switching Regulators
• Continuous Switching Regulators
Switching Regulator Controllers —
• DC/DC Controllers
• Digital Voltage Programmers
• Off-Line AC/DC Controllers
Linear Regulators, Power Management —
• Linear Regulators
• Charge Pump DC/DC Converters
• Battery Charging & Management
• Power Switching & MOSFET Drivers
• Hot Swap Controllers
• PCMCIA Power Controllers
• CCFL Backlight Converters
• Special Power Functions
Data Converters —
• Analog-to-Digital Converters
• Digital-to-Analog Converters
• Switches & Multiplexers
Interface, Supervisors —
• RS232/562
• RS485
• Mixed Protocol
• SMBus/I2C
• Supervisors
Linear Technology Magazine • September 2003
DESIGN TOOLS
Applications Handbooks
Linear Applications Handbook, Volume I — Almost a
thousand pages of application ideas covered in depth by
40 Application Notes and 33 Design Notes. This catalog
covers a broad range of real world linear circuitry. In
addition to detailed, systems-oriented circuits, this
handbook contains broad tutorial content together
with liberal use of schematics and scope photography.
A special feature in this edition includes a 22-page section on SPICE macromodels.
Linear Applications Handbook, Volume II — Continues
the stream of real world linear circuitry initiated by Volume
I. Similar in scope to Volume I, this book covers Application Notes 40 through 54 and Design Notes 33 through
69. References and articles from non-LTC publications
that we have found useful are also included.
Linear Applications Handbook, Volume III —
This 976-page handbook includes Application Notes 55
through 69 and Design Notes 70 through 144. Subjects
include switching regulators, measurement and control
circuits, ilters, video designs, interface, data converters,
power products, battery chargers and CCFL inverters.
An extensive subject index references circuits in Linear
data sheets, design notes, application notes and Linear
Technology magazines.
www.linear.com and
the Linear Online Store
www.linear.com — Customers can quickly and conveniently ind and retrieve the latest technical information
covering the Company’s products on Linear’s website.
Located at www.linear.com, the site allows searching
of data sheets, application notes, design notes, Linear
Technology magazine issues and other LTC publications.
The LTC website simpliies searches by providing three
separate search engines. The irst is a quick search function that provides a complete list of all documentation for
a particular word or part number. There is also a product
function tree that lists all products in a given product family. The most powerful, though, is the parametric search
engine. It allows engineers to specify key parameters
and speciications that satisfy their design requirements.
Other areas within the site include a sales ofice directory,
press releases, inancial information, quality assurance
documentation, and corporate information.
Linear Direct Online Store — The Linear Online Store at
www.linear.com now offers a simple way to order LTC
products factory direct. The new store accepts major
credit cards and allows customers to create personalized
accounts where they can check order history, shipment
information and reorder products. The maximum quantity per order has increased to 500.
Brochures
Power Management & Wireless Solutions for Handheld
Products — The solutions in this product selection guide
solve real-life problems for cell phones, digital cameras,
PDAs and other portable devices. Circuits are shown for
Li-Ion battery chargers, battery managers, USB support,
system power regulation, display drivers, white LED
drivers, photolash chargers, DC/DC converters, SIM
and smart card interfaces, photolash chargers, and RF
PA power supply and control. All solutions are designed
to maximize battery run time, save space and reduce
EMI where necessary—important considerations when
designing circuits for handheld devices.
Software
SwitcherCAD™ III/LTC SPICE — LTC SwitcherCAD III is a
fully functional SPICE simulator with enhancements and
models to ease the simulation of switching regulators.
This SPICE is a high performance circuit simulator and
integrated waveform viewer, and also includes schematic
capture. Our enhancements to SPICE result in much
faster simulation of switching regulators than is possible with normal SPICE simulators. SwitcherCAD III
includes SPICE, macromodels for 80% of LTC’s switching
regulators and over 200 op amp models. It also includes
models of resistors, transistors and MOSFETs. With this
SPICE simulator, most switching regulator waveforms
can be viewed in a few minutes on a high performance
PC. Circuits using op amps and transistors can also be
easily simulated. Download at www.linear.com
FilterCAD™ 3.0 — FilterCAD 3.0 is a computer aided design program for creating ilters with Linear Technology’s
ilter ICs. FilterCAD is designed to help users without
special expertise in ilter design to design good ilters
with a minimum of effort. It can also help experienced
ilter designers achieve better results by playing “what if”
with the coniguration and values of various components
and observing the results. With FCAD, you can design
lowpass, highpass, bandpass or notch ilters with a
variety of responses, including Butterworth, Bessel,
Chebychev, elliptic and minimum Q elliptic, plus custom
responses. Download at www.linear.com
SPICE Macromodel Library — This library includes LTC
op amp SPICE macromodels. The models can be used
with any version of SPICE for analog circuit simulations.
These models run on SwitcherCAD III/LTC SPICE.
Noise Program — This PC program allows the user to
calculate circuit noise using LTC op amps, determine
the best LTC op amp for a low noise application, display
the noise data for LTC op amps, calculate resistor noise
and calculate noise using specs for any op amp.
39
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© 2003 Linear Technology Corporation/Printed in U.S.A./36.5K
Linear Technology Magazine • September 2003