ICS858020 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-CML FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS858020 is a high speed 1-to-4 Differentialto-CML Fanout Buffer and is a member of the HiPerClockS™ HiPerClockS™ family of high performance clock solutions from ICS. The ICS858020 is optimized for high speed and very low output skew, making it suitable for use in demanding applications such as SONET, 1 Gigabit and 10 Gigabit Ethernet, and Fibre Channel. The internally terminated differential input and VREF_ AC pin allow other differential signal families such as LVDS, LVHSTL and CML to be easily interfaced to the input with minimal use of external components. The ICS858020 is packaged in a small 3mm x 3mm 16-pin VFQFN package which makes it ideal for use in space-constrained applications. • Four differential CML outputs ICS • One LVPECL differential clock input • IN, nIN pair can accept the following differential input levels: LVPECL, LVDS, CML, SSTL • Maximum output frequency: 3.2GHz • Output skew: 30ps (maximum) • Part-to-part skew: 225ps (maximum) • Additive phase jitter, RMS: <0.03ps (typical) • Propagation delay: 600ps (maximum) • Operating voltage supply range: VCC = 2.375V to 3.63V, VEE = 0V • -40°C to 85°C ambient operating temperature • Available in both standard (RoHS5) and lead-free (RoHS 6) packages VREF_AC VCC nQ0 16 15 14 13 12 Q1 nQ1 10 Q2 nIN 4 9 nQ2 5 6 7 8 VCC 11 Q3 VT 2 VREF_AC 3 nQ3 Q1 nQ1 IN 1 VEE IN VT nIN Q0 nQ0 Q0 PIN ASSIGNMENT VEE BLOCK DIAGRAM ICS858020 16-Lead VFQFN 3mm x 3mm x 0.95 package body K Package Top View Q2 nQ2 Q3 nQ3 858020AK 1 REV. A DECEMBER 10, 2007 ICS858020 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-CML FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1 IN Input Non-inver ting LVPECL differential clock input. This input internally terminates with 50Ω to the VT pin. 2 VT Input Termination input. 3 VREF_AC Output 4 nIN Input Inver ting differential LVPECL clock input. This input internally terminates with 50Ω to the VT pin. 5, 16 VEE Power Negative supply pin. 6, 7 nQ3, Q3 Output Differential output pair. CML interface levels. Reference voltage for AC-coupled applications. This output biases to VCC - 1.38V. 8, 13 VCC Power Positive supply pins. 9, 10 nQ2, Q2 Output Differential output pair. CML interface levels. 11, 12 14, 15 nQ1, Q1 nQ0, Q0 Output Output Differential output pair. CML interface levels. Differential output pair. CML interface levels. 858020AK 2 REV. A DECEMBER 10, 2007 ICS858020 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-CML FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V (CML mode, VEE = 0) Inputs, VI -0.5V to VCC + 0.5 V Outputs, IO Continuous Current Surge Current 20mA 40mA Input Current, IN, nIN ±50mA VT Current, IVT ±100mA Input Sink/Source, IREF_AC ± 0.5mA NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Operating Temperature Range, TA -40°C to +85°C Storage Temperature, TSTG -65°C to 150°C Package Thermal Impedance, θJA 51.5°C/W (0 lfpm) (Junction-to-Ambient) TABLE 2A. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.375V TO 3.6V; VEE = 0V Symbol Parameter VCC Positive Supply Voltage IEE Power Supply Current Test Conditions Minimum Typical 2.375 3.3 Maximum Units 3.6 V 135 mA TABLE 2B. DC CHARACTERISTICS, VCC = 2.375V TO 3.6V; VEE = 0V Symbol Parameter RIN Differential Input Resistance (IN, nIN) Test Conditions Minimum Typical Maximum Units IN to VT 40 50 60 Ω VIH Input High Voltage (IN, nIN) 1.2 VCC V VIL Input Low Voltage (IN, nIN) 0 VIH - 0.15 V VIN Input Voltage Swing; NOTE 1 0.15 2.8 V VDIFF_IN Differential Input Voltage Swing VREF_AC Reference Voltage VT_IN In-to-VT Voltage 0.3 VCC - 1.5 VCC - 1.4 3.4 V VCC - 1.3 V 1.5 V Units NOTE 1: Refer to Parameter Measurement Information, Input Voltage Swing diagram. TABLE 2C. CML DC CHARACTERISTICS, VCC = 2.375V TO 3.6V; VEE = 0V Symbol Parameter Conditions Minimum Typical Maximum VCC VOH Output High Voltage; NOTE 1 VCC - 0.020 VCC - 0.010 VOUT Output Voltage Swing 325 400 mV VDIFF_OUT Differential Output Voltage Swing 650 800 mV ROUT Output Source Impedance 40 50 60 V Ω NOTE 1: Outputs terminated with 100Ω across differential output pair. 858020AK 3 REV. A DECEMBER 10, 2007 ICS858020 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-CML FANOUT BUFFER TABLE 3. AC CHARACTERISTICS, VCC = 0V; VEE = -3.6V TO -2.375V OR VCC = 2.375 TO 3.6V; VEE = 0V Symbol Parameter fMAX Maximum Output Frequency Propagation Delay; (Differential); NOTE 1 Output Skew; NOTE 2, 4 t PD tsk(o) tsk(pp) tjit tR/tF Condition Minimum 350 15 Par t-to-Par t Skew; NOTE 3, 4 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section Output Rise/Fall Time Typical Maximum Units 3.2 GHz 575 ps 30 ps 225 ps <0.03 20% to 80% 60 ps 180 ps All parameters characterized at ≤ 1.2GHz unless otherwise noted. RL = 100Ω after each output pair. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. 858020AK 4 REV. A DECEMBER 10, 2007 ICS858020 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-CML FANOUT BUFFER ADDITIVE PHASE JITTER the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in 0 -10 Additive Phase Jitter at 155.52MHz = <0.03ps (typical) -20 -30 -40 SSB PHASE NOISE dBc/HZ -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1M 10M 100M OFFSET FROM CARRIER FREQUENCY (HZ) As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The de- 858020AK vice meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment. 5 REV. A DECEMBER 10, 2007 ICS858020 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-CML FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION 0V VCC SCOPE Qx Power Supply nIN VCC V CML Driver Cross Points IN V IH IN VEE V -3.3V ± 10% -2.5V ± 5% IL V EE OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL nQx PART 1 Qx nQx nQy nQy Qx PART 2 Qy Qy tsk(pp) tsk(o) PART-TO-PART SKEW OUTPUT SKEW nIN IN VDIF_IN VIN nQ0:nQ3 Q0:Q3 VIN, VOUT VDIFF_IN, VDIFF_OUT 400mV (typical) 800mV (typical) tPD PROPAGATION DELAY SINGLE ENDED & DIFFERENTIAL INPUT VOLTAGE SWING 80% 80% VSW I N G Clock Outputs 20% 20% tR tF OUTPUT RISE/FALL TIME 858020AK 6 REV. A DECEMBER 10, 2007 ICS858020 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-CML FANOUT BUFFER APPLICATION INFORMATION LVPECL INPUT WITH Ω TERMINATION INTERFACE (2.5V) BUILT-IN 50Ω The IN/nIN with built-in 50Ω terminations accepts LVDS, LVPECL, LVHSTL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VIH and VIL input requirements. Figures 1A to 1D show interface examples for the HiPerClockS IN/nIN input with built-in 50Ω terminations driven 3.3V or 2.5V by the most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use the termination they recommend. Please consult with the vendor of the driver component to confirm the driver termination requirements. 2.5V 2.5V 2.5V Zo = 50 Ohm Zo = 50 Ohm IN IN VT Zo = 50 Ohm nIN LVDS nIN Receiver With Built-In 50 Ohm Receiver With Built-In 50 Ohm 2.5V LVPECL R1 18 FIGURE 1A. HIPERCLOCKS IN/nIN INPUT WITH Ω DRIVEN BY AN LVDS DRIVER BUILT-IN 50Ω 2.5V VT Zo = 50 Ohm FIGURE 1B. HIPERCLOCKS IN/nIN INPUT WITH Ω DRIVEN BY AN LVPECL DRIVER BUILT-IN 50Ω 2.5V 2.5V 2.5V Zo = 50 Ohm Zo = 50 Ohm IN IN VT Zo = 50 Ohm nIN CML - Open Collector Zo = 50 Ohm VT nIN Receiver With Built-In 50 Ohm CML - Built-in 50 Ohm Pull-up Receiver With Built-In 50 Ohm FIGURE 1D. HIPERCLOCKS IN/nIN INPUT WITH Ω DRIVEN BY A CML DRIVER BUILT-IN 50Ω Ω PULLUP WITH BUILT-IN 50Ω FIGURE 1C. HIPERCLOCKS IN/nIN INPUT WITH Ω DRIVEN BY AN OPEN COLLECTOR BUILT-IN 50Ω CML DRIVER 2.5V 2.5V R1 25 Zo = 50 Ohm IN Zo = 50 Ohm VT nIN R2 SSTL 25 Receiver With Built-In 50Ω FIGURE 1E. HIPERCLOCKS IN/nIN INPUT WITH Ω DRIVEN BY AN SSTL DRIVER BUILT-IN 50Ω 858020AK 7 REV. A DECEMBER 10, 2007 ICS858020 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-CML FANOUT BUFFER Ω TERMINATION INTERFACE (3.3V) LVPECL INPUT WITH BUILT-IN 50Ω The IN /nIN with built-in 50Ω terminations accepts LVDS, LVPECL, LVHSTL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VIH and VIL input requirements. Figures 2A to 2D show interface examples for the HiPerClockS IN/nIN input with built-in 50Ω terminations driven 3.3V by the most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use the termination they recommend. Please consult with the vendor of the driver component to confirm the driver termination requirements. 3.3V 3.3V 3.3V Zo = 50 Ohm Zo = 50 Ohm IN IN Zo = 50 Ohm VT nIN nIN Receiver With Built-In 50 Ohm LVDS 3.3V Receiver With Built-In 50 Ohm LVPECL R1 50 FIGURE 2A. HIPERCLOCKS IN/nIN INPUT WITH Ω DRIVEN BY AN LVDS DRIVER BUILT-IN 50Ω FIGURE 2B. HIPERCLOCKS IN/nIN INPUT WITH Ω DRIVEN BY AN LVPECL DRIVER BUILT-IN 50Ω 3.3V 3.3V 3.3V Zo = 50 Ohm Zo = 50 Ohm IN IN Zo = 50 Ohm VT Zo = 50 Ohm VT Zo = 50 Ohm nIN CML- Open Collector nIN Receiver With Built-In 50 Ohm CML- Built-in 50 Ohm Pull-Up Receiver With Built-In 50 Ohm FIGURE 2D. HIPERCLOCKS IN/nIN INPUT WITH Ω DRIVEN BY A CML DRIVER BUILT-IN 50Ω Ω PULLUP WITH BUILT-IN 50Ω FIGURE 2C. HIPERCLOCKS IN/nIN INPUT WITH Ω DRIVEN BY A CML DRIVER BUILT-IN 50Ω WITH O PEN COLLECTOR 3.3V VT 3.3V R1 25 Zo = 50 Ohm IN Zo = 50 Ohm VT nIN SSTL R2 25 Receiver With Built-In 50 Ohm FIGURE 2E. HIPERCLOCKS IN/nIN INPUT WITH Ω DRIVEN BY AN SSTL DRIVER BUILT-IN 50Ω 858020AK 8 REV. A DECEMBER 10, 2007 ICS858020 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-CML FANOUT BUFFER SCHEMATIC EXAMPLE couple. This example shows the ICS858020 input driven by a 2.5V LVPECL driver with AC couple. The ICS858020 outputs are CML driver with built-in 50Ω pull up resistors. In this example, we assume the traces are long transmission line and the receiver is high input impedance without built-in matched load. An external 100Ω resistor across the receiver input is required. Figure 3 shows a schematic example of the ICS858020. This schematic provides examples of input and output handling. The ICS858020 input has built-in 50Ω termination resistors. The input can directly accept various types of differential signal without AC couple. If AC couple termination is used, the ICS858020 also provides VREF_AC pin for proper offset level after the AC 3.3V Zo = 50 + Zo = 50 R3 100 3.3V 16 15 14 13 2.5V Zo = 50 C5 1 2 3 4 Zo = 50 C6 R2 100 Q1 nQ1 Q2 nQ2 IN VT VREF_AC nIN 12 11 10 9 3.3V 5 6 7 8 R1 100 100 Ohm Dif f erential VEE nQ3 Q3 VCC LVPECL - VEE Q0 nQ0 VCC U1 ICS858020 C1 0.1u 3.3V C2 0.1u Zo = 50 + Zo = 50 R4 100 - 100 Ohm Dif f erential FIGURE 3. ICS858020 APPLICATION SCHEMATIC EXAMPLE 858020AK 9 REV. A DECEMBER 10, 2007 ICS858020 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-CML FANOUT BUFFER VFQFN EPAD THERMAL RELEASE PATH In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in Figure 4. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/ electrical performance. Sufficient clearance should be designed on the PCB between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. “heat pipes”) are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These recommendations are to be used as a guideline only. For further information, refer to the Application Note on the Surface Mount Assembly of Amkor’s Thermally/Electrically Enhance Leadfame Base Package, Amkor Technology. While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. PIN PIN PAD SOLDER EXPOSED HEAT SLUG GROUND PLANE SOLDER LAND PATTERN THERMAL VIA PIN PIN PAD (GROUND PAD) FIGURE 4. P.C.ASSEMBLY FOR EXPOSED PAD THERMAL RELEASE PATH –SIDE VIEW (DRAWING NOT TO SCALE) 858020AK 10 REV. A DECEMBER 10, 2007 ICS858020 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-CML FANOUT BUFFER RELIABILITY INFORMATION TABLE 4. θJAVS. AIR FLOW TABLE FOR 16 LEAD VFQFN θJA at 0 Air Flow (Linear Feet per Minute) 0 51.5°C/W Multi-Layer PCB, JEDEC Standard Test Boards TRANSISTOR COUNT The transistor count for ICS858020 is: 28 Pin compatible with SY58020U 858020AK 11 REV. A DECEMBER 10, 2007 ICS858020 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-CML FANOUT BUFFER PACKAGE OUTLINE - K SUFFIX FOR 16 LEAD VFQFN (Ref.) Seating Plane (R ef.) A1 Index Area ND & NE Even (ND-1)x e L A3 N N Anvil Singula tion e (Typ.) 2 If ND & NE 1 are Even 2 E2 OR (NE -1)x e (Re f.) E2 2 Top View b A (Ref.) D e ND & NE Odd 0. 08 Chamfer 4x 0.6 x 0.6 max OPTIONAL C D2 2 Thermal Base D2 C TABLE 5. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL MINIMUM A 0.80 A1 0 1.0 0.05 0.25 Reference A3 b MAXIMUM 16 N 0.18 0.30 e 0.50 BASIC ND 4 NE 4 D 3.0 D2 0.25 1.25 3.0 E E2 0.25 1.25 L 0.30 0.50 Reference Document: JEDEC Publication 95, MO-220 858020AK 12 REV. A DECEMBER 10, 2007 ICS858020 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-CML FANOUT BUFFER TABLE 6. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS858020AK 020A 16 Lead VFQFN Tube -40°C to 85°C ICS858020AKT 020A 16 Lead VFQFN 2500 Tape & Reel -40°C to 85°C ICS858020AKLF 20AL 16 Lead "Lead-Free" VFQFN Tube -40°C to 85°C ICS858020AKLFT 20AL 16 Lead "Lead-Free" VFQFN 2500 Tape & Reel -40°C to 85°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. 858020AK 13 REV. A DECEMBER 10, 2007 ICS858020 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-CML FANOUT BUFFER REVISION HISTORY SHEET Rev Table Page A T6 12 Ordering Information Table - correct Shipping Packaging from Tray to Tube. 3/17/06 A T6 12 10 12 13 Ordering Information Table - corrected marking from 820A to 020A. Added VFQFN EPAD Thermal Release Path section. Updated VFQFN package outline. Ordering Information Table - added Lead-Free marking. 4/24/06 A T6 858020AK Description of Change 14 Date 12/10/07 REV. A DECEMBER 10, 2007